ninja: Entering directory `out/gn'
[0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix)
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
-- Testing: 27910 tests, 64 workers --
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (2 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 0
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 1
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ac1678beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac16788e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac1678c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e2e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e2e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e2e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e2e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac16721bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac16721a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac167068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac163b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac163b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e2e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e2e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e2e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac163b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (4 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, half noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca half, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store half %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load half, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync no
# | ...
# `---data was truncated (10240/10512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005595fe8ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595fe8fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595fe90062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8c9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8c9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8c9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8c9e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595fe895bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595fe895a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595fe87a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595fe529e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595fe529b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8c9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8c9e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8c9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595fe529a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (5 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 0
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 1
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 3
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005584dc609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584dc606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584dc60a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddcbc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddcbc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddcbc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddcbc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584dc59fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584dc59fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584dc5848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584dc233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584dc233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddcbc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddcbc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddcbc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584dc233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (7 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005561f07e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561f07e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561f07e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd75133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd7518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd75133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd7511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561f0779bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561f0779a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561f075e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561f040de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561f040db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd7511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd7511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd7511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561f040da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (8 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dd0939feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd0939ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd093a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb55e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb55ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb55e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb55e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd09335bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd09335a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd0931a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd08fc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd08fc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb55e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb55e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb55e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd08fc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (29 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate2_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %1, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561f85fbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f85fbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f85fbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd51f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd51f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd51f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd51f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f85f54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f85f54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f85f398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f85be8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f85be8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd51f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd51f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd51f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f85be8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (65 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate4_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1, <vscale x 16 x i1> %x2, <vscale x 16 x i1> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   %x2.addr = alloca <vscale x 16 x i1>, align 2
# |   %x4.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   store <vscale x 16 x i1> %x2, ptr %x2.addr, align 2
# |   store <vscale x 16 x i1> %x4, ptr %x4.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %x2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x4.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6, <vscale x 16 x i1> %3, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %7
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056042bf34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056042bf31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056042bf3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cc1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cc18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cc1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cc1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056042becabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056042becaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056042beaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056042bb5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056042bb5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cc1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cc18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cc18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056042bb5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (73 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 
# | ...
# `---data was truncated (10240/172384) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005628622a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628622a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628622a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f315a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f315a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f315a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f315a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562862239bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562862239a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056286221e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562861ecde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562861ecdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f315a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f315a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f315a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562861ecda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (74 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2q_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svld2q_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2q_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | d
# | ...
# `---data was truncated (10240/75038) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b8b63e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8b63e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8b63e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe63fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe63faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe63fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe63fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8b6379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8b6379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8b635e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8b600de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8b600db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe63fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe63fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe63fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8b600da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (83 of 27910)
******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x half> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x float> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x double> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x bfloat> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055cb3a090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb3a08de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb3a09162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfe9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfe998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfe9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfe991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb3a026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb3a026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb3a00b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb39cbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb39cbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfe991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfe991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfe991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb39cbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (84 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta
# | ...
# `---data was truncated (10240/10820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557bbf507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bbf504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bbf50862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7d8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7d818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7d8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7d811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bbf49dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bbf49da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bbf4828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bbf131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bbf131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7d811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7d811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7d811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bbf131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (85 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# | 
# | ...
# `---data was truncated (10240/23662) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055aeabe5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aeabe57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aeabe5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c4f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c4f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aeabdf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aeabdf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aeabdd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aeaba84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aeaba84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c4f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aeaba84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (86 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d25b30deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d25b30ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d25b30e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ab831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d25b2a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d25b2a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d25b2888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d25af37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d25af37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44ab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ab8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d25af37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (87 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 4)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 5)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 2)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 3)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svextq_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svextq_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 2)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svextq_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svextq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 6)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr,
# | ...
# `---data was truncated (10240/11061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005605271f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605271f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605271f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e51505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e5155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e51505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e514ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056052718abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056052718aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056052716f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560526e1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560526e1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e514eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e514ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e514ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560526e1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (88 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d9209bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9209b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9209bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57ba505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57ba55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57ba505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57ba4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d920951bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d920951a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9209368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9205e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9205e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57ba4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57ba4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57ba4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9205e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (89 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 7)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x
# | ...
# `---data was truncated (10240/11356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005647806baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647806b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647806bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba81b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba81b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba81b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba81b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564780650bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564780650a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647806358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647802e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647802e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba81b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba81b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba81b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647802e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (90 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 7)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560115cdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560115cdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560115ce062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c10e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c10ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c10e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c10e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560115c75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560115c75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560115c5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560115909e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560115909b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c10e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c10e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c10e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560115909a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (95 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563c58dc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c58dbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c58dc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7696f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7696f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7696f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7696f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c58d56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c58d56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c58d3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c589eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c589eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7696f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7696f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7696f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c589eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (100 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bd1ce52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd1ce4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd1ce5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd1cde8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd1cde8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd1cdcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd1ca7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd1ca7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd1ca7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (103 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   ret <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/58597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560c976f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c976f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c976f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbba9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbba9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbba9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbba9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9768ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c9768ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c976738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c97322e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c97322b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbba9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbba9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbba9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c97322a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (109 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcompact_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcompact_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564f3195deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f3195ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f3195e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1976533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f197658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1976533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f197651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f318f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f318f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f318d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f31587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f31587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f197651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f197651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f197651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f31587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (114 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 2)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_laneq_f16(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %0, i32 4)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_laneq_f32(<vscale x 4 x float> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %0, i32 1)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_laneq_f64(<vscale x 2 x double> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %0, i32 1)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_laneq_bf16(<vscale x 8 x bfloat> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %0, i32 3)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 1)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005588118e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588118e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588118e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2de1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2de1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2de1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2de1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055881187dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055881187da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588118628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558811511e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558811511b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2de1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2de1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2de1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558811511a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (116 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d627880eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d62787de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d62788162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d627816bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d627816a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6277fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6274aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6274aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6274aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (118 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055737672feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055737672ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055737673062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36c1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36c1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36c1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36c1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573766c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573766c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573766aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557376359e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557376359b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36c1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36c1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36c1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557376359a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (119 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrun_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000559f4bfa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f4bf9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f4bfa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4971133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4971133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f4bf37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f4bf37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f4bf1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f4bbcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f4bbcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f497111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f4bbcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (122 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_u8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_u16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_u32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_u64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_s8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_s16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_s32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_s64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbxq_f16(<vscale x 8 x half> %passthru, <vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbxq_f32(<vscale x 4 x float> %passthru, <vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.tbxq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/14102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564a18d42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a18d3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a18d4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb41449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb414a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb41449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb41431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a18cd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a18cd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a18cbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a1896ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a1896cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb41432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb414330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb414330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a1896ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (123 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055989c25eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055989c25be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055989c25f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055989c1f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055989c1f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055989c1d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055989be88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055989be88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbd311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055989be88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (126 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cf940b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf940b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf940b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff86bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff86bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff86bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff86bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf9404abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf9404aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf9402f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf93cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf93cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff86bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff86bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff86bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf93cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (128 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclamp_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svclamp_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svclamp_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b2b013ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2b0139e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2b013d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2b00d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2b00d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2b00b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2afd66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2afd66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2afd66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (130 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1
# | ...
# `---data was truncated (10240/37926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056546fd27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056546fd24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056546fd2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc749649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7496a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc749649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc749631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056546fcbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056546fcbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056546fca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056546f951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056546f951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc749632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7496330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7496330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056546f951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (131 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_u8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_u16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_u32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_s64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_u64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svreinterpret_f16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svreinterpret_bf16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svreinterpret_f32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x float>
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svreinterpret_f64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 t
# | ...
# `---data was truncated (10240/168193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x00005615bfa4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615bfa4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615bfa5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f551b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f551b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f551b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f551b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615bf9e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615bf9e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615bf9ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615bf679e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615bf679b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f551b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f551b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f551b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615bf679a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (133 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpand_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svexpand_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpand_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, al
# | ...
# `---data was truncated (10240/12168) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005618e2ce0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618e2cdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618e2ce162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff57f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff57f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff57f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff57f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618e2c76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618e2c76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618e2c5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618e290ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618e290ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff57f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff57f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff57f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618e290aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (137 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmsb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b0ac930eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0ac92de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0ac93162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f262e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f262e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f262e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f262e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0ac8c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0ac8c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0ac8ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0ac55ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0ac55ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f262e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f262e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f262e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0ac55aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (138 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/77120) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e966226eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e966223e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e96622762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde1f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde1f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde1f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde1f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9661bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9661bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9661a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e965e50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e965e50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde1f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde1f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde1f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e965e50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (147 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef45ab2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef45aafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef45ab362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33d7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33d70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33d7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33d7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef45a48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef45a48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef45a2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef456dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef456dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33d7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33d70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33d70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef456dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (148 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpa_f16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpa_f32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svexpa_f64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e804063eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e804060e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e80406462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6c7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6c778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6c7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6c771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e803ff9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e803ff9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e803fde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e803c8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e803c8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6c771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6c771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6c771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e803c8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (149 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vsc
# | ...
# `---data was truncated (10240/72568) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005586017f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586017f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586017f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5436d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5436d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5436d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5436ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558601789bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558601789a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055860176e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055860141de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055860141db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5436ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5436cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5436cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055860141da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (150 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmla_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056148c61deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056148c61ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056148c61e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5bf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056148c5b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056148c5b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056148c5988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056148c247e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056148c247b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056148c247a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (151 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vsca
# | ...
# `---data was truncated (10240/53696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056107f17aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056107f177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056107f17b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf1c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf1c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf1c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf1c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056107f110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056107f110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056107f0f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056107eda4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056107eda4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf1c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf1c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf1c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056107eda4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (152 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmad_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005634f6e0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634f6e0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634f6e1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8072a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8072aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8072a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8072a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634f6da5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634f6da5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634f6d8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634f6a39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634f6a39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8072a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8072a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8072a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634f6a39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (157 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055af6dca0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af6dc9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af6dca162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa83a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa83a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa83a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af6dc36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af6dc36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af6dc1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af6d8cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af6d8cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa83a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa83a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa83a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af6d8caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (158 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/63749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000563a3d8a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a3d89fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a3d8a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a13849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a138a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a13849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a13831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a3d838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a3d838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a3d81d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a3d4cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a3d4ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a13832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a138330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a138330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a3d4cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (159 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmin_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmin_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b163b57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b163b54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b163b5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f304db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f304db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f304db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f304db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b163aedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b163aeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b163ad28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b163781e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b163781b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f304db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f304db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f304db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b163781a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (160 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splat
# | ...
# `---data was truncated (10240/24132) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056404cc71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056404cc6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056404cc7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68b6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68b658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68b6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68b651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056404cc07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056404cc07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056404cbec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056404c89be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056404c89bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68b651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68b651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68b651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056404c89ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (164 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.a
# | ...
# `---data was truncated (10240/28771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562a4f2e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a4f2dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a4f2e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f853a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f853a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f853a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f853a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a4f277bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a4f277a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a4f25c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a4ef0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a4ef0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f853a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f853a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f853a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a4ef0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (165 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef5611beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef56118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef5611c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa79b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa79b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa79b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa79b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef560b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef560b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef560968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef55d45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef55d45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa79b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa79b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa79b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef55d45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (166 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | 
# | ...
# `---data was truncated (10240/178306) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005596a904deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596a904ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596a904e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdff9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdff9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdff9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdff9a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596a8fe3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596a8fe3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596a8fc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596a8c77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596a8c77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdff9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdff9a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdff9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596a8c77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (167 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 2
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 2
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue 
# | ...
# `---data was truncated (10240/21007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e1dcda1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1dcd9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1dcda262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc25b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc25b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc25b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc25b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1dcd37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1dcd37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1dcd1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1dc9cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1dc9cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc25b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc25b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc25b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1dc9cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (169 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call
# | ...
# `---data was truncated (10240/48703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005593d2756eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593d2753e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593d275762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d5a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d5a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d5a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d5a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593d26ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593d26eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593d26d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593d2380e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593d2380b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d5a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d5a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d5a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593d2380a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (170 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005629230f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629230eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629230f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ca5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ca538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ca5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ca531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562923087bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562923087a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056292306c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562922d1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562922d1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ca531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ca531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ca531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562922d1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (172 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svget2_f16(<vscale x 8 x half> %tuple.coerce0, <vscale x 8 x half> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %tuple.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svget2_f32(<vscale x 4 x float> %tuple.coerce0, <vscale x 4 x float> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %tuple.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | d
# | ...
# `---data was truncated (10240/14679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a382d4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a382d4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a382d4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11eca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11ecaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11eca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11eca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a382ce3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a382ce3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a382cc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a382977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a382977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11eca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11eca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11eca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a382977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (174 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f71caa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f71caa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f71caaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa09e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa09e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa09e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa09e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f71ca3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f71ca3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f71ca248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f71c6d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f71c6d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa09e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa09e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa09e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f71c6d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (187 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005609d8c88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609d8c85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609d8c8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70e4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70e4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70e4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70e4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609d8c1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609d8c1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609d8c038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609d88b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609d88b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70e4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70e4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70e4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609d88b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (188 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f095b6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f095b69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f095b6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c18505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c18505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c184ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f095b02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f095b02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f095ae78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f095796e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f095796b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c184eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c184ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c184ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f095796a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (191 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2, <vscale x 16 x i8> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %data.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 0
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 1
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 2
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 3
# |   call void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2, <vscale x 8 x i16> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %data.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 0
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 1
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 2
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 3
# |   %11 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10, <vscale x 8 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2, <vscale x 4 x i32> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %data.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 0
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 1
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 2
# |   %10 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 3
# |   %11 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10, <vscale x 4 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2, <vscale x 2 x i64> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %da
# | ...
# `---data was truncated (10240/73307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005563c33c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563c33c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563c33c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e75d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e75d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e75d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e75d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c335bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563c335ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563c33408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563c2fefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563c2fefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e75d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e75d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e75d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c2fefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (192 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005557f3963eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557f3960e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557f396462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557f38f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557f38f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557f38de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557f358de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557f358db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557f358da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (205 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fbc09caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbc09c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbc09cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c3af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c3af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c3af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c3aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbc0960bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbc0960a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbc09458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbc05f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbc05f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c3aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c3aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c3aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbc05f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (206 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e2b50a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2b50a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2b50a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27b9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27b978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27b9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27b971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2b503dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2b503da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2b50228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2b4cd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2b4cd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27b971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27b971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27b971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2b4cd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (207 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556522487eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556522484e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055652248862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4e2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4e2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4e2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4e2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055652241dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055652241da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565224028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565220b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565220b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4e2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4e2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4e2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565220b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (208 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svrshl_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svrshl_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> 
# | ...
# `---data was truncated (10240/93119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005629e7e36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629e7e33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629e7e3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8edf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8edf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8edf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8edf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629e7dccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629e7dcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629e7db18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629e7a60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629e7a60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8edf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8edf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8edf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629e7a60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (211 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005598a3613eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598a3610e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598a361462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa074e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa074ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa074e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa074e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598a35a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598a35a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598a358e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598a323de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598a323db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa074e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa074e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa074e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598a323da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (212 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e39b468eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e39b465e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e39b46962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3195b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3195b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3195b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3195b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e39b3febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e39b3fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e39b3e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e39b092e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e39b092b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3195b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3195b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3195b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e39b092a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (214 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564840e49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564840e46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564840e4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ca3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ca30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ca3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ca3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564840ddfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564840ddfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564840dc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564840a73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564840a73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ca3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ca30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ca30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564840a73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (217 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_s8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_s16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_s32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_s64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_u8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_u16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_u32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_u64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdupq_lane_f16(<vscale x 8 x half> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdupq_lane_f32(<vscale x 4 x float> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdupq_lane_f64(<vscale x 2 x double> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 {
# | entry:
# |   %x0.addr = alloca i8, align 1
# |   %x1.addr = alloca i8, align 1
# |   %x2.addr = alloca i8, align 1
# |   %x3.addr = alloca i8, align 1
# |   %x4.addr = alloca i8, align 1
# |   %x5.addr = alloca i8, align 1
# |   %x6.addr = alloca i8, align 1
# |   %x7.addr = alloca i8, align 1
# |   %x8.addr = alloca i8, align 1
# |   %x9.addr = alloca i8, align 1
# |   %x10.addr = alloca i8, align 1
# |   %x11.addr = alloca i8, align 1
# |   %x12.addr = alloca i8, align 1
# |   %x13.addr = alloca i8, align 1
# |   %x14.addr = alloca i8, align 1
# |   %x15.addr = alloca i8, align 1
# |   store i8 %x0, ptr %x0.addr, align 1
# |   store i8 %x1, ptr %x1.addr, align 1
# |   store i8 %x2, ptr %x2.addr, align 1
# |   store i8 %x3, ptr %x3.addr, align 1
# |   store i8 %x4, ptr %x4.addr, align 1
# |   store i8 %x5, ptr %x5.addr, align 1
# |   store i8 %x6, ptr %x6.addr, align 1
# |   store i8 %x7, ptr %x7.addr, align 1
# |   store i8 %x8, ptr %x8.addr, align 1
# |   store i8 %x9, ptr %x9.addr, align 1
# |   store i8 %x10, ptr %x10.addr, align 1
# |   store i8 %x11, ptr %x11.addr, align 1
# |   store i8 %x12, ptr %x12.addr, align 1
# |   store i8 %x13, ptr %x13.addr, align 1
# |   store i8 %x14, ptr %x14.addr, align 1
# |   store i8 %x15, ptr %x15.addr, align 1
# |   %0 = load i8, ptr %x0.addr, align 1
# |   %1 = load i8, ptr %x1.addr, align 1
# |   %2 = load i8, ptr %x2.addr, align 1
# |   %3 = load i8, ptr %x3.addr, align 1
# |   %4 = load i8, ptr %x4.addr, align 1
# |   %5 = load i8, ptr %x5.addr, align 1
# |   %6 = load i8, ptr %x6.addr, align 1
# |   %7 = load i8, ptr %x7.addr, align 1
# |   %8 = load i8, ptr %x8.addr, align 1
# |   %9 = load i8, ptr %x9.addr, align 1
# |   %10 = load i8, ptr %x10.addr, align 1
# |   %11 = load i8, ptr %x11.addr, align 1
# |   %12 = load i8, ptr %x12.addr, align 1
# |   %13 = load i8, ptr
# | ...
# `---data was truncated (10240/42600) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a32968eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a32968be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a32968f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8da6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8da6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8da6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8da6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a329624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a329624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3296098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3292b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3292b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8da6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8da6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8da6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3292b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (218 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef78eb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef78eb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef78eba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74d5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74d515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74d5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74d50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef78e4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef78e4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef78e348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef78ae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef78ae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74d50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74d50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74d50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef78ae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (221 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef2_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef4_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c71a0ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c71a0fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c71a10062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca6ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca6ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca6ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca6ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c71a095bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c71a095a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c71a07a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c719d29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c719d29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca6ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca6ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca6ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c719d29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (223 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |  
# | ...
# `---data was truncated (10240/16804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055af22b75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af22b72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af22b7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9081533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f908158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9081533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f908151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af22b0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af22b0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af22af08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af2279fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af2279fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f908151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f908151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f908151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af2279fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (224 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/11769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a56db9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a56db9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a56db9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fbc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fbc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fbc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fbc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a56db33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a56db33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a56db188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a56d7c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a56d7c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fbc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fbc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fbc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a56d7c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (228 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563395758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563395755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056339575962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1406449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1406449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1406431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633956eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633956eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633956d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563395382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563395382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1406432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563395382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (229 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i32>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store 
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005597792bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597792bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597792c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf94e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf94ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf94e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf94e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559779255bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559779255a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055977923a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559778ee9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559778ee9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf94e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf94e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf94e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559778ee9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (230 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a9392b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9392b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9392ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08da105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08da15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08da105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08da0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a93924fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a93924fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9392348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a938ee3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a938ee3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08da0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08da0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08da0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a938ee3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (231 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 8 x half
# | ...
# `---data was truncated (10240/88476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005567765c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567765c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567765c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055677655ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055677655ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567765438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567761f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567761f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5de0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567761f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (233 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005575c6036eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575c6033e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575c603762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa70a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa70a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa70a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa70a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575c5fccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575c5fcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575c5fb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575c5c60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575c5c60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa70a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa70a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa70a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575c5c60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (234 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fc426b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc426b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc426b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b92f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b92f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b92f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b92f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc42649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc42649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc4262e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc422dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc422ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b92f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b92f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b92f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc422dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (235 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroi
# | ...
# `---data was truncated (10240/32102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005581d217aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581d2177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581d217b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1436649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1436649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1436631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581d2110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581d2110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581d20f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581d1da4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581d1da4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1436632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14366330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581d1da4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (236 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e9851feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e9851ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e9852062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f665a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f665a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f665a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f665a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e984b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e984b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e9849a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e98149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e98149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f665a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f665a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f665a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e98149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (239 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055592c843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055592c840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592c84462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdffc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdffca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdffc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdffc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055592c7d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055592c7d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055592c7be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055592c46de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055592c46db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdffc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdffc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdffc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055592c46da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (241 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d5e927beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5e9278e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5e927c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a5da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a5daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a5da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a5da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5e9211bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5e9211a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5e91f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5e8ea5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5e8ea5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a5da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a5da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a5da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5e8ea5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (242 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 3
# |   %14 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 3
# |   call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, <vscale x 8 x i16> %10, <vscale x 8 x i16> %11, <vscale x 8 x i16> %12, <vscale x 8 x i16> %13, <vscale x 8 x i16> %15, <vscale x 8 x i16> %16, <vscale x 8 x i16> %17, <vscale x 8 x i16> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, <vscale x 16 x i8> %zm.coerce2, <vscale x 16 x i8> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align
# | ...
# `---data was truncated (10240/127452) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055599d994eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055599d991e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055599d99562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aafd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aafd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aafd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aafd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055599d92abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055599d92aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055599d90f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055599d5bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055599d5beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aafd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aafd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aafd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055599d5bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (244 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/46416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005624e5079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624e5076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624e507a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c24733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c2478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c24733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c2471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624e500fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624e500fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624e4ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624e4ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624e4ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c2471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c2471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c2471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624e4ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (245 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005611c0fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611c0f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611c0fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa62333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa6238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa62333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa6231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611c0f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611c0f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611c0f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611c0bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611c0bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa6231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa6231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa6231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611c0bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (246 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561bcd19feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bcd19ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bcd1a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06ae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06ae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06ae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06ae231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bcd135bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bcd135a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bcd11a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bccdc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bccdc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06ae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06ae2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06ae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bccdc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (247 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555b868e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b868dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b868e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0626f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0626f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0626f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0626eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b86876bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b86876a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b8685b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b8650ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b8650ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0626eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0626eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0626eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b8650aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (248 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld3_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld3_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svld3_f64(<vscale x
# | ...
# `---data was truncated (10240/26187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558e6eabbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e6eab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e6eabc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f44e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f44ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f44e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f44e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e6ea51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e6ea51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e6ea368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e6e6e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e6e6e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f44e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f44e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f44e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e6e6e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (249 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558eee8e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558eee8dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558eee8e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feca5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feca5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feca5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feca5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eee878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558eee878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558eee85d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558eee50ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558eee50cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feca5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feca5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feca5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eee50ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (250 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbo
# | ...
# `---data was truncated (10240/21216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562593d60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562593d5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562593d6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb22b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb22b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb22b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb22b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562593cf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562593cf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562593cdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056259398ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056259398ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb22b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb22b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb22b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056259398aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (252 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmax_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmax_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557794d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557794cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557794d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557794c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557794c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557794c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055779492ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055779492ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055779492aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (253 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005601eedcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601eedc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601eedcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc875e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc875ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc875e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc875e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601eed62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601eed62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601eed478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601ee9f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601ee9f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc875e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc875e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc875e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601ee9f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (254 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate3_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1, <vscale x 8 x half> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   %x2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x half> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vsc
# | ...
# `---data was truncated (10240/15704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055de93479eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de93476e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de9347a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9f5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9f50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9f5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9f5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9340fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de9340fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de933f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de930a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de930a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9f5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9f50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9f50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de930a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (255 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055f3f3f3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3f3f37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3f3f3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2aed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2aed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2aed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2aeced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3f3ed0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3f3ed0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3f3eb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3f3b64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3f3b64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2aeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2aecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2aecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3f3b64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (256 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> }
# | ...
# `---data was truncated (10240/45653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c0bd870eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0bd86de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0bd87162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84f9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84f998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84f9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84f991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0bd806bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0bd806a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0bd7eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0bd49ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0bd49ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84f991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84f991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84f991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0bd49aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (257 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dc90429eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc90426e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc9042a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38fe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38fe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38fe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38fe11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc903bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc903bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc903a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc90053e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc90053b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38fe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38fe11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38fe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc90053a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (258 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalb_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005575ff463eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575ff460e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575ff46462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9810333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f981038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9810333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f981031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575ff3f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575ff3f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575ff3de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575ff08de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575ff08db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f981031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f981031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f981031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575ff08da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (260 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 
# | ...
# `---data was truncated (10240/22063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee4bc8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee4bc89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee4bc8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cce449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cce4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cce449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cce431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee4bc22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee4bc22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee4bc078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee4b8b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee4b8b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cce432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cce4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cce4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee4b8b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (261 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b8c3fa3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8c3fa0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8c3fa462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8c3f39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8c3f39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8c3f1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8c3bcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8c3bcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8c3bcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (262 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/22149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eabe846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eabe843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eabe84762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51f6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51f695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51f6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51f68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eabe7dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eabe7dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eabe7c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eabe470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eabe470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51f68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51f68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51f68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eabe470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (263 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.ad
# | ...
# `---data was truncated (10240/17434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dca6b5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dca6b57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dca6b5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4ed105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4ed15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4ed105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4ed0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dca6af0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dca6af0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dca6ad58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca6784e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca6784b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4ed0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4ed0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4ed0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca6784a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (264 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e49bc27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e49bc24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e49bc2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76e2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76e28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76e2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76e2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e49bbbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e49bbbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e49bba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e49b851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e49b851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76e2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76e28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76e28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e49b851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (265 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/21295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c2f5a93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2f5a90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2f5a9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb23849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb23849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb23831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2f5a29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2f5a29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2f5a0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2f56bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2f56bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb23832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb238330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2f56bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (266 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b749d43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b749d40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b749d4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24c5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24c58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24c5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24c5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b749cd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b749cd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b749cbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b74996de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b74996db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24c5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24c58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24c58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b74996da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (267 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557587940eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055758793de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055758794162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4248533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f424858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4248533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f424851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575878d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575878d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575878bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055758756ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055758756ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f424851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f424851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f424851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055758756aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (268 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b13048deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b13048ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b13048e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52e4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52e498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52e4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52e491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b130423bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b130423a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1304088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1300b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1300b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52e491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52e491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52e491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1300b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (269 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 {
# | entry:
# |   %cnt.addr = alloca target("aarch64.svcount"), align 2
# |   store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2
# |   %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1> %0)
# |   ret target("aarch64.svcount") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005610e32aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610e32abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610e32af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f103a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f103a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f103a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f103a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e3244bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610e3244a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610e32298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610e2ed8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610e2ed8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f103a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f103a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f103a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e2ed8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (270 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c1ff2b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1ff2b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1ff2b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96e4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96e42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96e4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96e4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1ff24bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1ff24ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1ff2308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1feedfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1feedfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96e4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96e42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96e42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1feedfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (272 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/53158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005630d0e3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630d0e38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630d0e3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d39c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d39ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d39c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d39c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630d0dd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630d0dd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630d0db68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630d0a65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630d0a65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d39c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d39c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d39c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630d0a65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (273 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %5, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %5, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %5, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %5, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# | ...
# `---data was truncated (10240/34217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055828aeeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055828aee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055828aeeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c97d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c97d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c97d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c97d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055828ae80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055828ae80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055828ae658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055828ab14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055828ab14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c97d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c97d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c97d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055828ab14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (274 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c27f05eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c27f05be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c27f05f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36be81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36be8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36be81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36be803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c27eff4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c27eff4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c27efd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c27ec88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c27ec88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36be804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36be8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36be8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c27ec88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (275 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %9 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 0
# |   %11 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 1
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 2
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 3
# |   %14 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 0
# |   %16 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 1
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 2
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 3
# |   %19 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i8> %13, <vscale x 16 x i8> %15, <vscale x 16 x i8> %16, <vscale x 16 x i8> %17, <vscale x 16 x i8> %18)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %19
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn3.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn4.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %8 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %9 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %8, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   %zn3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %0, align 16
# |   %zn4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %1, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn3, ptr %zn3.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn4, ptr %zn4.addr, align 16
# |   %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 0
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 1
# |   %14 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 2
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 3
# |   %16 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 0
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 1
# |   %19 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 2
# |   %20 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 3
# |   %21 = call { <vscale x 16 x i8>, <vscale x 16 
# | ...
# `---data was truncated (10240/73319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x00005636c5e02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636c5dffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636c5e0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78e671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636c5d98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636c5d98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636c5d7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636c5a2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636c5a2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78e671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636c5a2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (276 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x ha
# | ...
# `---data was truncated (10240/18235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556fdf22deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fdf22ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fdf22e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3800133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f380018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3800133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f380011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fdf1c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fdf1c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fdf1a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fdee57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fdee57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f380011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f380011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f380011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fdee57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (279 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005573a192ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573a1929e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573a192d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13d8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13d8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13d8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13d8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a18c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573a18c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573a18a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573a1556e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573a1556b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13d8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13d8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13d8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a1556a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (280 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c07f121eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c07f11ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c07f12262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e6b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e6b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e6b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e6aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c07f0b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c07f0b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c07f09c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c07ed4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c07ed4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42e6aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e6aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e6aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c07ed4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (281 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eace510eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eace50de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eace51162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dde61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dde6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dde61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dde603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eace4a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eace4a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eace48b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eace13ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eace13ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dde604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dde6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dde6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eace13aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (282 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %4, 0
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %4, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale
# | ...
# `---data was truncated (10240/25462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a3aa672eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3aa66fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3aa67362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87f5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87f5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87f5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87f5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3aa608bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3aa608a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3aa5ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3aa29ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3aa29cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87f5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87f5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87f5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3aa29ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (283 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055c7d7158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7d7155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7d715962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28f7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7d70eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7d70eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7d70d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7d6d82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7d6d82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7d6d82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (284 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f868459eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f868456e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f86845a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd606505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd60655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd606505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6064ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8683efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8683efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8683d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f868083e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f868083b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6064eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6064ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6064ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f868083a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (285 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ab4ba51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab4ba4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab4ba5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7be1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7be178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7be1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7be171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab4b9e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab4b9e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab4b9cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab4b67be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab4b67bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7be171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7be171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7be171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab4b67ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (286 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svld2_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm
# | ...
# `---data was truncated (10240/24404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558c08fc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c08fc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c08fc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d52c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d52ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d52c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d52c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c08f5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c08f5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c08f428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c08bf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c08bf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d52c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d52c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d52c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c08bf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (287 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_u8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_u16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_u32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_u64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svinsr_n_f16(<vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %0, half %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svinsr_n_f32(<vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %0, float %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svinsr_n_f64(<vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load double, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %0, double %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svinsr_n_bf16(<vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d89b051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d89b04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d89b05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd384849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3848a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd384849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd384831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d89afe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d89afe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d89afcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d89ac7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d89ac7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd384832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3848330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3848330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d89ac7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (288 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005560e67f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560e67f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560e67f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc87a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc87a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc87a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc87a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e678abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560e678aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560e676f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560e641ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560e641eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc87a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc87a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc87a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e641ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (289 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr
# | ...
# `---data was truncated (10240/26796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556169e9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556169e9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556169ea062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9669d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9669d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9669d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9669d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556169e35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556169e35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556169e1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556169ac9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556169ac9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9669d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9669d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9669d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556169ac9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (290 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x2(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x2(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svscale_single_f64_x2(<vscale x 2 x double> %op1.coerce0, <vscale x 2 x double> %op1.coerce1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %op1.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x4(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x half> %op1.coerce2, <vscale x 8 x half> %op1.coerce3, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %op1.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x4(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x float> %op1.coerce2, <vscale x 4 x float> %op1.coerce3, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %op1.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr 
# | ...
# `---data was truncated (10240/37349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b4bd75beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4bd758e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4bd75c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f940ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f940ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f940ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f940ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4bd6f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4bd6f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4bd6d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4bd385e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4bd385b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f940ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f940ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f940ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4bd385a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (291 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563206c04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563206c01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563206c0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e34049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e34049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e34031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563206b9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563206b9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563206b7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056320682ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056320682eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e34032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e340330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056320682ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (292 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005575cf974eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575cf971e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575cf97562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6682333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f668238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6682333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f668231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575cf90abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575cf90aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575cf8ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575cf59ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575cf59eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f668231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f668231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f668231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575cf59ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (293 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005610ec4f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610ec4ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610ec4f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73c0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73c098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73c0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73c091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610ec486bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610ec486a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610ec46b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610ec11ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610ec11ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73c091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73c091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73c091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610ec11aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (294 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 8, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 9, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056489782beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564897828e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056489782c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81cfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81cfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81cfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81cfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648977c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648977c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648977a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564897455e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564897455b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81cfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81cfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81cfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564897455a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (297 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   call void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 2
# |   %9 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 0
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 1
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 2
# |   %9 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, <vscale x 2 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = al
# | ...
# `---data was truncated (10240/58378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c7d72bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7d72b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7d72bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cf641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cf64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cf641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cf6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7d7252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7d7252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7d72378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7d6ee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7d6ee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cf6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cf64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cf64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7d6ee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (299 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i16>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/18010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005572d44efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572d44ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572d44f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e75049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e75049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e75031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572d4485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572d4485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572d446a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572d4119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572d4119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e75032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e750330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572d4119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (300 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ac6069eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac6069be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac6069f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2afd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2afd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2afd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2afd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac60634bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac60634a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac606198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac602c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac602c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2afd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2afd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2afd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac602c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (303 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e702e43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e702e40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e702e4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf8bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf8bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf8bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e702dd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e702dd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e702dbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e702a6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e702a6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf8bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf8bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf8bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e702a6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (304 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %.splat, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d32abdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d32abdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d32abe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22ac133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22ac18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22ac133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22ac11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d32ab75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d32ab75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d32ab5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d32a809e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d32a809b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22ac11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22ac11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22ac11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d32a809a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (306 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056326ee33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056326ee30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056326ee3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb31dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb31dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb31dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb31dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056326edc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056326edc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056326edae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056326ea5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056326ea5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb31dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb31dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb31dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056326ea5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (307 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a433ce6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a433ce3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a433ce762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfc4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfc4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfc4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfc4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a433c7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a433c7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a433c618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a433910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a433910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfc4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfc4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfc4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a433910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (308 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561cd0af9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cd0af6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cd0afa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f4f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f4f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f4f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f4f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cd0a8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cd0a8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cd0a748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cd0723e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cd0723b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f4f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f4f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f4f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cd0723a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (309 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 1
# | ...
# `---data was truncated (10240/48782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055effb38beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055effb388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055effb38c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ffed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ffed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ffed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ffed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055effb321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055effb321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055effb3068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055effafb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055effafb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ffed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ffed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ffed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055effafb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (310 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b7270f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7270f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7270f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef52449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef52449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef52431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b72708cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b72708ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7270718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b726d20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b726d20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef52432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef524330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b726d20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (311 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000557af6e5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557af6e58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557af6e5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd68aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd68aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd68aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd68aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557af6df1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557af6df1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557af6dd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557af6a85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557af6a85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd68aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd68aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd68aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557af6a85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (315 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 13, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 29, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c120fa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c120fa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c120fa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0064249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00642a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0064249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0064231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c120f3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c120f3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c120f208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c120bcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c120bcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0064232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00642330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00642330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c120bcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (316 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055991ceb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055991ceb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055991ceb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa60e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa60e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa60e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa60e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055991ce4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055991ce4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055991ce338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055991cae2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055991cae2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa60e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa60e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa60e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055991cae2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (317 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556030dceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556030dcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556030dcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a1e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556030d64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556030d64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556030d498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560309f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560309f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560309f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (318 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clasta.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056494056deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056494056ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056494056e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe111933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe11198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe111933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe11191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564940503bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564940503a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649404e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564940197e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564940197b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe11191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe11191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe11191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564940197a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (319 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   
# | ...
# `---data was truncated (10240/11488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bf9bd5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf9bd5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf9bd5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb8be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb8bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb8be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb8be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf9bcf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf9bcf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf9bcd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf9b988e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf9b988b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb8be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb8be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb8be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf9b988a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (320 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 270)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.ad
# | ...
# `---data was truncated (10240/12234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556482525eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556482522e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055648252662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fbfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fbfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fbfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fbfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564824bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564824bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564824a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055648214fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055648214fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fbfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fbfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fbfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055648214fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (321 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_3_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557ea8c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea8c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea8c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea8be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea8be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea8bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea8874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea8874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea8874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (322 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svmov_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005640d0e0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640d0e09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640d0e0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0767649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0767649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0767631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640d0da2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640d0da2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640d0d878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640d0a36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640d0a36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0767632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640d0a36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (323 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clastb.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005562c4321eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562c431ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562c432262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7855249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78552a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7855249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7855231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562c42b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562c42b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562c429c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562c3f4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562c3f4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7855232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78552330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78552330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562c3f4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (324 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 29, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 30, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bc294a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc294a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc294a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc57d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc57d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc57d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc57d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc2943ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc2943ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc294238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc290d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc290d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc57d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc57d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc57d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc290d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (330 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/75656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055851346eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055851346be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055851346f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc73fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc73fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc73fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc73fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558513404bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558513404a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585133e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558513098e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558513098b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc73fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc73fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc73fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558513098a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (331 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c089d21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c089d1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c089d2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c3c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c3c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c3c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c3c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c089cb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c089cb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c089c9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c08994be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c08994bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c3c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c3c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c3c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c08994ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (332 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ec2321aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec23217e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec2321b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc71b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc71b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc71b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc71b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec231b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec231b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec231958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec22e44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec22e44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc71b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc71b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc71b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec22e44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (333 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005610bf1edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610bf1eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610bf1ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4e9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4e90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4e9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4e9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610bf183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610bf183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610bf1688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610bee17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610bee17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4e9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4e90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4e90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610bee17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (334 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   store <vscale x 4 x i32> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %1, 1
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, <vscale x 4 x i32> %2, 2
# |   %7 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, <vscale x 4 x i32> %3, 3
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate4_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2, <vscale x 2 x i64> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   %x4.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   store <vscale x 2 x i64> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %1, 1
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, <vscale x 2 x i64> %2, 2
# |   %7 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, <vscale x 2 x i64> %3, 3
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vs
# | ...
# `---data was truncated (10240/21212) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b5e1ab5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5e1ab2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5e1ab662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f8db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f8db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f8db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f8db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5e1a4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5e1a4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5e1a308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5e16dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5e16dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f8db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f8db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f8db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5e16dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (336 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a87d3aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a87d3a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a87d3ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40bbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40bbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40bbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40bbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a87d340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a87d340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a87d3258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a87cfd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a87cfd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40bbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40bbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40bbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a87cfd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (337 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cebfe26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cebfe23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cebfe2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd319133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd31918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd319133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd31911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cebfdbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cebfdbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cebfda18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cebfa50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cebfa50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd31911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd31911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd31911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cebfa50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (338 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i64>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d97ec44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d97ec41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d97ec4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9944133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f994418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9944133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f994411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d97ebdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d97ebdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d97ebbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d97e86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d97e86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f994411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f994411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f994411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d97e86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (339 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsplice_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/14328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d759bfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d759bf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d759bfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f978e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f978e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f978e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f978e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d759b92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d759b92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d759b778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d759826e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d759826b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f978e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f978e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f978e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d759826a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (340 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560fc0089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fc0086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fc008a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feec1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feec1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feec1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feec1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fc001fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fc001fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fc00048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fbfcb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fbfcb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feec1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feec1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feec1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fbfcb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (341 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055defc879eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055defc876e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055defc87a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd43d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd43d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd43d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd43d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055defc80fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055defc80fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055defc7f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055defc4a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055defc4a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd43d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd43d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd43d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055defc4a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (342 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_f16_f16(
# | ...
# `---data was truncated (10240/27272) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056369801feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056369801ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056369802062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4fcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563697fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563697fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563697f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563697c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563697c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563697c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (343 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/11908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dec1927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dec1924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dec192862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dec18bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dec18bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dec18a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dec1551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dec1551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97a7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dec1551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (344 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bd59004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd59001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd5900562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd86c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd86c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd86c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd86c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd58f9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd58f9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd58f7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd58c2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd58c2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd86c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd86c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd86c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd58c2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (345 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 8, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 9, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560288c20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560288c1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560288c2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2697849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2697849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2697831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560288bb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560288bb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560288b9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056028884ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056028884ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2697832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056028884aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (347 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055753acd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055753accee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055753acd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f350ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f350caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f350ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f350ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055753ac67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055753ac67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055753ac4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055753a8fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055753a8fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f350ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f350ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f350ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055753a8fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (348 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld4_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld4_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.fr
# | ...
# `---data was truncated (10240/27970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056162c2e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056162c2dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056162c2e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f8ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f8ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f8ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f8ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056162c277bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056162c277a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056162c25c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056162bf0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056162bf0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f8ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f8ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f8ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056162bf0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (349 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fd44c75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd44c72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd44c7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e36d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e36d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e36d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e36d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd44c0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd44c0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd44bf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd4489fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd4489fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e36d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e36d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e36d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd4489fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (350 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005574c56aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574c56a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574c56ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68cf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574c5642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574c5642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574c56278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574c52d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574c52d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574c52d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (351 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_ra
# | ...
# `---data was truncated (10240/35066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055e6c9427eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6c9424e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6c942862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89b1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89b12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89b1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89b1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6c93bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6c93bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6c93a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6c9051e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6c9051b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89b1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89b12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89b12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6c9051a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (352 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %
# | ...
# `---data was truncated (10240/74176) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d93be8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d93be8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d93be8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f302af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f302af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f302af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d93be23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d93be23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d93be088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d93bab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d93bab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f302af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f302af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f302af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d93bab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (353 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 3, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 4, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee0197deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee0197ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee0197e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe8fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe8fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe8fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe8fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee01913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee01913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee018f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee015a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee015a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe8fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe8fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe8fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee015a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (354 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056462fb29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056462fb26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056462fb2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f373da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f373daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f373da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f373da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056462fabfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056462fabfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056462faa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056462f753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056462f753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f373da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f373da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f373da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056462f753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (355 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/33353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005584a71bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584a71b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584a71bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eed231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584a7151bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584a7151a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584a71368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584a6de5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584a6de5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5eed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eed2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584a6de5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (356 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrev_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrev_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrev_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b8(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b16(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b32(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b64(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svrev_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005565d1f71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565d1f6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565d1f7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabafa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabafa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabafa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabafa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565d1f07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565d1f07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565d1eec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565d1b9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565d1b9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabafa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabafa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabafa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565d1b9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (357 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d0a0328eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0a0325e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0a032962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f985d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f985d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f985d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f985d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0a02bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0a02bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0a02a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d09ff52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d09ff52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f985d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f985d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f985d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d09ff52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (358 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlastb_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlastb_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlastb_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e90b921eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e90b91ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e90b92262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3222e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3222ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3222e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3222e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e90b8b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e90b8b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e90b89c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e90b54be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e90b54bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3222e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3222e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3222e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e90b54ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (360 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16(<vscale x 8 x bfloat> %zn_zm.coerce0, <vscale x 8 x bfloat> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(<vscale x 8 x half> %zn_zm.coerce0, <vscale x 8 x half> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32(<vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32(<vscale x 16 x i8> %zd, <vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zd.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store <vscale x 16 x i8> %zd, ptr %zd.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zd.addr, align 16
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   %7 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret <vscale x 16 x i8> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555b42112eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b4210fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b4211362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7853a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7853aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7853a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7853a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b420a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b420a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b4208d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b41d3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b41d3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7853a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7853a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7853a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b41d3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (361 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef9daaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef9daabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef9daaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa33133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa3318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa33133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa3311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef9da44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef9da44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef9da298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef9d6d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef9d6d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa3311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa3311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa3311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef9d6d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (362 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c4d43b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4d43b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4d43b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45e8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45e818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45e8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45e811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4d434bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4d434ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4d43308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4d3fdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4d3fdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45e811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45e811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45e811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4d3fdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (363 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpa_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f67b474eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f67b471e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f67b47562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6a3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6a30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6a3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6a3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f67b40abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f67b40aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f67b3ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f67b09ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f67b09eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6a3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6a30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6a30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f67b09ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (364 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a36550aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a365507e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a36550b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55cc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55cc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55cc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55cc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3654a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3654a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3654858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a365134e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a365134b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55cc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55cc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55cc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a365134a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (365 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a49d163eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a49d160e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a49d16462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdc0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdc0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdc0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdc0a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a49d0f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a49d0f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a49d0de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a49cd8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a49cd8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdc0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdc0a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdc0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a49cd8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (366 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 {
# | entry:
# |   ret target("aarch64.svcount") zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560d62731eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d6272ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d6273262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3252d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3252d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3252d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3252d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d626c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d626c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d626ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d6235be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d6235bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3252d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3252d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3252d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d6235ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (367 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate2_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %1, 1
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcreate2_f32(<vscale x 4 x float> %x0, <vscale x 4 x float> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x float>, align 16
# |   %x1.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x float> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %1, 1
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svcreate2_f64(<vscale x 2 x double> %x0, <vscale x 2 x double> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x double>, align 16
# |   %x1.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x double> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %1, 1
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_mf8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svcreate2_bf16(<vscale x 8 x bfloat> %x0, <vscale x 8 x bfloat> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %x1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x bfloat> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/10734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005572648b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572648b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572648ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb79fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb79faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb79fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb79fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055726484fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055726484fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572648348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572644e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572644e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb79fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb79fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb79fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572644e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (368 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlasta_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlasta_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlasta_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561f4333eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f4333be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f4333f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc75e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc75e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc75e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc75e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f432d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f432d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f432b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f42f68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f42f68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc75e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc75e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc75e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f42f68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (369 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 3
# |   %14 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 3
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, <vscale x 8 x half> %10, <vscale x 8 x half> %11, <vscale x 8 x half> %12, <vscale x 8 x half> %13, <vscale x 8 x half> %15, <vscale x 8 x half> %16, <vscale x 8 x half> %17, <vscale x 8 x half> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/34400) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005624040bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624040b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624040bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70e0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70e0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70e0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70e0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562404051bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562404051a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624040368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562403ce5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562403ce5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70e0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70e0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70e0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562403ce5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (370 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b059048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b059045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b05904962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b058fdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b058fdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b058fc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b058c72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b058c72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b058c72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (371 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1>, ptr, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = getelementptr <vscale x 16 x i8>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_s32offset(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/16554) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556825706eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556825703e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055682570762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c42733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c4278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c42733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c4271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055682569cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055682569ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568256818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556825330e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556825330b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c4271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c4271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c4271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556825330a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (378 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560add457eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560add454e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560add45862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe14133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe1418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe14133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe1411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560add3edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560add3eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560add3d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560add081e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560add081b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe1411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe1411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe1411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560add081a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (379 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamax_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svamax_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 0
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 1
# |   %10 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %8, <vscale x 4 x float> %9)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svamax_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm.coerce0, <vscale x 2 x double> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %zm.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1
# |   %7 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 0
# |   %9 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 1
# |   %10 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %8, <vscale x 2 x double> %9)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamin_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8
# | ...
# `---data was truncated (10240/45703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b3ecefeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3ecefbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3eceff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1fca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1fcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1fca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1fca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3ece94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3ece94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3ece798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3ecb28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3ecb28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1fca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1fca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1fca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3ecb28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (380 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 1
# |   %6 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | ...
# `---data was truncated (10240/24605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055947e7cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055947e7c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055947e7cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ea5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ea518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ea5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ea511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055947e762bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055947e762a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055947e7478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055947e3f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055947e3f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ea511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ea511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ea511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055947e3f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (381 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560c3a32feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c3a32ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c3a33062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c3a2c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c3a2c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c3a2aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c39f59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c39f59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c39f59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (382 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 2, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 3, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005647cc504eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647cc501e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647cc50562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe79f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe79f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe79f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe79f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647cc49abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647cc49aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647cc47f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647cc12ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647cc12eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe79f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe79f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe79f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647cc12ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (383 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000557f2502eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f2502be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f2502f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1968533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f196858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1968533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f196851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f24fc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f24fc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f24fa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f24c58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f24c58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f196851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f196851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f196851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f24c58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (384 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005652afb70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652afb6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652afb7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2761249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27612a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2761249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2761231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652afb06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652afb06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652afaeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652af79ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652af79ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2761232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27612330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27612330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652af79aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (386 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnt1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %b
# | ...
# `---data was truncated (10240/22231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005623e18c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623e18c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623e18c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0684d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0684d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0684d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0684d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623e1859bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623e1859a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623e183e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623e14ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623e14edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0684d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0684d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0684d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623e14eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (387 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056516d01beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056516d018e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056516d01c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6942249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6942249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6942231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056516cfb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056516cfb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056516cf968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056516cc45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056516cc45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6942232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056516cc45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (388 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b73e530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b73e52de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b73e53162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae42f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae42f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae42f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae42f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b73e4c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b73e4c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b73e4ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b73e15ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b73e15ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae42f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae42f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae42f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b73e15aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (390 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpklo_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556410e92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556410e8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556410e9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbcf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbcf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbcf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbcf4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556410e28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556410e28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556410e0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556410abce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556410abcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbcf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbcf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbcf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556410abca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (392 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000564d975d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d975d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d975d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bf2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bf2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bf2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bf2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d9756dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d9756da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d975528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d97201e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d97201b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bf2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bf2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bf2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d97201a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (393 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svqdmulh_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svqdmulh_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x4(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zdn.coerce2, <vscale x 16 x i8> %zdn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zdn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x4(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zdn.coerce2, <vscale x 8
# | ...
# `---data was truncated (10240/47111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005577fc2b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577fc2b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577fc2b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdeee01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdeee0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdeee01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdeee003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577fc24cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577fc24ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577fc2318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577fbee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577fbee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdeee004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdeee0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdeee0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577fbee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (394 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x2(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svclamp_single_s16_x2(<vscale x 8 x i16> %op1.coerce0, <vscale x 8 x i16> %op1.coerce1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %op1.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svclamp_single_s32_x2(<vscale x 4 x i32> %op1.coerce0, <vscale x 4 x i32> %op1.coerce1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %op1.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svclamp_single_s64_x2(<vscale x 2 x i64> %op1.coerce0, <vscale x 2 x i64> %op1.coerce1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %op1.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x4(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op1.coerce2, <vscale x 16 x i8> %op1.coerce3, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %op1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/62547) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558766af3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558766af0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558766af462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37aa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37aa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37aa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37aa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558766a89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558766a89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558766a6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055876671de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055876671db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37aa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37aa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37aa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055876671da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (399 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 8)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 1)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 16)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 1)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z_1(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 32)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 1)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z_1(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 64)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i32 1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, 
# | ...
# `---data was truncated (10240/14353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055df5cf81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df5cf7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df5cf8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8248533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8248533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df5cf17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df5cf17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df5cefc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df5cbabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df5cbabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f824851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df5cbaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (400 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <
# | ...
# `---data was truncated (10240/50724) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562c51741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c5173ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c5174262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b1d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b1d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b1d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b1d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c516d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c516d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c516bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c5136be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c5136bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b1d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b1d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b1d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c5136ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (403 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1, <vscale x 16 x i8> %val.coerce2, <vscale x 16 x i8> %val.coerce3) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %val.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %val.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %4 = load i32, ptr %base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale
# | ...
# `---data was truncated (10240/150970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559fcf850eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fcf84de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fcf85162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6f4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6f4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6f4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6f4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fcf7e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fcf7e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fcf7cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fcf47ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fcf47ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6f4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6f4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6f4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fcf47aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (405 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056162d394eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056162d391e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056162d39562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba85849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba85849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba85831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056162d32abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056162d32aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056162d30f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056162cfbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056162cfbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba85832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba858330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056162cfbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (406 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c1671e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1671e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1671e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f724e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f724e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f724e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f724e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c16717ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c16717ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1671638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c166e12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c166e12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f724e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f724e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f724e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c166e12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (407 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555a1fb2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a1fb29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a1fb2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0910249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0910249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0910231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a1fac2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a1fac2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a1faa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a1f756e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a1f756b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0910232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09102330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a1f756a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (408 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svminnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svminnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svminnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556eba981eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556eba97ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556eba98262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aff11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eba917bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556eba917a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556eba8fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eba5abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eba5abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3aff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aff11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eba5aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (411 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %
# | ...
# `---data was truncated (10240/93831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055dcfed24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcfed21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcfed2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15be71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcfecbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcfecbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcfec9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcfe94ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcfe94eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15be71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcfe94ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (412 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_s8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_s16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_s32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_s64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_u8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_u16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_u32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_u64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbl_f16(<vscale x 8 x half> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbl_f32(<vscale x 4 x float> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtbl_f64(<vscale x 2 x double> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtbl_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptra
# | ...
# `---data was truncated (10240/10361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cb14f83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb14f80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb14f8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f9cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f9cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f9cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f9cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb14f19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb14f19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb14efe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb14bade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb14badb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f9cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f9cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f9cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb14bada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (413 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 0)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 90)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_2(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 180)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_3(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 270)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 0)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 90)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale
# | ...
# `---data was truncated (10240/21122) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d8fb2cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8fb2cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8fb2d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45f8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45f818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45f8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45f811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8fb265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8fb265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8fb24a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8faef9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8faef9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45f811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45f811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45f811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8faef9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (415 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557b06612eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b0660fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0661362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f427cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f427cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f427cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f427cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b065a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b065a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b0658d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b0623ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b0623cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f427cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f427cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f427cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0623ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (417 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 
# | ...
# `---data was truncated (10240/13379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d85eb64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d85eb61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d85eb6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6696f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6696f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6696f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6696f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d85eafabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d85eafaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d85eadf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d85e78ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d85e78eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6696f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6696f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6696f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d85e78ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (418 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1, <vscale x 8 x bfloat> %zm.coerce2, <vscale x 8 x bfloat> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, <vscale x 8 x bfloat> %zm.coerce2, 2
# |   %7 = insertvalue { <v
# | ...
# `---data was truncated (10240/13687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561b55eeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b55eebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b55eef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5820b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5820b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5820b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5820b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b55e84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b55e84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b55e698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b55b18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b55b18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5820b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5820b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5820b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b55b18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (420 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsel_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/15264) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b48430aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b484307e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b48430b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8aff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8aff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8aff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8aff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4842a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4842a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4842858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b483f34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b483f34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8aff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8aff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8aff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b483f34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (423 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055c861bcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c861bcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c861bd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fade2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fade2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fade2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fade2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c861b65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c861b65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c861b4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8617f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8617f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fade2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fade2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fade2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8617f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (427 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0
# | ...
# `---data was truncated (10240/39820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055f76ea8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f76ea8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f76ea9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52c2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52c2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52c2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52c2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f76ea25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f76ea25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f76ea0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f76e6b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f76e6b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52c2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52c2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52c2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f76e6b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (429 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
# | ...
# `---data was truncated (10240/37760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005648b04cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648b04cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648b04d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe7a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe7a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe7a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe7a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648b0465bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648b0465a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648b044a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648b00f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648b00f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe7a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe7a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe7a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648b00f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (431 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8_1(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 0)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16_1(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 0)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32_1(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64_1(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svext_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 127)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svext_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr 
# | ...
# `---data was truncated (10240/12880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ae87641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae8763ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae8764262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb126933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb12698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb126933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb12691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae875d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae875d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae875bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae8726be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae8726bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb12691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb12691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb12691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae8726ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (433 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dedaed4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dedaed1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dedaed562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc889e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc889ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc889e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc889e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dedae6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dedae6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dedae4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dedaafee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dedaafeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc889e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc889e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc889e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dedaafea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (435 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055843b1a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055843b1a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055843b1a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c5a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c5a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c5a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c5a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055843b139bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055843b139a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055843b11e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055843adcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055843adcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c5a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c5a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c5a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055843adcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (438 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f74f9caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f74f9c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f74f9cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10a1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10a1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10a1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10a1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f74f960bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f74f960a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f74f9458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f74f5f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f74f5f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10a1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10a1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10a1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f74f5f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (439 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056170398eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056170398be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056170398f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe67e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe67e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe67e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe67e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561703924bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561703924a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617039098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617035b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617035b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe67e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe67e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe67e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617035b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (440 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s16_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u16_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <v
# | ...
# `---data was truncated (10240/25017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d0025afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0025ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0025b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b31a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b31aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b31a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b31a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d002545bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d002545a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d00252a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0021d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0021d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b31a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b31a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b31a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0021d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (443 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a1d9551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1d954ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1d955262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f154d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f154d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f154d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f154d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1d94e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1d94e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1d94cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1d917be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1d917bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f154d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f154d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f154d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1d917ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (448 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f3fc69beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3fc698e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3fc69c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50aa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3fc631bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3fc631a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3fc6168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3fc2c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3fc2c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3fc2c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (449 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005603fa206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603fa203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603fa20762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f724c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f724c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f724c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f724c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603fa19cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603fa19ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603fa1818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603f9e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603f9e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f724c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f724c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f724c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603f9e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (451 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfirst_b(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ba363b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba363b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba363b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f486f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f486f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba3634bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba3634ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba363308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba35fdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba35fdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f486f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba35fdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (455 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005622892f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622892efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622892f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb10049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb100a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb10049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb10031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562289288bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562289288a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056228926d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562288f1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562288f1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb10032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb100330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb100330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562288f1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (456 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555d7e527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d7e524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d7e52862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f63449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f63449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f63431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d7e4bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d7e4bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d7e4a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d7e151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d7e151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f63432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f634330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d7e151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (458 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_s16_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, i32 16)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/33461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055fa2d443eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa2d440e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa2d44462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdfac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdfaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdfac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdfac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa2d3d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa2d3d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa2d3be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa2d06de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa2d06db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdfac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdfac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdfac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa2d06da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (462 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_1(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 =
# | ...
# `---data was truncated (10240/15126) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564006320eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056400631de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056400632162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a72449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a72449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a72431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640062b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640062b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056400629b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564005f4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564005f4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a72432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564005f4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (464 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za16_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za32_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005579e412feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579e412ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579e413062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd53a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd53a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd53a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd53a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e40c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579e40c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579e40aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579e3d59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579e3d59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd53a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd53a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd53a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e3d59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (466 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvt_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvt_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_u32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_s32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, p
# | ...
# `---data was truncated (10240/39207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555d67b23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d67b20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d67b2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62d2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62d2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62d2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62d2a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d67ab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d67ab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d67a9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d6774de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d6774db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62d2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62d2a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62d2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d6774da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (467 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1q_gather_u64base_offset_f64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1q_gather_u64base_offset_f32(<vscale x 16 x i1> %pg, <vscale x 2 x
# | ...
# `---data was truncated (10240/58824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f045496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f045493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f04549762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb28fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb28fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb28fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb28faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f04542cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f04542ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0454118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0450c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0450c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb28faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb28faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb28faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0450c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (468 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalt_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b7b3c9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7b3c9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7b3ca062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4198b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4198b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4198b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4198b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7b3c35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7b3c35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7b3c1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7b38c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7b38c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4198b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4198b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4198b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7b38c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (470 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_x(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_m(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056026cb81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056026cb7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056026cb8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc056d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc056d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc056d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc056d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056026cb17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056026cb17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056026cafc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056026c7abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056026c7abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc056d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc056d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc056d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056026c7aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (472 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svzip_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svzip_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svzip_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564a505f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a505f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a505f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11a621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11a62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11a621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11a6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a50589bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a50589a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a5056e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a5021de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a5021db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11a6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11a62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11a62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a5021da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (474 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvtn_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvtn_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_loc
# | ...
# `---data was truncated (10240/17734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005645377fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645377fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645377fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc78449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc78449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc78431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564537793bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564537793a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645377788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564537427e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564537427b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc78432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc784330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564537427a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (475 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_s32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_u32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svadd_vector_single2_s64(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x
# | ...
# `---data was truncated (10240/34761) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005620a4da8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620a4da5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620a4da962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb33c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb33ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb33c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb33c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620a4d3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620a4d3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620a4d238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620a49d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620a49d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb33c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb33c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb33c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620a49d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (478 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1rq_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1rq_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1rq_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1rq_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005566c63c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566c63c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566c63c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc005249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc005249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc005231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566c635dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566c635da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566c63428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566c5ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566c5ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc005232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566c5ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (479 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2  -target-feature +sme  -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u8_1(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s8_2(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u16_3(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s16_1(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u32_2(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s32_3(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u64_0(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s64_1(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f16_2(<vscale x 8 x half> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_bf16_3(<vscale x 8 x bfloat> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f32_0(<vscale x 4 x float> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f64_1(<vscale x 2 x double> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %
# | ...
# `---data was truncated (10240/13584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c6b46c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6b46c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6b46c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6b4659bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6b4659a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6b463e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6b42ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6b42edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6b42eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (482 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svsel_s16_x2(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   %11 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale 
# | ...
# `---data was truncated (10240/33971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005603de32deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603de32ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603de32e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6ce649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6ce6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6ce649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6ce631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603de2c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603de2c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603de2a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603ddf57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603ddf57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6ce632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6ce6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6ce6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603ddf57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (483 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561d04471eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d0446ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d0447262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcae2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcae2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcae2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcae2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d04407bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d04407a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d043ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d0409be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d0409bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcae2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcae2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcae2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d0409ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (485 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e9e346deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9e346ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9e346e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a4c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a4c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a4c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a4c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9e3403bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9e3403a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9e33e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9e3097e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9e3097b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a4c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a4c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a4c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9e3097a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (487 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c714824eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c714821e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c71482562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76fd41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76fd4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76fd41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76fd403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7147babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7147baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c71479f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c71444ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c71444eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76fd404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76fd4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76fd4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c71444ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (489 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintam_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintm_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintn_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn me
# | ...
# `---data was truncated (10240/17932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555e85f96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e85f93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e85f9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8b0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8b02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8b0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8b0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e85f2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e85f2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e85f118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e85bc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e85bc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8b0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8b02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8b02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e85bc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (492 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmmla_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005641a135deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641a135ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641a135e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff698533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff69858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff698533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff69851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641a12f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641a12f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641a12d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641a0f87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641a0f87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff69851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff69851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff69851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641a0f87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (493 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dd7dadfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd7dadce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd7dae062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e9aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e9aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e9aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e9aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd7da75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd7da75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd7da5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd7d709e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd7d709b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e9aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e9aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e9aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd7d709a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (496 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmaxnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svmaxnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svmaxnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b10a334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b10a331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b10a33562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f37e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f37ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f37e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f37e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b10a2cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b10a2caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b10a2af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b109f5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b109f5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f37e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f37e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f37e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b109f5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (497 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svuzp_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svuzp_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svuzp_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559fb3087eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fb3084e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fb308862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb850b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb850b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb850b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb850b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fb301dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fb301da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fb30028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fb2cb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fb2cb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb850b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb850b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb850b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fb2cb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (500 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_m(<vscale x 8 x bfloat> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558b1f5caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b1f5c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b1f5cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f974c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f974c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b1f560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b1f560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b1f5458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b1f1f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b1f1f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f974c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b1f1f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (502 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e7af629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7af626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7af62a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc50249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc502a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc50249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc50231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7af5bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7af5bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7af5a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7af253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7af253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc50232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc502330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc502330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7af253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (507 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   %10 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %10)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/15164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056446bf70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056446bf6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056446bf7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55e3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55e3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55e3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55e3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056446bf06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056446bf06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056446beeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056446bb9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056446bb9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55e3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55e3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55e3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056446bb9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (512 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005589fb188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589fb185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589fb18962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09aa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09aa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09aa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09aa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589fb11ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589fb11ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589fb1038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589fadb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589fadb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09aa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09aa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09aa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589fadb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (514 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e49025eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e49022e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e4902662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a31d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e48fbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e48fbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e48fa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e48c4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e48c4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e48c4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (516 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_u32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564abb169eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564abb166e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564abb16a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc3dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc3dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc3dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc3dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564abb0ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564abb0ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564abb0e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564abad93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564abad93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc3dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc3dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc3dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564abad93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (518 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559017ca1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559017c9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559017ca262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7381249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7381249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7381231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559017c37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559017c37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559017c1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590178cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590178cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7381232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590178cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (519 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1ro_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1ro_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1ro_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1ro_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e800987eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e800984e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e80098862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdef031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e80091dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e80091da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8009028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8005b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8005b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdef0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8005b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (521 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562bbe48aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bbe487e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bbe48b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86dc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86dc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86dc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86dc803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bbe420bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bbe420a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bbe4058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bbe0b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bbe0b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86dc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86dc8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86dc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bbe0b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (523 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x float>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_f64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x double> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %zt, ptr %zt.addr
# | ...
# `---data was truncated (10240/12466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d3aa2aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3aa2abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3aa2af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d9b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d9b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d9b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d9b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3aa244bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3aa244a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3aa2298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3a9ed8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3a9ed8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d9b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d9b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d9b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3a9ed8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (524 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000564ef6b5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ef6b5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ef6b5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effc2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effc2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effc2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effc2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ef6af3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ef6af3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ef6ad88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ef6787e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ef6787b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effc2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effc2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effc2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ef6787a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (526 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000564f73a7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f73a7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f73a8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f210b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f210b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f210b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f210b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f73a15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f73a15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f739fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f736a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f736a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f210b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f210b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f210b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f736a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (528 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055615d8fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055615d8f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055615d8fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f715d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f715d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f715d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f715d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055615d892bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055615d892a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055615d8778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055615d526e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055615d526b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f715d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f715d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f715d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055615d526a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (530 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldff1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldff1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldff1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/64727) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e8d4fd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8d4fd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8d4fd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12e1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12e1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12e1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12e1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8d4f6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8d4f6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8d4f4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8d4bfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8d4bfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12e1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12e1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12e1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8d4bfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (531 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559d07818eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d07815e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d0781962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26cc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26cc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26cc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26cc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d077aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d077aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d077938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d07442e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d07442b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26cc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26cc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26cc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d07442a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (537 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558bfb11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bfb119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bfb11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8023f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8023f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8023f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8023eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bfb0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bfb0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bfb0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bfad46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bfad46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8023eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8023eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8023eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bfad46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (543 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32f16(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560ffa1f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ffa1f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ffa1f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff227e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff227ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff227e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff227e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ffa18abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ffa18aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ffa16f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ff9e1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ff9e1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff227e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff227e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff227e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ff9e1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (544 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %a.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %b.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x bfloat> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557d862dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d862d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d862dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f5df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d86272bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d86272a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d862578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d85f06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d85f06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d85f06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (546 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvtn_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt1_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt2_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr
# | ...
# `---data was truncated (10240/17058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005616a2a48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616a2a45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616a2a4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51fe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51fe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51fe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51fe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616a29debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616a29dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616a29c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616a2672e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616a2672b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51fe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51fe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51fe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616a2672a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve/minv.c (553 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558ea0624eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ea0621e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ea062562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe167b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe167b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe167b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe167aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ea05babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ea05baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ea059f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ea024ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ea024eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe167aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe167aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe167aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ea024ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (561 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_cvtl_f32_x2(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560a5be5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a5be5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a5be6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f423a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f423a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f423a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f423a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a5bdf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a5bdf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a5bdda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a5ba89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a5ba89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f423a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f423a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f423a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a5ba89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (568 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562e88c92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e88c8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e88c9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cbfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cbfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cbfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cbfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e88c28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e88c28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e88c0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e888bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e888bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cbfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cbfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cbfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e888bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (576 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtssel_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtssel_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtssel_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561aa82faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aa82f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aa82fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9efe21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9efe2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9efe21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9efe203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa8290bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aa8290a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aa82758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561aa7f24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561aa7f24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9efe204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9efe2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9efe2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa7f24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (580 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 7
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x float>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_vnum_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x double>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"
# | ...
# `---data was truncated (10240/10573) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005632d3713eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632d3710e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632d371462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec9cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec9cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec9cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec9cc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632d36a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632d36a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632d368e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632d333de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632d333db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec9cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec9cc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec9cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632d333da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (581 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svadda_f16(<vscale x 16 x i1> %pg, half noundef %initial, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca half, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store half %initial, ptr %initial.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load half, ptr %initial.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %3, half %1, <vscale x 8 x half> %2)
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svadda_f32(<vscale x 16 x i1> %pg, float noundef %initial, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca float, align 4
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store float %initial, ptr %initial.addr, align 4
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load float, ptr %initial.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %3, float %1, <vscale x 4 x float> %2)
# |   ret float %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svadda_f64(<vscale x 16 x i1> %pg, double noundef %initial, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca double, align 8
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store double %initial, ptr %initial.addr, align 8
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load double, ptr %initial.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %3, double %1, <vscale x 2 x double> %2)
# |   ret double %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dc9279deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc9279ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc9279e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9aae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9aaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9aae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9aae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc92733bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc92733a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc927188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc923c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc923c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9aae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9aae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9aae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc923c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (583 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16(<vscale x 8 x half> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f7a2361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7a235ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7a236262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4883e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4883ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4883e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4883e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7a22f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7a22f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7a22dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7a1f8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7a1f8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4883e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4883e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4883e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7a1f8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (584 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_s32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_s64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_u32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_u64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557a140e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a140e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a140e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c5d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c5d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c5d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c5d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a1407abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a1407aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a1405f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a13d0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a13d0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c5d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c5d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c5d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a13d0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (589 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_1() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_2() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_3() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_4() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_5() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_6() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_7() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_9() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_10() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_11() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_12() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_13() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 13)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_14() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 29)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_15() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 30)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_16() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 1)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 2)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560042117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560042114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004211862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f715df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f715df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f715df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f715df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600420adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600420ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600420928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560041d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560041d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f715df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f715df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f715df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560041d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (590 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055738b5cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055738b5cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055738b5d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fe381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fe38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fe381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fe3803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055738b565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055738b565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055738b54a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055738b1f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055738b1f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fe3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fe38050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fe38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055738b1f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (592 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcompact_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcompact_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056501a7f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056501a7f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056501a7f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefe91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056501a78cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056501a78ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056501a7718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056501a420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056501a420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdefe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefe91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056501a420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (595 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x0000564769ed8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564769ed5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564769ed962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0c5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0c538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0c5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0c531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564769e6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564769e6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564769e538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564769b02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564769b02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0c531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0c531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0c531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564769b02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (597 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 3)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 7)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005581f78cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581f78cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581f78ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc05905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc05905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc058ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581f7863bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581f7863a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581f78488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581f74f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581f74f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc058eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc058ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc058ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581f74f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (599 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562d8e8cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d8e8cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d8e8d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24fd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d8e865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d8e865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d8e84a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d8e4f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d8e4f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d8e4f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (601 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svclamp_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c8ac2c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8ac2c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8ac2c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1179933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f117998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1179933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f117991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8ac259bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8ac259a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8ac23e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8abeede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8abeedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f117991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f117991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f117991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8abeeda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (603 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnf1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnf1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnf1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/22483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056040734aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560407347e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056040734b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f162e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f162e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f162e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f162e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604072e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604072e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604072c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560406f74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560406f74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f162e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f162e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f162e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560406f74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (610 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d1e76f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1e76f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1e76f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce8051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1e768abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1e768aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1e766f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1e731ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1e731eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce8051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1e731ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (614 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpkhi_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559334bc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559334bbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559334bc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559334b57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559334b57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559334b3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593347ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593347ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593347eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (616 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055a45e48eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a45e48be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a45e48f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61bcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61bcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61bcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61bcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a45e424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a45e424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a45e4098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a45e0b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a45e0b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61bcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61bcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61bcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a45e0b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (623 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16_1(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtmad_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtmad_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055df3aef8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df3aef5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df3aef962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc45f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc45f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc45f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc45f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df3ae8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df3ae8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df3ae738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df3ab22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df3ab22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc45f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc45f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc45f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df3ab22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (631 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055621c1a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055621c1a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055621c1a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa519733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa51978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa519733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa51971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055621c13abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055621c13aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055621c11f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055621bdcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055621bdceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa51971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa51971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa51971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055621bdcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/andv.c (638 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055a5dd4c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5dd4c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5dd4c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5708049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5708049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5708031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5dd45dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5dd45da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5dd4428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5dd0f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5dd0f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5708032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5dd0f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (642 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtsmul_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtsmul_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtsmul_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005592b002feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592b002ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592b003062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18a2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18a2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18a2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18a2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592affc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592affc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592affaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592afc59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592afc59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18a2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18a2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18a2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592afc59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (644 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558bbaecceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bbaec9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bbaecd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b23a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b23aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b23a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b23a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bbae62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bbae62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bbae478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bbaaf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bbaaf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b23a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b23a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b23a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bbaaf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (646 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f4b4dbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4b4db8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4b4dbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8d6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8d6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8d6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8d6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b4d51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4b4d51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4b4d368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4b49e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4b49e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8d6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8d6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8d6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b49e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (651 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16mf8(<vscale x 8 x half> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b7832b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7832b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7832b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc689849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc689849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc689831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b78324dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b78324da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7832328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b782ee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b782ee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc689832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6898330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b782ee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (654 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpe_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpe_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpe_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005647e5e33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647e5e30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647e5e3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f520cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f520cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f520cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f520cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647e5dc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647e5dc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647e5dae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647e5a5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647e5a5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f520cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f520cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f520cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647e5a5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/recps.c (655 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecps_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecps_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecps_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000564164fcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564164fc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564164fcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1436649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1436649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1436631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564164f61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564164f61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564164f468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564164bf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564164bf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1436632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14366330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564164bf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/orv.c (658 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055a861606eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a861603e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a86160762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70b9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70b90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70b9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70b9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a86159cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a86159ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8615818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a861230e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a861230b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70b9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70b90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70b90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a861230a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (659 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000555f190f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f190f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f190f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5f9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5f9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5f9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5f9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f1908abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f1908aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f1906f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f18d1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f18d1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5f9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5f9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5f9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f18d1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (667 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef2_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef2_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef2_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef2_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055900da01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055900d9fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055900da0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2c4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2c42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2c4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2c4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055900d997bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055900d997a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055900d97c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055900d62be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055900d62bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2c4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2c42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2c42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055900d62ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (670 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32mf8(<vscale x 4 x float> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e56cf5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e56cf5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e56cf6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc58ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc58ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc58ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc58ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e56cef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e56cef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e56ceda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e56cb89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e56cb89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc58ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc58ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc58ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e56cb89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 
FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (674 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005564e18d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564e18d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564e18d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e186ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564e186ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564e18538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564e1502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564e1502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00c2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e1502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (708 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmmla_f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 2 x double>, align 16
# |   %y.addr = alloca <vscale x 2 x double>, align 16
# |   %z.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x, ptr %x.addr, align 16
# |   store <vscale x 2 x double> %y, ptr %y.addr, align 16
# |   store <vscale x 2 x double> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %y.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %z.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b5e059feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5e059ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5e05a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cb3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cb3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cb3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cb3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5e0535bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5e0535a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5e051a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5e01c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5e01c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cb3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cb3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cb3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5e01c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (713 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005579a7456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579a7453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579a745762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f192af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f192af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f192af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f192af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579a73ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579a73eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579a73d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579a7080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579a7080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f192af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f192af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f192af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579a7080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (715 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i)
# |   store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i)
# |   store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056479b9ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056479b9e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056479b9ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcdbd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcdbd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcdbd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcdbced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056479b981bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056479b981a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056479b9668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056479b615e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056479b615b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcdbceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcdbcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcdbcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056479b615a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/nor.c (733 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnor_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558cc6765eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cc6762e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cc676662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f63933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f6398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f63933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f6391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cc66fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cc66fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cc66e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cc638fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cc638fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f6391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f6391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f6391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cc638fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/dup.c (735 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_u8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_u16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_n_f16(half noundef %op) #0 {
# | entry:
# |   %op.addr = alloca half, align 2
# |   store half %op, ptr %op.addr, align 2
# |   %0 = load half, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_n_f32(float noundef %op) #0 {
# | entry:
# |   %op.addr = alloca float, align 4
# |   store float %op, ptr %op.addr, align 4
# |   %0 = load float, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_n_f64(double noundef %op) #0 {
# | entry:
# |   %op.addr = alloca double, align 8
# |   store double %op, ptr %op.addr, align 8
# |   %0 = load double, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b8(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 16 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 16 x i1> %.splatinsert, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
# |   ret <vscale x 16 x i1> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b16(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 8 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 8 x i1> %.splatinsert, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b32(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 4 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 4 x i1> %.splatinsert, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b64(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 2 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 2 x i1> %.splatinsert, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_n_bf16(bfloat noundef %op) #0 {
# | entry:
# |   %op.addr = alloca bfloat, align 2
# |   store bfloat %op, ptr %op.addr, align 2
# |   %0 = load bfloat, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8_z(<vscale x 16 x i1> %pg, i8 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i8, align 1
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i8, ptr %op.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16_z(<vscale x 16 x i1> %pg, i16 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i16, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vsca
# | ...
# `---data was truncated (10240/49557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055e59b3d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e59b3d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e59b3d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7033733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f703378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7033733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f703371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e59b369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e59b369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e59b34e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e59affde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e59affdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f703371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f703371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f703371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e59affda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (738 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005584d7df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584d7df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584d7dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584d7d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584d7d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584d7d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584d7a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584d7a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87a9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584d7a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (753 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056362c512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056362c50fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056362c51362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ab505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ab55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ab505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ab4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056362c4a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056362c4a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056362c48d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056362c13ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056362c13cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ab4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ab4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ab4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056362c13ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/nand.c (754 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnand_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055b0f6b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0f6b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0f6b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7a3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7a318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7a3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7a311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0f6ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0f6ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0f6ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0f6766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0f6766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7a311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7a311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7a311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0f6766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (779 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfalse_b() #0 {
# | entry:
# |   ret <vscale x 16 x i1> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000557c36f36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c36f33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c36f3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6466249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64662a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6466249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6466231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c36eccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c36ecca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c36eb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c36b60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c36b60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6466232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64662330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64662330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c36b60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/addv.c (780 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svaddv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svaddv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svaddv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | a
# | ...
# `---data was truncated (10240/10826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x00005642f3e33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f3e30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f3e3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85c0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85c058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85c0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85c051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f3dc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f3dc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f3dae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f3a5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f3a5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85c051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85c051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85c051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f3a5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (782 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrte_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrte_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrte_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055ea09456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea09453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea0945762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb80e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb80e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb80e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb80e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea093ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea093eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea093d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea09080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea09080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb80e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb80e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb80e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea09080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (784 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef4_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef4_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef4_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef4_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560d2ea20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d2ea1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d2ea2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b1b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b1b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b1b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b1b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d2e9b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d2e9b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d2e99b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d2e64ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d2e64ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b1b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b1b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b1b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d2e64aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (795 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556941b16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556941b13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556941b1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67b2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67b278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67b2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67b271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556941aacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556941aaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556941a918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556941740e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556941740b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67b271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67b271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67b271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556941740a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (797 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmmla_f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 4 x float>, align 16
# |   %z.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 4 x float> %y, ptr %y.addr, align 16
# |   store <vscale x 4 x float> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %y.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aafb17aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aafb177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aafb17b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca3cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca3cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca3cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca3caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aafb110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aafb110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aafb0f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aafada4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aafada4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca3caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca3caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca3caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aafada4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (802 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef3_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef3_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef3_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef3_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005599e5de4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599e5de1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599e5de562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f483b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f483b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f483b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f483b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599e5d7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599e5d7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599e5d5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599e5a0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599e5a0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f483b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f483b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f483b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599e5a0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (805 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x
# | ...
# `---data was truncated (10240/51854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005630ab4f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630ab4f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630ab4f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d07a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d07aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d07a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d07a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630ab48cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630ab48ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630ab4718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630ab120e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630ab120b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d07a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d07a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d07a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630ab120a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve/len.c (811 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c         | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vscale.i64() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055c3117b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3117afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3117b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1787e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1787ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1787e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1787e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c311748bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c311748a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c31172d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3113dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3113dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1787e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1787e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1787e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3113dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (814 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrts_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrts_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrts_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558a952e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a952e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a952e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03e611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a9527cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a9527ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a952618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a94f10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a94f10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03e611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a94f10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (823 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_s8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_s16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_s32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_s64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_u8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_u16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_u32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_u64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svundef_f16() #0 {
# | entry:
# |   ret <vscale x 8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svundef_f32() #0 {
# | entry:
# |   ret <vscale x 4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svundef_f64() #0 {
# | entry:
# |   ret <vscale x 2 x double> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_mf8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svundef_bf16() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> undef
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005647f31b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647f31b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647f31ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0971133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f097118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0971133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f097111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647f314fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647f314fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647f31348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647f2de3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647f2de3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f097111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f097111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f097111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647f2de3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (827 of 27910)
******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu  -target-cpu swift   -target-feature +fullfp16 -ffreestanding   -flax-vector-conversions=none   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7s-apple-darwin"
# | 
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p0.addr.i1, align 8
# |   store <8 x i8> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %8, ptr %__ret.i3, align 8
# |   %9 = load <8 x i8>, ptr %__ret.i3, align 8
# |   %add.i = add <8 x i8> %3, %9
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x i16>, align 8
# |   %__p1.addr.i2 = alloca <4 x i16>, align 8
# |   %__ret.i3 = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %5 = load <4 x i16>, ptr %__p2.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p0.addr.i1, align 8
# |   store <4 x i16> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16>
# |   %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %8, ptr %__ret.i3, align 8
# |   %9 = load <4 x i16>, ptr %__ret.i3, align 8
# |   %add.i = add <4 x i16> %3, %9
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %10 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <2 x i32>, align 8
# |   %__p1.addr.i2 = alloca <2 x i32>, align 8
# |   %__ret.i3 = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x i32>, ptr %__p2.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p0.addr.i1, align 8
# |   store <2 x i32> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32>
# |   %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %8, ptr %__ret.i3, align 8
# |   %9 = load <2 x i32>, ptr %__ret.i3, align 8
# |   %add.i = add <2 x i32> %3, %9
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %10 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, pt
# | ...
# `---data was truncated (10240/2159854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d937d16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d937d13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d937d1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3a4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3a4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3a4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3a4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d937cacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d937caca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d937c918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d937940e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d937940b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3a4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3a4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3a4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d937940a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve/orn.c (829 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svorn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000056246a257eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056246a254e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056246a25862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08f831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056246a1edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056246a1eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056246a1d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562469e81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562469e81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08f831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562469e81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (833 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e9af3e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9af3dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9af3e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcbd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcbd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcbd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcbd831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9af378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9af378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9af35d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9af00ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9af00cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcbd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcbd8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcbd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9af00ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (842 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_scatter_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %3, <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) #
# | ...
# `---data was truncated (10240/43213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000562fbe9fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fbe9f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fbe9fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82c7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82c7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82c7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82c7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbe991bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fbe991a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fbe9768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fbe625e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fbe625b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82c7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82c7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82c7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fbe625a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (847 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 8 x i16> %3 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %6, <vscale x 8 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | e
# | ...
# `---data was truncated (10240/32866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000563601a9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563601a9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563601a9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad8c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad8c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad8c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad8c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563601a34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563601a34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563601a198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636016c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636016c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad8c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad8c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad8c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636016c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (860 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #4
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64
# | ...
# `---data was truncated (10240/21923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005621864d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621864d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621864d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f218c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f218c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f218c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f218c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056218646cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056218646ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621864518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562186100e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562186100b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f218c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f218c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f218c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562186100a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (865 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c85468ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c854689e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c85468d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7344249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73442a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7344249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7344231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c854622bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c854622a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8546078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8542b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8542b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7344232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73442330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73442330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8542b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (874 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556176c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556176bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556176c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3880a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3880aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3880a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3880a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556176b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556176b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556176b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055617682be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055617682bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3880a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3880a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3880a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055617682ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (875 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fccdd29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fccdd26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fccdd2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1302933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f130298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1302933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f130291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fccdcbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fccdcbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fccdca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fccd953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fccd953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f130291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f130291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f130291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fccd953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (876 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d7dbdc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7dbdbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7dbdc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56c5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56c518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56c5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56c511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7dbd58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7dbd58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7dbd3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7db9ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7db9ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56c511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56c511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56c511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7db9eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (878 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x
# | ...
# `---data was truncated (10240/66009) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555b84dc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b84dc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b84dc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b9c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b9c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b9c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b9c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b84d59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b84d59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b84d3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b849ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b849edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b9c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b9c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b9c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b849eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (897 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <
# | ...
# `---data was truncated (10240/50499) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fece0d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fece0d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fece0d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90df249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90df2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90df249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90df231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fece06abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fece06aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fece04f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fecdcfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fecdcfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90df232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90df2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90df2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fecdcfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (925 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558a3bd2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a3bd29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a3bd2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6134a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6134aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6134a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6134a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a3bcc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a3bcc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a3bca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a3b956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a3b956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6134a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6134a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6134a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a3b956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (926 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d2e6f59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2e6f56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2e6f5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2e6eefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2e6eefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2e6ed48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2e6b83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2e6b83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30e191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2e6b83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (928 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c16ab32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c16ab2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c16ab3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7092649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7092649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7092631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c16aac8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c16aac8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c16aaad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c16a75ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c16a75cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7092632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70926330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c16a75ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (930 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563ea6f34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ea6f31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ea6f3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e08e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e08ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e08e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e08e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ea6ecabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ea6ecaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ea6eaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ea6b5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ea6b5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e08e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e08e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e08e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ea6b5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (947 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svzero_zt() #0 {
# | entry:
# |   call void @llvm.aarch64.sme.zero.zt(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563075697eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563075694e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307569862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d5d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d5d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d5d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d5d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307562dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056307562da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630756128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630752c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630752c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d5d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d5d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d5d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630752c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (949 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555913527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555913524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055591352862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe577733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe57778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe577733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe57771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559134bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559134bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559134a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555913151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555913151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe57771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe57771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe57771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555913151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (955 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svldr_zt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svstr_zt(ptr noundef %base) #2 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) }
# | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055585e4cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055585e4c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055585e4cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d95533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d9558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d95533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d9551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055585e462bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055585e462a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055585e4478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055585e0f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055585e0f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d9551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d9551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d9551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055585e0f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (988 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsetffr() #0 {
# | entry:
# |   call void @llvm.aarch64.sve.setffr()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.setffr() #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aa12846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa12843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa1284762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fa8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fa878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fa8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fa871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa127dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa127dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa127c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa12470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa12470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fa871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fa871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fa871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa12470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (992 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562104fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562104fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562104fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4f0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4f04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4f0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4f0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562104f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562104f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562104f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562104c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562104c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4f0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4f04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4f04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562104c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (993 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563b6299aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b62997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b6299b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe03b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe03b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe03b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe03b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b62930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b62930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b629158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b625c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b625c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe03b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe03b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe03b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b625c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (1005 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr_z(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055d842a3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d842a37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d842a3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f61533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f6158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f61533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f6151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8429d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8429d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8429b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d842664e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d842664b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f6151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f6151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f6151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d842664a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (1008 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559f7b12aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f7b127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f7b12b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08ca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08ca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08ca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08ca631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f7b0c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f7b0c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f7b0a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f7ad54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f7ad54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08ca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08ca6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08ca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f7ad54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (1020 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559b0d4a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b0d4a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b0d4a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c84249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c842a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c84249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c84231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b0d43bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b0d43ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b0d4208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b0d0cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b0d0cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c84232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c842330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c842330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b0d0cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (1025 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560ccefe1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ccefdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ccefe262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b68133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b68133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ccef77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ccef77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ccef5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ccec0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ccec0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b6811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ccec0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (1049 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrffr(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005595e766feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595e766ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595e767062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba68733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba6878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba68733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba6871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e7605bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595e7605a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595e75ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595e7299e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595e7299b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba6871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba6871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba6871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e7299a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (1057 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <4 x half>, align 8
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6)
# |   store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %9 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %9, ptr %__ret, align 8
# |   %10 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %10, ptr %tmp, align 8
# |   %11 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <16 x i8>, align 16
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   store <16 x i8> %2, ptr %__s2, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <16 x i8>, ptr %__s2, align 16
# |   %7 = load i64, ptr %__s4, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %8, ptr %__ret, align 8
# |   %9 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %9, ptr %tmp, align 8
# |   %10 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <16 x i8>, ptr %__s0, align 16
# |   %5 = load <16 x i8>, ptr %__s1, align 16
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3)
# |   store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16
# |   %9 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <
# | ...
# `---data was truncated (10240/24508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055be257b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be257b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be257b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a02533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a0258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a02533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a0251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be2574ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be2574ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be257338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be253e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be253e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a0251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a0251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a0251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be253e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/cx-complex-range.c (1077 of 27910)
******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %coerce.real, ptr %retval.realp, align 4
# |   store float %coerce.imag, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__divsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %coerce.real, ptr %.realp1, align 4
# |   store float %coerce.imag, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul_ac = fmul float %a.real, %b.real
# |   %mul_bd = fmul float %a.imag, %b.imag
# |   %mul_ad = fmul float %a.real, %b.imag
# |   %mul_bc = fmul float %a.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %real_mul_phi, ptr %retval.realp, align 4
# |   store float %imag_mul_phi, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__mulsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul_ac = fmul float %.real, %b.real
# |   %mul_bd = fmul float %.imag, %b.imag
# |   %mul_ad = fmul float %.real, %b.imag
# |   %mul_bc = fmul float %.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %real_mul_phi, ptr %.realp2, align 4
# |   store float %imag_mul_phi, ptr %.imagp3, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b = alloca { double, double }, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %2, align 8
# |   %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %3, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load doub
# | ...
# `---data was truncated (10240/29171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b5e6d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5e6d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5e6d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facb4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facb4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facb4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facb4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5e6cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5e6cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5e6cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5e6969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5e6969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facb4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facb4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facb4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5e6969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (1084 of 27910)
******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
# |   ret <8 x float> %shufp
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> <i32 1, i32 0>
# |   ret <2 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 1, i32 2, i32 3>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <4 x double> %b, ptr %b.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <4 x double>, ptr %b.addr, align 32
# |   %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
# |   ret <4 x double> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
# |   ret <8 x float> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <4 x i64>, align 32
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <4 x i64> %b, ptr %b.addr, align 32
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <4 x i64>, ptr %b.addr, align 32
# |   %3 = bitcast <4 x i64> %2 to <8 x i32>
# |   %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
# |   %4 = bitcast <8 x i32> %vperm to <4 x i64>
# |   ret <4 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3
# |   store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__d.i = alloca double, align 8
# |   %.compoundliteral.i = alloca <4 x double>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load double, ptr %1, align 1
# |   store double %2, ptr %__d.i, align 8
# |   %3 = load double, ptr %__d.i, align 8
# |   %vecinit.i = insertelement <4 x double> poison, double %3, i32 0
# |   %4 = load double, ptr %__d.i, align 8
# |   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1
# |   %5 = load double, ptr %__d.i, align 8
# |   %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2
# |   %6 = load double, ptr %__d.i, align 8
# |   %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3
# |   store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32
# |   %7 = load <4 x double>, ptr %.compoundliteral.i, align 32
# |   ret <4 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <8 x float>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <8 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3
# |   %7 = load float, ptr %__f.i, align 4
# |   %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4
# |   %8 = load float, ptr %__f.i, align 4
# |   %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5
# |   %9 = load float, ptr %__f.i, align 4
# |   %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6
# |   %10 = load float, ptr %__f.i, align 4
# |   %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7
# |   store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32
# |   %11 = load <8 x float>, ptr %.compoundliteral.i, align 32
# |   ret <8 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <4 x float>, align 16
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
# |   ret <8 x float> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <2 x double>, align 16
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
# |   ret <4 x double> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <2 x i64>, ptr
# | ...
# `---data was truncated (10240/21933) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593e7267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593e7264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593e726862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f080ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f080ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f080ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f080ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e71fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593e71fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593e71e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593e6e91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593e6e91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f080ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f080ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f080ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e6e91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1090 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__ret.i, align 8
# |   %2 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 {
# | entry:
# |   
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x00005563c111ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563c1119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563c111d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff964505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff96455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff964505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9644ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c10b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563c10b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563c10978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563c0d46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563c0d46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9644eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9644ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9644ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c0d46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (1091 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i)
# |   store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i)
# |   store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane)
# |   store <4 x float> %vdot2, ptr %ref.tmp, align 16
# |   %7 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %7, ptr %__ret, align 16
# |   %8 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %8, ptr %tmp, align 16
# |   %9 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aa
# | ...
# `---data was truncated (10240/11256) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055776e286eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055776e283e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055776e28762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb04c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb04c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb04c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb04c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055776e21cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055776e21ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055776e2018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055776deb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055776deb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb04c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb04c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb04c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055776deb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (1110 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 
# | ...
# `---data was truncated (10240/35980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055ca50723eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca50720e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca5072462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd59f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd59f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd59f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd59f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca506b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca506b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca5069e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca5034de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca5034db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd59f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd59f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd59f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca5034da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1121 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <4 x float> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = fcmp oeq <4 x float> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = icmp eq <4 x i32> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = 
# | ...
# `---data was truncated (10240/125481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ab966beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ab9668e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ab966c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff84e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff84e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ab9601bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ab9601a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ab95e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ab9295e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ab9295b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff84e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ab9295a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (1184 of 27910)
******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13)
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundlit
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9d7dafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9d7dace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9d7db062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce00933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce0098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce00933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce0091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9d7d45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9d7d45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9d7d2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9d79d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9d79d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce0091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce0091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce0091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9d79d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (1188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %isneg.i = icmp slt i32 %1, 0
# |   %not.i = xor i32 %1, -1
# |   %2 = select i1 %isneg.i, i32 %not.i, i32 %1
# |   %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false)
# |   %4 = sub nuw i32 %3, 1
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rev_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %2 = call i32 @llvm.bitreverse.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rd.addr.i, align 4
# |   %4 = load i32, ptr %__rs1.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rs1.addr.i, align 4
# |   %4 = load i32, ptr %__rd.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false)
# |   ret i32 %elt.abs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function At
# | ...
# `---data was truncated (10240/1228637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x0000562b40805eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b40802e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b4080662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd003849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0038a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd003849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd003831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b4079bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b4079ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b407808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b4042fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b4042fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd003832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0038330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0038330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b4042fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40
FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (1205 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <2 x float>, align 8
# |   store <2 x float> %x, ptr %x.addr, align 8
# |   %0 = load <2 x float>, ptr %x.addr, align 8
# |   %1 = bitcast <2 x float> %0 to <8 x i8>
# |   ret <8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <8 x i8> %0 to <2 x float>
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <4 x float>, align 16
# |   store <4 x float> %x, ptr %x.addr, align 16
# |   %0 = load <4 x float>, ptr %x.addr, align 16
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i128, align 16
# |   store i128 %x, ptr %x.addr, align 16
# |   %0 = load i128, ptr %x.addr, align 16
# |   %1 = bitcast i128 %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to i128
# |   ret i128 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055a6920a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6920a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6920a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a34c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a34ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a34c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a34c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a69203abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a69203aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a69201f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a691ccee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a691cceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a34c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a34c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a34c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a691ccea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (1247 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | declare void @g(<1 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_cst(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %vecext = extractelement <16 x i8> %0, i32 3
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# |  #0 0x000055f54d724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f54d721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f54d72562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feda2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feda258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feda2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feda251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f54d6babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f54d6baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f54d69f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f54d34ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f54d34eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feda251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feda251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feda251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f54d34ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (1266 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i
# | ...
# `---data was truncated (10240/23350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000056210a6aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056210a6abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210a6af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22bed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22bed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22bed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22bed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210a644bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210a644a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056210a6298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056210a2d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056210a2d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22bed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22bed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22bed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210a2d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (1268 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret bfloat %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x bfloat> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | !llvm.errno.tbaa = !{!6}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# | !6 = !{!7, !8, i64 0}
# | !7 = !{!"__libc_errno", !8, i64 0}
# | !8 = !{!"int", !9, i64 0}
# | !9 = !{!"omnipotent char", !10, i64 0}
# | !10 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055dd520d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd520d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd520d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2ad649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2ad6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2ad649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2ad631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd5206cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd5206ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd520518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd51d00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd51d00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2ad632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2ad6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2ad6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd51d00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1346 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = fneg <8 x half> %1
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = fneg <4 x float> %1
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %c, ptr %c.addr, align 2
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = mul <8 x i16> %0, %.splat
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = add <8 x i16> %2, %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i32 %c, ptr %c.addr, align 4
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = mul <4 x i32> %0, %.splat
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = add <4 x i32> %2, %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, ali
# | ...
# `---data was truncated (10240/60411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000556afc489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556afc486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556afc48a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45d6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45d6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45d6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45d6a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556afc41fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556afc41fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556afc4048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556afc0b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556afc0b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45d6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45d6a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45d6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556afc0b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (1364 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = sitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = uitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = sitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = uitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptosi <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptosi <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptoui <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptoui <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm
# | ...
# `---data was truncated (10240/37578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f06f2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f06f29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f06f2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb46c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb46ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb46c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb46c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f06ec2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f06ec2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f06ea78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f06b56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f06b56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb46c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb46c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb46c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f06b56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (1378 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = mul <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = mul <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = mul <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fmul <4 x float> %0, %1
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.m
# | ...
# `---data was truncated (10240/21288) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055aed3dd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aed3dd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aed3dd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd296c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd296ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd296c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd296c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aed3d6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aed3d6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aed3d508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aed39ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aed39ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd296c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd296c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd296c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aed39ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (1388 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align
# | ...
# `---data was truncated (10240/30281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000559334244eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559334241e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055933424562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37df01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37df0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37df01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37df003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593341dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593341daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593341bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559333e6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559333e6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37df004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37df0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37df0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559333e6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (1401 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1
# | ...
# `---data was truncated (10240/26476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3e95fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3e95f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3e95fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa9a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa9a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3e9591bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3e9591a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3e95768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3e9225e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3e9225b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa9a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3e9225a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/arm64-lanes.c (1405 of 27910)
******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %src, ptr %src.addr, align 8
# |   %0 = load <2 x float>, ptr %src.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vdups_lane = extractelement <2 x float> %1, i32 0
# |   store float %vdups_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <1 x double>, ptr %src.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vdupd_lane = extractelement <1 x double> %1, i32 0
# |   store double %vdupd_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dec2cfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dec2cfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dec2cfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dec2c93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dec2c93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dec2c788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dec2927e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dec2927b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dec2927a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (1411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcreate_v_f16m1_f16m2(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %3 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %2, <vscale x 4 x half> %1, i64 4)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m1_f16m4(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %5 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %4, <vscale x 4 x half> %1, i64 4)
# |   %6 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %5, <vscale x 4 x half> %2, i64 8)
# |   %7 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %6, <vscale x 4 x half> %3, i64 12)
# |   ret <vscale x 16 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m1_f16m8(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   %v4.addr = alloca <vscale x 4 x half>, align 2
# |   %v5.addr = alloca <vscale x 4 x half>, align 2
# |   %v6.addr = alloca <vscale x 4 x half>, align 2
# |   %v7.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x half> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x half> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x half> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x half> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x half>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x half>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x half>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x half>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %9 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %8, <vscale x 4 x half> %1, i64 4)
# |   %10 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %9, <vscale x 4 x half> %2, i64 8)
# |   %11 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %10, <vscale x 4 x half> %3, i64 12)
# |   %12 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %11, <vscale x 4 x half> %4, i64 16)
# |   %13 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %12, <vscale x 4 x half> %5, i64 20)
# |   %14 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %13, <vscale x 4 x half> %6, i64 24)
# |   %15 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %14, <vscale x 4 x half> %7, i64 28)
# |   ret <vscale x 32 x half> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m2_f16m4(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %3 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %2, <vscale x 8 x half> %1, i64 8)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m2_f16m8(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   %v2.addr = alloca <vscale x 8 x half>, align 2
# |   %v3.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %5 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %4, <vscale x 8 x half> %1, i64 8)
# |   %6 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %5, <vscale x 8 x half> %2, i64 16)
# |   %7 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %6, <vscale x 8 x half> %3, i64 24)
# |   ret <vscale x 32 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m4_f16m8(<vscale x 16 x half> %v0, <vscale x 16 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x half>, align 2
# |   %v1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %0, i64 0)
# |   %3 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %2, <vscale x 16 x half> %1, i64 16)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcreate_v_f32m1_f32m2(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 2 x float>, align 4
# |   %v1.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %v0, ptr %v0.addr, align 4
# |   store <vscale x 2 x float> %v1, ptr %v1.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %v0.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %v1.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %0, i64 0)
# |   %3 = call <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/593252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c18ebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c18eb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c18ebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc891849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc891849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc891831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c18e52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c18e52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c18e378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c18ae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c18ae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc891832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c18ae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (1460 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = add <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fadd <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = add <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fadd <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055d2f2f14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2f2f11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2f2f1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb81bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb81bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb81bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb81bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2f2eaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2f2eaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2f2e8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2f2b3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2f2b3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb81bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb81bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb81bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2f2b3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (1473 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = sub <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fsub <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = sub <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fsub <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005631c481ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631c4819e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631c481d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe718533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe71858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe718533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe71851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631c47b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631c47b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631c47978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631c4446e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631c4446b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe71851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe71851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe71851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631c4446a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (1481 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 3
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 2
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_374 = alloca <4 x bfloat>, align 8
# |   %__s0_374 = alloca <4 x bfloat>, align 8
# |   %__s2_374 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.add
# | ...
# `---data was truncated (10240/18871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616ba171eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616ba16ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616ba17262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde0f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde0f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde0f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde0f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616ba107bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616ba107a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616ba0ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616b9d9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616b9d9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde0f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde0f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde0f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616b9d9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (1495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x half> %ma
# | ...
# `---data was truncated (10240/619127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b16ff3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b16ff0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b16ff462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54cfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54cfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54cfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54cfaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b16f89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b16f89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b16f6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b16c1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b16c1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54cfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54cfaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54cfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b16c1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (1507 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561885cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561885cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561885d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f36849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f368a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f36849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f36831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556188565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556188565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055618854a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561881f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561881f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f36832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f368330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f368330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561881f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (1523 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b7fa1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b7fa1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b7fa2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a7a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a7a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b7f9b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b7f9b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b7f99a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b7f649e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b7f649b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a7a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b7f649a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (1532 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x half>
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x float>
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 {
# | entry:
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 {
# | entry:
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000555604501eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556044fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055560450262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7792449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7792449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7792431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555604497bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555604497a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055560447c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055560412be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055560412bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7792432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77924330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055560412ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (1534 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__p2.addr.i3 = alloca <4 x half>, align 8
# |   %__ret.i4 = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i3, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %13, ptr %__ret.i4, align 8
# |   %14 = load <4 x half>, ptr %__ret.i4, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__p1.addr.i2 = alloca <8 x half>, align 16
# |   %__p2.addr.i3 = alloca <8 x half>, align 16
# |   %__ret.i4 = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i1, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i3, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %13, ptr %__ret.i4, align 16
# |   %14 = load <8 x half>, ptr %__ret.i4, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <4 x half>, ptr %__s0, align 8
# |   %4 = load <4 x half>, ptr %__s1, align 8
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <4 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %9 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i, align 8
# |   store <4 x half> %4, ptr %__p1.addr.i, align 8
# |   store <4 x half> %9, ptr %__p2.addr.i, align 8
# |   %10 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %13 = bitcast <8 x i8> %10 to <4 x half>
# |   %14 = bitcast <8 x i8> %11 to <4 x half>
# |   %15 = bitcast <8 x i8> %12 to <4 x half>
# |   %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13)
# |   store <4 x half> %16, ptr %ref.tmp.i, align 8
# |   %17 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %17, ptr %__ret.i, align 8
# |   %18 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %18, ptr %__ret, align 8
# |   %19 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %19, ptr %tmp, align 8
# |   %20 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %20
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <8 x half>, ptr %__s0, align 16
# |   %4 = load <8 x half>, ptr %__s1, align 16
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <8 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3
# |   %9 = load half, ptr %__s2, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4
# |   %10 = load half, ptr %__s2, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5
# |   %11 = load half, ptr %__s2, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6
# |   %12 = load half, ptr %__s2, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %13 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i, align 16
# |   store <8 x half> %4, ptr %__p1.addr.i, align 16
# |   store <8 x half> %13, ptr %__p2.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %15 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %16 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %17 = bitcast <16 x i8> %14 to <8 x half>
# |   %18 = bitcast <16 x i8> %15 to <8 x half>
# |   %19 = bitcast <16 x i8> %16 to <8 x half>
# |   %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17)
# |   store <8 x half> %20, ptr %ref.tmp.i, align 16
# |   %21 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %21, ptr %__ret.i, align 16
# |   %22 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %22, ptr %__ret, align 16
# |   %23 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %23, ptr %tmp, align 16
# |   %24 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half
# | ...
# `---data was truncated (10240/31903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005600865caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600865c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600865cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7200d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7200d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7200d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7200ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560086560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560086560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600865458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600861f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600861f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7200ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7200cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7200cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600861f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (1578 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e07ee48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e07ee45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e07ee4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f140b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f140b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f140b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f140b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e07eddebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e07eddea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e07edc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e07ea72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e07ea72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f140b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f140b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f140b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e07ea72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (1580 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1)
# |   store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1)
# |   store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca double, align 8
# |   %ref.tmp.i = alloca double, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1)
# |   store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8
# |   %2 = load double, ptr %ref.tmp.i, align 8
# |   store double %2, ptr %__ret.i, align 8
# |   %3 = load double, ptr %__ret.i, align 8
# |   ret double %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16>
# |   %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3)
# |   store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32>
# |   %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9)
# |   store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %2, ptr %__ret, align 8
# |   %3 = load <4 x i16>, p
# | ...
# `---data was truncated (10240/770739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055cedb9d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cedb9d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cedb9da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37fc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cedb96fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cedb96fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cedb9548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cedb603e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cedb603b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37fc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cedb603a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (1614 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone   -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %add.i = fadd <4 x float> %2, %3
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %sub.i = fsub <2 x float> %2, %3
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <4 x float> %2, %3
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <2 x double> %2, %3
# |   store <2 x double> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <4 x float> %2, %3
# |   store <4 x float> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <2 x double> %2, %3
# |   store <2 x double> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   %v3.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   store <2 x float> %v3, ptr %v3.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   %2 = load <2 x float>, ptr %v3.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x float>, ptr %__p2.addr.i, align 8
# |   %mul.i = fmul <2 x float> %4, %5
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %6 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   %v3.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   store <4 x float> %v3, ptr %v3.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   %2 = load <4 x float>, ptr %v3.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load <4 x float>, ptr %__p2.addr.i, align 16
# |   %mul.i = fmul <4 x float> %4, %5
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/91378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056193c604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056193c601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056193c60562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe650e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe650e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe650e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe650e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056193c59abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056193c59aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056193c57f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056193c22ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056193c22eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe650e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe650e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe650e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056193c22ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (1623 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca6ebe1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca6ebdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca6ebe262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0774849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07748a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0774849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0774831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca6eb77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca6eb77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca6eb5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca6e80be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca6e80bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0774832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07748330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07748330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca6e80ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (1701 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc    -triple aarch64 -target-feature +neon -target-feature +bf16    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0_824.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8
# |   store <4 x i16> %1, ptr %__s0.i, align 8
# |   %2 = load <8 x i8>, ptr %__s0.i, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   %4 = zext <4 x i16> %3 to <4 x i32>
# |   %vshll_n.i = shl <4 x i32> %4, splat (i32 16)
# |   store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16
# |   %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %6, ptr %tmp.i, align 16
# |   %7 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret_824.i, align 16
# |   %9 = load <4 x float>, ptr %__ret_824.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   store <4 x bfloat> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8
# |   store <4 x bfloat> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %4, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %inactive.addr = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <4 x float>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = fptrunc <4 x float> %6 to <4 x bfloat>
# |   %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %8, ptr %ref.tmp.i, align 16
# |   %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca bfloat, align 2
# |   %ref.tmp.i = alloca bfloat, align 2
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   store bfloat %2, ptr %ref.tmp.i, align 2
# |   %3 = load bfloat, ptr %ref.tmp.i, align 2
# |   store bfloat %3, ptr %__ret.i, align 2
# |   %4 = load bfloat, ptr %__ret.i, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load 
# | ...
# `---data was truncated (10240/10974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556e72b0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e72b08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e72b0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe090333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe09038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe090333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe09031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e72aa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e72aa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e72a868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e72735e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e72735b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe09031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe09031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe09031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e72735a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (1740 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <8 x i16> %2, %3
# |   store <8 x i16> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <4 x i32> %2, %3
# |   store <4 x i32> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   s
# | ...
# `---data was truncated (10240/798827) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bbbf6e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbbf6dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbbf6e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c9a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c9a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c9a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c9a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbbf676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbbf676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbbf65b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbbf30ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbbf30ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c9a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c9a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c9a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbbf30aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (1741 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, a
# | ...
# `---data was truncated (10240/13410) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564a9b1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564a9b17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564a9b1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b5d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b5d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b5d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b5d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564a9ab0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564a9ab0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564a9a958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564a9744e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564a9744b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b5d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b5d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b5d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564a9744a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-mfp8.c (1762 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 {
# | entry:
# |   %mfp8.addr = alloca <1 x i8>, align 1
# |   %f1n = alloca [10 x <1 x i8>], align 1
# |   store <1 x i8> %mfp8, ptr %mfp8.addr, align 1
# |   %0 = load <1 x i8>, ptr %mfp8.addr, align 1
# |   %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   store <1 x i8> %0, ptr %arrayidx, align 1
# |   %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   %1 = load <1 x i8>, ptr %arrayidx1, align 1
# |   ret <1 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   ret <1 x i8> %mfp8ext
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   %v.addr = alloca <1 x i8>, align 1
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   store <1 x i8> %v, ptr %v.addr, align 1
# |   %0 = load <1 x i8>, ptr %v.addr, align 1
# |   %1 = load i32, ptr %i.addr, align 4
# |   %2 = load <16 x i8>, ptr %x.addr, align 16
# |   %3 = bitcast <1 x i8> %0 to i8
# |   %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1
# |   store <16 x i8> %vecins, ptr %x.addr, align 16
# |   %4 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# |  #0 0x000056205cdb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056205cdb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056205cdb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6829d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6829d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6829d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6829d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056205cd49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056205cd49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056205cd2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056205c9dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056205c9ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6829d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6829d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6829d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056205c9dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (1768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x float
# | ...
# `---data was truncated (10240/338684) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575e2718eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575e2715e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575e271962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f186f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f186f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f186f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f186f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575e26aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575e26aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575e26938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575e2342e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575e2342b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f186f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f186f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f186f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575e2342a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (1786 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnda.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i)
# |   store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndp.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i)
# |   store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2)
# |   store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x half>
# |   store <4 x half> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__ret.i3 = alloca <8 x half>, align 16
# |   %__p0.addr.i.i = alloca <4 x float>, align 16
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 16
# |   %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   %6 = fptrunc <4 x float> %5 to <4 x half>
# |   store <4 x half> %6, ptr %ref.tmp.i.i, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %7, ptr %__ret.i.i, align 8
# |   %8 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %2, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %8, ptr %__p1.addr.i2, align 8
# |   %9 = load <4 x half>, ptr %__p0.addr.i1, align 8
# |   %10 = load <4 x half>, ptr %__p1.addr.i2, align 8
# |   %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i3, align 16
# |   %11 = load <8 x half>, ptr %__ret.i3, align 16
# |   store <8 x half> %11, ptr %__ret.i, align 16
# |   %12 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fpext <4 x half> %2 to <4 x float>
# |   store <4 x float> %3, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__ret.i2 = alloca <4 x half>, align 8
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x half>, ptr %__ret.i2, align 8
# |   store <4 x half> %4, ptr %__p0.addr.i.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %7 = fpext <4 x half> %6 to <4 x float>
# |   store <4 x float> %7, ptr %ref.tmp.i.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %8, ptr %__ret.i.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i.i, align 16
# |   store <4 x float> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055efd7c1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efd7c1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efd7c2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f7f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f7f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f7f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f7f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efd7bb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efd7bb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efd7b9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efd7849e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efd7849b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f7f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f7f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f7f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efd7849a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (1808 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <16 x i8> %4 to <8 x half>
# |   %fmla1 = bitcast <16 x i8> %3 to <8 x half>
# |   %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %fmla2, ptr %ref.tmp, align 16
# |   %7 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %7, ptr %__ret, align 16
# |   %8 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %8, ptr %tmp, align 16
# |   %9 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %10, ptr %__ret, align 8
# |   %11 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %11, ptr %tmp, align 8
# |   %12 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16
# | ...
# `---data was truncated (10240/13273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560261fc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560261fc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560261fc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f909f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f909f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f909f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f909f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560261f5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560261f5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560261f438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560261bf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560261bf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f909f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f909f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f909f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560261bf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (1837 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005623c35b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623c35afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623c35b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cebb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623c3548bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623c3548a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623c352d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623c31dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623c31dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623c31dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50
FAIL: Clang :: CodeGen/arm-neon-vld.c (1861 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float16x4x3_t, ptr %retval, align 8
# |   ret %struct.float16x4x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float16x4x4_t, ptr %retval, align 8
# |   ret %struct.float16x4x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float32x2x2_t, ptr %retval, align 8
# |   ret %struct.float32x2x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float32x2x3_t, ptr %retval, align 8
# |   ret %struct.float32x2x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float32x2x4_t, ptr %retval, align 8
# |   ret %struct.float32x2x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0)
# |   store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.poly16x4x2_t, ptr %retval, align 8
# |   ret %struct.poly16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16
# | ...
# `---data was truncated (10240/109928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a24f324eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a24f321e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a24f32562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f724e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f724e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f724e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f724e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a24f2babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a24f2baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a24f29f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a24ef4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a24ef4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f724e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f724e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f724e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a24ef4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.
FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (1887 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_72 = alloca <4 x i16>, align 8
# |   %__s0_72 = alloca <4 x i16>, align 8
# |   %__s1_72 = alloca <4 x i16>, align 8
# |   %__s2_72 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_72, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_72, align 8
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_72, align 8
# |   %3 = load <4 x i16>, ptr %__s0_72, align 8
# |   %4 = load <4 x i16>, ptr %__s1_72, align 8
# |   %5 = load <4 x i16>, ptr %__s2_72, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_72, align 8
# |   %11 = load <4 x i16>, ptr %__ret_72, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_62 = alloca <8 x i16>, align 16
# |   %__s0_62 = alloca <8 x i16>, align 16
# |   %__s1_62 = alloca <8 x i16>, align 16
# |   %__s2_62 = alloca <4 x i16>, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_62, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_62, align 16
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_62, align 8
# |   %3 = load <8 x i16>, ptr %__s0_62, align 16
# |   %4 = load <8 x i16>, ptr %__s1_62, align 16
# |   %5 = load <4 x i16>, ptr %__s2_62, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   %mul = mul <8 x i16> %4, %10
# |   %add = add <8 x i16> %3, %mul
# |   store <8 x i16> %add, ptr %__ret_62, align 16
# |   %11 = load <8 x i16>, ptr %__ret_62, align 16
# |   store <8 x i16> %11, ptr %tmp1, align 16
# |   %12 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_70 = alloca <2 x i32>, align 8
# |   %__s0_70 = alloca <2 x i32>, align 8
# |   %__s1_70 = alloca <2 x i32>, align 8
# |   %__s2_70 = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_70, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_70, align 8
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_70, align 8
# |   %3 = load <2 x i32>, ptr %__s0_70, align 8
# |   %4 = load <2 x i32>, ptr %__s1_70, align 8
# |   %5 = load <2 x i32>, ptr %__s2_70, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   %mul = mul <2 x i32> %4, %10
# |   %add = add <2 x i32> %3, %mul
# |   store <2 x i32> %add, ptr %__ret_70, align 8
# |   %11 = load <2 x i32>, ptr %__ret_70, align 8
# |   store <2 x i32> %11, ptr %tmp1, align 8
# |   %12 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_60 = alloca <4 x i32>, align 16
# |   %__s0_60 = alloca <4 x i32>, align 16
# |   %__s1_60 = alloca <4 x i32>, align 16
# |   %__s2_60 = alloca <2 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_60, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1_60, align 16
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_60, align 8
# |   %3 = load <4 x i32>, ptr %__s0_60, align 16
# |   %4 = load <4 x i32>, ptr %__s1_60, align 16
# |   %5 = load <2 x i32>, ptr %__s2_60, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x i32> %lane, ptr %ref.tmp, align 16
# |   %8 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %8, ptr %__ret, align 16
# |   %9 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %9, ptr %tmp, align 16
# |   %10 = load <4 x i32>, ptr %tmp, align 16
# |   %mul = mul <4 x i32> %4, %10
# |   %add = add <4 x i32> %3, %mul
# |   store <4 x i32> %add, ptr %__ret_60, align 16
# |   %11 = load <4 x i32>, ptr %__ret_60, align 16
# |   store <4 x i32> %11, ptr %tmp1, align 16
# |   %12 = load <4 x i32>, ptr %tmp1, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_482 = alloca <4 x i16>, align 8
# |   %__s0_482 = alloca <4 x i16>, align 8
# |   %__s1_482 = alloca <4 x i16>, align 8
# |   %__s2_482 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_482, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_482, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_482, align 16
# |   %3 = load <4 x i16>, ptr %__s0_482, align 8
# |   %4 = load <4 x i16>, ptr %__s1_482, align 8
# |   %5 = load <8 x i16>, ptr %__s2_482, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_482, align 8
# |   %11 = load <4 x i16>, ptr %__ret_482, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_472 = alloca <8 x i16>, align 16
# |   %__s0_472 = alloca <8 x i16>, align 16
# |   %__s1_472 = alloca <8
# | ...
# `---data was truncated (10240/857511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005590b7b54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590b7b51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590b7b5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f97e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f97ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f97e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f97e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590b7aeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590b7aeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590b7acf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590b777ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590b777eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f97e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f97e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f97e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590b777ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (1905 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <4 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <4 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <4 x i16> %vbsl5.i to <4 x half>
# |   store <4 x half> %7, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbsl.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <8 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <8 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <8 x i16> %vbsl5.i to <8 x half>
# |   store <8 x half> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x half> %vzip.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x half> %vzip1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x half> %vzip.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x half> %vzip1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   store <4 x half> %vuzp.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   store <4 x half> %vuzp1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   store <8 x half> %vuzp.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   store <8 x half> %vuzp1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef 
# | ...
# `---data was truncated (10240/31986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e69abaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e69aba7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e69abab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfcf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfcf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfcf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfcf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e69ab40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e69ab40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e69ab258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e69a7d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e69a7d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfcf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfcf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfcf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e69a7d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1940 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2, align 8
# |   %extract = extractelement <1 x double> %5, i32 0
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.fma.f64(double, double, double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <2 x double>, ptr %__s2, align 16
# |   %extract = extractelement <2 x double> %5, i32 1
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret_443 = alloca float, align 4
# |   %__s0_443 = alloca float, align 4
# |   %__s1_443 = alloca float, align 4
# |   %__s2_443 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_443, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1_443, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2_443, align 8
# |   %3 = load float, ptr %__s0_443, align 4
# |   store float %3, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1_443, align 4
# |   %fneg = fneg float %4
# |   store float %fneg, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2_443, align 8
# |   store <2 x float> %5, ptr %__s2, align 8
# |   %6 = load float, ptr %__s0, align 4
# |   %7 = load float, ptr %__s1, align 4
# |   %8 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %8, i32 1
# |   %9 = call float @llvm.fma.f32(float %7, float %extract, float %6)
# |   store float %9, ptr %ref.tmp, align 4
# |   %10 = load float, ptr %ref.tmp, align 4
# |   store float %10, ptr %__ret, align 4
# |   %11 = load float, ptr %__ret, align 4
# |   store float %11, ptr %tmp, align 4
# |   %12 = load float, ptr %tmp, align 4
# |   store float %12, ptr %__ret_443, align 4
# |   %13 = load float, ptr %__ret_443, align 4
# |   store float %13, ptr %tmp1, align 4
# |   %14 = load float, ptr %tmp1, align 4
# |   ret float %14
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.fma.f32(float, float, float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret_449 = alloca <1 x double>, align 8
# |   %__s0_449 = alloca <1 x double>, align 8
# |   %__s1_449 = alloca <1 x double>, align 8
# |   %__s2_449 = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   %tmp3 = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0_449, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_449, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2_449, align 8
# |   %3 = load <1 x double>, ptr %__s0_449, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s1_449, align 8
# |   %fneg = fneg <1 x double> %4
# |   store <1 x double> %fneg, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2_449, align 8
# |   store <1 x double> %5, ptr %__s2, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = load <8 x i8>, ptr %__s1, align 8
# |   %8 = load <8 x i8>, ptr %__s2, align 8
# |   %9 = bitcast <8 x i8> %8 to <1 x double>
# |   %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %7 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %6 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %10, ptr %__ret, align 8
# |   %11 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %11, ptr %tmp, align 8
# |   %12 = load <1 x double>, ptr %tmp, align 8
# |   store <1 x double> %12, ptr %__ret_449, align 8
# |   %13 = load <1 x double>, ptr %__ret_449, align 8
# |   store <1 x double> %13, ptr %tmp3, align 8
# |   %14 = load <1 x double>, ptr %tmp3, align 8
# |   ret <1 x double> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret_460 = alloca <1 x double>, align 8
# |   %__s0_460 = alloca <1 x double>, align 8
# |   %__s1_460 = alloca <1 x double>, align 8
# |   %__s2_460 = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %_
# | ...
# `---data was truncated (10240/12799) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056368087ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563680879e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056368087d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd38449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd38449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd38431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563680812bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563680812a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636807f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636804a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636804a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd38432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd384330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636804a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2111 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.1a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %c.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   %2 = load <8 x i16>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %c.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   %2 = load <4 x i32>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   store <4 x i32> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32>
# |   %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32>
# |   %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i)
# |   %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   %__ret_140 = alloca <4 x i16>, align 8
# |   %__s0_140 = alloca <4 x i16>, align 8
# |   %__s1_140 = alloca <4 x i16>, align 8
# |   %__s2_140 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_140, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_140, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_140, align 8
# |   %3 = load <4 x i16>, ptr %__s0_140, align 8
# |   %4 = load <4 x i16>, ptr %__s1_140, align 8
# |   %5 = load <4 x i16>, ptr %__s2_140, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_140, align 8
# |   %16 = load <4 x i16>, ptr %__ret_140, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr
# | ...
# `---data was truncated (10240/38786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000056494396feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056494396ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056494397062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc499049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc499049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc499031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564943905bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564943905a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649438ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564943599e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564943599b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc499032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4990330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564943599a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (2118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x hal
# | ...
# `---data was truncated (10240/514165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c766c7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c766c7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c766c7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4addb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4addb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4addb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4addb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c766c13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c766c13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c766bf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7668a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7668a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4addb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4addb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4addb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7668a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/AArch64/neon/load.c (2133 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %0, align 2
# |   store <8 x half> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %2, ptr %__ret, align 16
# |   %3 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %3, ptr %tmp, align 16
# |   %4 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %0, align 4
# |   store <4 x float> %1, ptr %ref.tmp, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %2, ptr %__ret, align 16
# |   %3 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %3, ptr %tmp, align 16
# |   %4 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <2 x double>, ptr %0, align 8
# |   store <2 x double> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %2, ptr %__ret, align 16
# |   %3 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %3, ptr %tmp, align 16
# |   %4 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   store <2 x i64> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %2, ptr %__ret, align 16
# |   %3 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %3, ptr %tmp, align 16
# |   %4 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store ptr %a
# | ...
# `---data was truncated (10240/415795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055dce090ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dce0909e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dce090d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8013533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8013533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dce08a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dce08a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dce08878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dce0536e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dce0536b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dce0536a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (2144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x h
# | ...
# `---data was truncated (10240/619135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d35e77beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d35e778e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d35e77c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2c3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2c3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2c3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2c3eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d35e711bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d35e711a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d35e6f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d35e3a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d35e3a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2c3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2c3eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2c3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d35e3a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/AArch64/neon/store.c (2165 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   store <4 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <2 x float>
# |   store <2 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   store <1 x double> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %val.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %val, ptr %val.addr, align 8
# |   %0 = load <8 x i8>, ptr %val.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   store <4 x i16> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store <1 x i64> %val, ptr %val.addr, align 8
# |   %0 = load <1 x i64>, ptr %val.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %ptr.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   store <1 x i64> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   store <8 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   %__s1 = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   store <4 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr
# | ...
# `---data was truncated (10240/446007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000556205bd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556205bcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556205bd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e2f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e2f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e2f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e2f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556205b66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556205b66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556205b4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562057fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562057fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e2f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e2f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e2f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562057faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (2175 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv
# | ...
# `---data was truncated (10240/255166) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b6027eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b6027be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b6027f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f4cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f4cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f4cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f4cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b60214bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b60214a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b601f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b5fea8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b5fea8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f4cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f4cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f4cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b5fea8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (2199 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vf
# | ...
# `---data was truncated (10240/117019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a52efeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a52efe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a52efeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7084133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f708418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7084133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f708411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a52ef80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a52ef80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a52ef658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a52ec14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a52ec14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f708411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f708411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f708411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a52ec14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (2214 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055640b8fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055640b8f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055640b8fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc0e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc0e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055640b891bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055640b891a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055640b8768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055640b525e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055640b525b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc0e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055640b525a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (2216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638ffb95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638ffb92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638ffb9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe006505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe00655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe006505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0064ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638ffb2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638ffb2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638ffb108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638ff7bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638ff7bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0064eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0064ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0064ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638ff7bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (2225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/427567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572a4caaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572a4ca7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572a4cab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa69fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa69fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa69fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa69fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572a4c40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572a4c40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572a4c258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572a48d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572a48d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa69fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa69fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa69fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572a48d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (2239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/200802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646879aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646879a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646879ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdc0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdc0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdc0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdc0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564687942bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564687942a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646879278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646875d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646875d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdc0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdc0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdc0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646875d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (2245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055910f10beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055910f108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055910f10c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d90f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d90f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d90f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d90f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055910f0a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055910f0a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055910f0868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055910ed35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055910ed35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d90f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d90f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d90f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055910ed35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (2256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b12896aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b128967e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b12896b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb92af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb92af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb92af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb92af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b128900bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b128900a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1288e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b128594e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b128594b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb92af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb92af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb92af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b128594a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/arm-neon-endianness.c (2257 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-arm-none-eabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 2
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 3
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 1
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# |  #0 0x0000563f884dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f884d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f884dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51efd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51efd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51efd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51efced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f88471bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f88471a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f884568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f88105e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f88105b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51efceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51efcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51efcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f88105a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (2283 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e83b4e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e83b4e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e83b4e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d50705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d5075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d50705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d506ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e83b47cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e83b47ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e83b4618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e83b110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e83b110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d506eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d506ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d506ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e83b110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/thinlto_backend.ll (2296 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# |  #0 0x000055bad3574eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bad3571e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bad357562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f305be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f305bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f305be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f305be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad350abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bad350aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bad34ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bad319ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bad319eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f305be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f305be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f305be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad319ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (2303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/424041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f88fe1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f88fe19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f88fe1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc744733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc74478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc744733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc74471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f88fdb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f88fdb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f88fd978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f88fa46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f88fa46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc74471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc74471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc74471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f88fa46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (2306 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c01f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560c01ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560c01f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9d6d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9d6d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9d6d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9d6ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c0186bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560c0186a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560c016b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560bfe1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560bfe1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9d6ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9d6cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9d6cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560bfe1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (2311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558db63fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558db63f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558db63fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb43bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb43bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb43bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb43bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558db6391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558db6391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558db63768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558db6025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558db6025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb43bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb43bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb43bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db6025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (2320 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> noundef %a.coerce, <vscale x 8 x half> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x half>, align 16
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca <32 x half>, align 16
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %b.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store <32 x half> %b, ptr %b.addr, align 16
# |   %0 = load <32 x ha
# | ...
# `---data was truncated (10240/161192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055bf3ba70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf3ba6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf3ba7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab6d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab6d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab6d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab6d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf3ba06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf3ba06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf3b9eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf3b69ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf3b69ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab6d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab6d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab6d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf3b69aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (2323 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055581cc86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055581cc83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055581cc8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b65e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b65ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b65e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b65e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055581cc1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055581cc1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055581cc018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055581c8b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055581c8b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b65e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b65e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b65e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055581c8b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (2332 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %value.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576)
# |   %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1
# |   store <2 x i64> %3, ptr %0, align 8
# |   %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = load <4 x i32>, ptr %value.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2)
# |   store <4 x i32> %3, ptr %0, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4
# | 
# | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593e1552eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593e154fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593e155362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8af4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8af40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8af4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8af4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e14e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593e14e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593e14cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593e117ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593e117cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8af4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8af40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8af40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e117ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (2347 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597efeb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597efeb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597efeb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4235a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4235a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4235a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4235a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597efe4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597efe4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597efe328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597efae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597efae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4235a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4235a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4235a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597efae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (2358 of 27910)
******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @_Z9cond_boolu10__SVBool_tS_(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ult <vscale x 16 x i1> %0, %1
# |   %2 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %vector_select = select <vscale x 16 x i1> %cmp, <vscale x 16 x i1> %2, <vscale x 16 x i1> %3
# |   ret <vscale x 16 x i1> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_i8u10__SVInt8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_u8u11__SVUint8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_i16u11__SVInt16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_u16u12__SVUint16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_i32u11__SVInt32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_u32u12__SVUint32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_i64u11__SVInt64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_u64u12__SVUint64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @_Z8cond_f16u13__SVFloat16_tS_(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x half> %2, <vscale x 8 x half> %3
# |   ret <vscale x 8 x half> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @_Z8cond_f32u13__SVFloat32_tS_(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %3 = load <vs
# | ...
# `---data was truncated (10240/16444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564abab13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564abab10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564abab1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30d8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30d8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30d8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30d8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564abaaa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564abaaa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564abaa8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aba73de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aba73db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30d8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30d8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30d8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aba73da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (2365 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i)
# |   %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8>
# |   store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i)
# |   %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i)
# |   %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8>
# |   store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i)
# |   %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i)
# |   %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8>
# |   store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i)
# |   %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i)
# |   %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8>
# |   store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i)
# |   %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i)
# |   %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8>
# |   store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i)
# |   %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i)
# |   %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8>
# |   store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x
# | ...
# `---data was truncated (10240/16447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056307f406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056307f403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307f40762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ee9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ee958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ee9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ee951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307f39cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056307f39ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056307f3818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056307f030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056307f030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ee951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ee951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ee951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056307f030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (2368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i16>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i32>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, <vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void
# | ...
# `---data was truncated (10240/179328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562677d2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562677d2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562677d2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dbc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dbc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dbc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dbc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562677cc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562677cc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562677ca98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562677958e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562677958b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dbc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dbc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dbc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562677958a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (2379 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 
# | ...
# `---data was truncated (10240/73182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d98004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d98001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d9800562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca69649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca69649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca69631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d97f9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d97f9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d97f7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d97c2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d97c2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca69632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca696330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d97c2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (2381 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563198c0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563198c0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563198c0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7974333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f797438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7974333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f797431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563198ba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563198ba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563198b888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563198837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563198837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f797431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f797431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f797431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563198837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (2386 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/424049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f490c6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f490c68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f490c6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2989333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2989333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f490c01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f490c01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f490be68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f490895e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f490895b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f298931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f490895a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (2391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willre
# | ...
# `---data was truncated (10240/273697) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561eb8f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561eb8f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561eb8f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f367c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f367c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f367c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f367c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561eb88abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561eb88aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561eb86f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561eb51ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561eb51eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f367c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f367c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f367c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561eb51ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (2398 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3667c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3667c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3667c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56bd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f36675ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f36675ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3667438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3663f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3663f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3663f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (2401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x
# | ...
# `---data was truncated (10240/514173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056164259feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056164259ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616425a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd889e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd889e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd889e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd889e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561642535bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561642535a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056164251a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616421c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616421c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd889e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd889e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd889e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616421c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (2408 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon         -target-feature +v8.3a         -target-feature +fullfp16         -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i)
# |   %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8>
# |   store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %acc.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float>
# |   %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float>
# |   %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i)
# |   %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8>
# |   store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %lhs.addr = alloca <8 x half>, align 16
# |   %rhs.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %lhs, ptr %lhs.addr, align 16
# |   store <8 x half> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %lhs.addr, align 16
# |   %2 = load <8 x half>, ptr %rhs.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i)
# |   %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %lhs.addr = alloca <4 x float>, align 16
# |   %rhs.addr = alloca <4 x float>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <4 x float> %lhs, ptr %lhs.addr, align 16
# |   store <4 x float> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <4 x float>, ptr %lhs.addr, align 16
# |   %2 = load <4 x float>, ptr %rhs.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float>
# |   %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float>
# |   %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i)
# |   %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <2 x double>, align 16
# |   %lhs.addr = alloca <2 x double>, align 16
# |   %rhs.addr = alloca <2 x double>, align 16
# |   store <2 x double> %acc, ptr %acc.addr, align 16
# |   store <2 x double> %lhs, ptr %lhs.addr, align 16
# |   store <2 x double> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <2 x double>, ptr %acc.addr, align 16
# |   %1 = load <2 x double>, ptr %lhs.addr, align 16
# |   %2 = load <2 x double>, ptr %rhs.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double>
# |   %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double>
# |   %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double>
# |   %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i)
# |   %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16
# |   %6 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %6, ptr %__ret.i, align 16
# |   %7 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v
# | ...
# `---data was truncated (10240/166298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# |  #0 0x000055b1ac40aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1ac407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1ac40b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1ac3a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1ac3a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1ac3858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1ac034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1ac034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95c2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1ac034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2410 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr
# | ...
# `---data was truncated (10240/44315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e8a82a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8a82a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8a82a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f144fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f144fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f144fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f144fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8a823dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8a823da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8a82228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8a7ed1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8a7ed1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f144fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f144fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f144fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8a7ed1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (2412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579635e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579635dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579635e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd763649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7636a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd763649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd763631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557963576bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557963576a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055796355b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055796320ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055796320ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd763632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7636330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7636330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055796320aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (2414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb46ed5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb46ed2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb46ed662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b1de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b1dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b1de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b1de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb46e6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb46e6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb46e508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb46affe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb46affb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b1de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b1de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b1de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb46affa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (2420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579d7d6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579d7d6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579d7d7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12a051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579d7d05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579d7d05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579d7cea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579d7999e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579d7999b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12a051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579d7999a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (2422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056507f58eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056507f58be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056507f58f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b9a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b9a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b9a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b9a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056507f524bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056507f524a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056507f5098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056507f1b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056507f1b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b9a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b9a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b9a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056507f1b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (2431 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 8 x half> %0, %1
# |   ret <vscale x 8 x half> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @add_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 4 x float> %0, %1
# |   ret <vscale x 4 x float> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @add_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 2 x double> %0, %1
# |   ret <vscale x 2 x double> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %add = add <vscale x 4 x i32> %1, %0
# |   store <vscale x 4 x i32> %add, ptr %a.addr, align 16
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_inplace_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %add = add <vscale x 2 x i64> %1, %0
# |   store <vscale x 2 x i64> %add, ptr %a.addr, align 16
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <
# | ...
# `---data was truncated (10240/107144) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005556d2f1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556d2f1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556d2f1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd706449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd706449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd706431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556d2eb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556d2eb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556d2e988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556d2b47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556d2b47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd706432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556d2b47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (2433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b571e3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b571e3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b571e3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f236d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f236d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f236d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f236d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b571dd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b571dd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b571db88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b571a67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b571a67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f236d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f236d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f236d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b571a67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (2451 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604bdedfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604bdedce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604bdee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe401705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe40175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe401705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4016ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604bde75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604bde75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604bde5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604bdb09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604bdb09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4016eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4016ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4016ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604bdb09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (2452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558699c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558699bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558699c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e51933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e5198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e51933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e5191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555869957bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555869957a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055586993c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558695ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558695ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e5191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e5191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e5191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558695eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (2453 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, al
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e9bf2fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9bf2f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9bf2fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c5af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9bf291bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9bf291a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9bf2768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9bef25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9bef25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9bef25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (2484 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d546081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d54607ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d54608262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e6e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e6e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e6e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e6e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d546017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d546017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d545ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d545cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d545cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e6e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e6e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e6e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d545caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (2491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596d31feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d31fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d31ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f729f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f729f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f729f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f729f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d3194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d3194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d31798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d2e28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d2e28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f729f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f729f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f729f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d2e28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (2494 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/79071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bb1f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bb1f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bb1f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe11e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe11e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe11e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe11e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bb1f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bb1f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bb1efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bb1bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bb1bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe11e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe11e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe11e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bb1baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (2505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b785cdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b785cdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b785ce062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faabce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faabcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faabce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faabce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b785c75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b785c75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b785c5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b785909e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b785909b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faabce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faabce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faabce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b785909a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (2506 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = and <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = and <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = and <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = and <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr
# | ...
# `---data was truncated (10240/11060) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ccfa88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ccfa85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ccfa8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5421b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5421b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5421b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5421b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ccfa1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ccfa1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ccfa038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ccf6b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ccf6b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5421b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5421b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5421b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ccf6b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (2508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   s
# | ...
# `---data was truncated (10240/280209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646753a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646753a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646753a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8927705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f892775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8927705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89276ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056467533abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056467533aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056467531f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564674fcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564674fceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89276eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89276ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89276ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564674fcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (2511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bf2742eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bf273fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bf274362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd35a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd35a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd35a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd35a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bf26d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bf26d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bf26bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bf236ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bf236cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd35a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd35a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd35a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bf236ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (2512 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <16 x i8> %2, %3
# |   store <16 x i8> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <8 x i16> %2, %3
# |   store <8 x i16> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <4 x i32> %2, %3
# |   store <4 x i32> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   store <1 x i64> %v2, ptr %v2.addr, align 8
# |   %0 = load <1 x i64>, ptr %v1.addr, align 8
# |   %1 = load <1 x i64>, ptr %v2.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <1 x i64> %2, %3
# |   store <1 x i64> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v1.addr = alloca <2 x i64>, align 16
# |   %v2.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %v1, ptr %v1.addr, align 16
# |   store <2 x i64> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x i64>, ptr %v1.addr, align 16
# |   %1 = load <2 x i64>, ptr %v2.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <2 x i64> %2, %3
# |   store <2 x i64> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/170019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005580f4e6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580f4e69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580f4e6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5c1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5c1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5c1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5c1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580f4e02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580f4e02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580f4de78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580f4a96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580f4a96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5c1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5c1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5c1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580f4a96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (2515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056382c4a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056382c49fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056382c4a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6800533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6800533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056382c438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056382c438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056382c41d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056382c0cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056382c0ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f680051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056382c0cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/aapcs-bitfield.c (2517 of 27910)
******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-eabi"
# | 
# | %struct.st6 = type { i16, i8, i8 }
# | %struct.st7b = type { i8, [3 x i8], %struct.st7a }
# | %struct.st7a = type { i8, i8, [2 x i8] }
# | %struct.st11 = type <{ i8, i16, i8 }>
# | %struct.st13 = type <{ i8, i32 }>
# | %struct.st16 = type { i32, i16, i32, i16 }
# | %struct.st17 = type <{ i32, i8 }>
# | %struct.zero_bitfield = type { i8, i8, [2 x i8] }
# | %struct.zero_bitfield_ok = type { i16, i32 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st0_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st0_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st1_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.ashr = ashr i16 %bf.load, 10
# |   %conv = sext i16 %bf.ashr to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st1_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, 1023
# |   %bf.set = or i16 %bf.clear, 1024
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st2_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 9
# |   %bf.ashr = ashr i32 %bf.shl, 25
# |   %bf.cast = trunc i32 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st2_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -8323073
# |   %bf.set = or i32 %bf.clear, 65536
# |   store i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st3_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st3_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store volatile i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st4_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 2
# |   %bf.ashr = ashr i16 %bf.shl, 11
# |   %bf.cast = trunc i16 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -15873
# |   %bf.set = or i16 %bf.clear, 512
# |   store volatile i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -512
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st5_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 11
# |   %bf.ashr = ashr i32 %bf.shl, 27
# |   %bf.cast = trunc i32 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st5_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -2031617
# |   %bf.set = or i32 %bf.clear, 65536
# |   store volatile i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st6_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %x = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 4
# |   %bf.ashr = ashr i16 %bf.shl, 4
# |   %bf.cast = sext i16 %bf.ashr to i32
# |   store i32 %bf.cast, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   %2 = load volatile i8, ptr %b, align 2
# |   %conv = sext i8 %2 to i32
# |   %3 = load i32, ptr %x, align 4
# |   %add = add nsw i32 %3, %conv
# |   store i32 %add, ptr %x, align 4
# |   %4 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2
# |   %bf.load1 = load volatile i8, ptr %c, align 1
# |   %bf.shl2 = shl i8 %bf.load1, 3
# |   %bf.ashr3 = ashr i8 %bf.shl2, 3
# |   %bf.cast4 = sext i8 %bf.ashr3 to i32
# |   %5 = load i32, ptr %x, align 4
# |   %add5 = add nsw i32 %5, %bf.cast4
# |   store i32 %add5, ptr %x, align 4
# |   %6 = load i32, ptr %x, align 4
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st6_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -4096
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   store i8 2, ptr %b, align 2
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2
# |   %bf.load1 = load i8, ptr %c, align 1
# |   %bf.clear2 = and i8 %bf.load1, -32
# |   %bf.set3 = or i8 %bf.clear2, 3
# |   store i8 %bf.set3, ptr %c, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st7_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %r = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   %1 = load i8, ptr %x, align 4
# |   %conv = sext i8 %1 to i32
# |   store i32 %conv, ptr %r, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   %3 = load volatile i8, ptr %a, align 4
# |   %conv1 = sext i8 %3 to i32
# |   %4 = load i32, ptr %r, align 4
# |   %add = add nsw i32 %4, %conv1
# |   store i32 %add, ptr %r, align 4
# |   %5 = load ptr, ptr %m.addr, align 4
# |   %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.shl = shl i8 %bf.load, 3
# |   %bf.ashr = ashr i8 %bf.shl, 3
# |   %bf.cast = sext i8 %bf.ashr to i32
# |   %6 = load i32, ptr %r, align 4
# |   %add3 = add nsw i32 %6, %bf.cast
# |   store i32 %add3, ptr %r, align 4
# |   %7 = load i32, ptr %r, align 4
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st7_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   store i8 1, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   store volatile i8 2, ptr %a, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.clear = and i8 %bf.load, -32
# |   %bf.set = or i8 %bf.clear, 3
# |   store volatile i8 %bf.set, ptr %b, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   store i16 -1, ptr %0, align 4
# |   ret i32 65535
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @read_st9(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 4
# |   %bf.cast = sext i8 %bf.load to i32
# |   r
# | ...
# `---data was truncated (10240/24998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b995cb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b995cafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b995cb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe9d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe9d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe9d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b995c48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b995c48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b995c2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9958dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9958dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe9d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe9d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe9d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9958dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (2523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale
# | ...
# `---data was truncated (10240/410383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056329e2a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056329e2a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056329e2aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f718041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71804725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f718041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7180403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056329e23fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056329e23fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056329e2248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056329ded3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056329ded3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7180404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71804050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71804050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056329ded3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (2527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f79ab0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f79ab0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f79ab1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f499821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49982725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f499821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4998203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f79aaa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f79aaa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f79aa8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f79a739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f79a739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4998204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49982050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49982050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f79a739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm_acle.c (2529 of 27910)
******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dmb() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dsb() #0 {
# | entry:
# |   call void @llvm.arm.dsb(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_isb() #0 {
# | entry:
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pld() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pldx() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pli() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_plix() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 32
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %4, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i32, ptr %__x.addr.i, align 4
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %shr.i = lshr i32 %5, %6
# |   %7 = load i32, ptr %__x.addr.i, align 4
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 32, %8
# |   %shl.i = shl i32 %7, %sub.i
# |   %or.i = or i32 %shr.i, %shl.i
# |   store i32 %or.i, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | __ror.exit:                                       ; preds = %if.then.i, %if.end.i
# |   %9 = load i32, ptr %retval.i, align 4
# |   ret i32 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i.i = alloca i32, align 4
# |   %__x.addr.i.i = alloca i32, align 4
# |   %__y.addr.i.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   store i32 %2, ptr %__x.addr.i.i, align 4
# |   store i32 %3, ptr %__y.addr.i.i, align 4
# |   %4 = load i32, ptr %__y.addr.i.i, align 4
# |   %rem.i.i = urem i32 %4, 32
# |   store i32 %rem.i.i, ptr %__y.addr.i.i, align 4
# |   %5 = load i32, ptr %__y.addr.i.i, align 4
# |   %cmp.i.i = icmp eq i32 %5, 0
# |   br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i
# | 
# | if.then.i.i:                                      ; preds = %entry
# |   %6 = load i32, ptr %__x.addr.i.i, align 4
# |   store i32 %6, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | if.end.i.i:                                       ; preds = %entry
# |   %7 = load i32, ptr %__x.addr.i.i, align 4
# |   %8 = load i32, ptr %__y.addr.i.i, align 4
# |   %shr.i.i = lshr i32 %7, %8
# |   %9 = load i32, ptr %__x.addr.i.i, align 4
# |   %10 = load i32, ptr %__y.addr.i.i, align 4
# |   %sub.i.i = sub i32 32, %10
# |   %shl.i.i = shl i32 %9, %sub.i.i
# |   %or.i.i = or i32 %shr.i.i, %shl.i.i
# |   store i32 %or.i.i, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | __rorl.exit:                                      ; preds = %if.then.i.i, %if.end.i.i
# |   %11 = load i32, ptr %retval.i.i, align 4
# |   ret i32 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i64, align 8
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i64, align 8
# |   %y.addr = alloca i32, align 4
# |   store i64 %x, ptr %x.addr, align 8
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i64, ptr %x.addr, align 8
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 64
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i64, ptr %__x.addr.i, align 8
# |   store i64 %4, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i64, ptr %__x.addr.i, align 8
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %sh_prom.i = zext i32 %6 to i64
# |   %shr.i = lshr i64 %5, %sh_prom.i
# |   %7 = load i64, ptr %__x.addr.i, align 8
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 64, %8
# |   %sh_prom1.i = zext i32 %sub.i to i64
# |   %shl.i = shl i64 %7, %sh_prom1.i
# |   %or.i = or i64 %shr.i, %shl.i
# |   store i64 %or.i, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | __rorll.exit:                                     ; preds = %if.then.i, %if.end.i
# |   %9 = load i64, ptr %retval.i, align 8
# |   ret i64 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clz(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzl(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzll(i64 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i64, align 8
# |   %t.addr = alloca i64, align 8
# |   store i64 %t, ptr %t.addr, align 8
# |   %0 = load i64, ptr %t.addr, align 8
# |   store i64 %0, ptr %__t.addr.i, align 8
# |   %1 = load i64, ptr %__t.addr.i, align 8
# |   %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
# |   %3 = trunc i64 %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %cls.i = call i32 @llvm.arm.cls(i32 %1)
# |   ret i32 %cls.i
# | }
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/86891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c214c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c214c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c214c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f32e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f32ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f32e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f32e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c2145bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c2145ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c214408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c210efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c210efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f32e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f32e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f32e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c210efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (2532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df03b29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df03b26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df03b2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9624d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9624d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9624d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9624d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df03abfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df03abfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df03aa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df03753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df03753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9624d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9624d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9624d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df03753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (2533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dcce58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dcce55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dcce5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9a1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9a195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9a1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9a18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dccdeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dccdeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dccdd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dcca82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dcca82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9a18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9a18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9a18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dcca82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2535 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -252)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 -243)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 195)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 8978432)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 27391)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 -5570561)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 -18689)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 1023410175)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -11265)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -13893633)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -37)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -1644167169)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 13568)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 654311424)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 175)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 89)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056310ceabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056310cea8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056310ceac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ac7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ac798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ac7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ac791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056310ce41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056310ce41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056310ce268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056310cad5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056310cad5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ac791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ac791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ac791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056310cad5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (2536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a52cf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a52cf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a52cf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1ef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1ef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1ef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1ef031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a52c8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a52c8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a52c718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a52920e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a52920b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1ef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1ef0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1ef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a52920a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (2541 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 5)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 5)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 18)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 3)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 11)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 7)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 4)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 19)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 7)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 15)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 31)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = lshr <16 x i8> %0, splat (i8 1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = lshr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = lshr <4 x i32> %0, splat (i32 10)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   ret <16 x i8> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   ret <4 x i32> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinlin
# | ...
# `---data was truncated (10240/66359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600c54aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600c54abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600c54af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1aa7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1aa7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1aa7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1aa7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600c5444bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600c5444a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600c54298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600c50d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600c50d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1aa7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1aa7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1aa7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600c50d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (2543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1ad652eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1ad64fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1ad65362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7afc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7afc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7afc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7afc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1ad5e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1ad5e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1ad5cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1ad27ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1ad27cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7afc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7afc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7afc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1ad27ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (2551 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633b06beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633b06bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633b06bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4b7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4b778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4b7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4b771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633b0654bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633b0654a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633b06398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633b02e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633b02e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4b771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4b771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4b771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633b02e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (2552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c408ab3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c408ab0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c408ab462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8c9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8c9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8c9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8c9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c408a49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c408a49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c408a2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4086dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4086ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8c9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8c9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8c9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4086dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (2553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbf3253eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbf3250e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbf325462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faae6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faae62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faae6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faae6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbf31e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbf31e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbf31ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbf2e7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbf2e7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faae6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faae62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faae62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbf2e7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (2574 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c178678eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c178675e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c17867962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c17860ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c17860ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1785f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1782a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1782a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efff0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1782a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (2575 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x half>, ptr %0, align 2
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x float>, ptr %0, align 4
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i8>, ptr %0, align 1
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i8>, ptr %0, align 1
# |   %2 = sext <4 x i8> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = a
# | ...
# `---data was truncated (10240/50873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0c8276eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0c8273e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0c827762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9805533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9805533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0c820cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0c820ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0c81f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0c7ea0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0c7ea0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f980551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0c7ea0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (2579 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0)
# |   %2 = extractvalue { <8 x half>, <8 x half> } %1, 0
# |   %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0
# |   %4 = extractvalue { <8 x half>, <8 x half> } %1, 1
# |   %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1
# |   ret %struct.float16x8x2_t %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0)
# |   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
# |   %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0
# |   %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
# |   %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1
# |   %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
# |   %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2
# |   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
# |   %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3
# |   ret %struct.uint8x16x4_t %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.uint32x4x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.uint32x4x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0
# |   store [2 x <4 x i32>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0
# |   %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.int8x16x4_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.int8x16x4_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0
# |   store [4 x <16 x i8>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false)
# |   %3 = load %struct.int8x16x4_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.int8x16x4_t %3, 0, 0
# |   %5 = extractvalue %struct.int8x16x4_t %3, 0, 1
# |   %6 = extractvalue %struct.int8x16x4_t %3, 0, 2
# |   %7 = extractvalue %struct.int8x16x4_t %3, 0, 3
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.float16x8x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.float16x8x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0
# |   store [2 x <8 x half>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.float16x8x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.float16x8x2_t %3, 0, 0
# |   %5 = extractvalue %struct.float16x8x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %values.addr = alloca ptr, align 4
# |   %v = alloca %struct.uint16x8x2_t, align 8
# |   %tmp = alloca %struct.uint16x8x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %values, ptr %values.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0)
# |   %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
# |   %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0
# |   %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
# |   %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1
# |   store %struct.uint16x8x2_t %5, ptr %tmp, align 8
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false)
# |   %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0
# |   %6 = load <8 x i16>, ptr %arrayidx, align 8
# |   %7 = load ptr, ptr %values.addr, align 4
# |   %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0
# |   store <8 x i16> %6, ptr %arrayidx1, align 8
# |   %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1
# |   %8 = load <8 x i16>, ptr %arrayidx3, align 8
# |   %9 = load ptr, ptr %values.addr, align 4
# |   %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1
# |   store <8 x i16> %8, ptr %arrayidx4, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %ref.tmp = alloca %struct.int32x4x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0)
# |   %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
# |   %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
# |   %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1
# |   store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8
# |   %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0
# |   %6 = load <4 x i32>, ptr %arrayidx, align 8
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000563672d9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563672d97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563672d9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6df9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6df938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6df9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6df931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563672d30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563672d30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563672d158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636729c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636729c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6df931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6df931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6df931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636729c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (2580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055988e2cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055988e2c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055988e2cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6611a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6611a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6611a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6611a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055988e262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055988e262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055988e2478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055988def6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055988def6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6611a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6611a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6611a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055988def6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (2583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563daec21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563daec1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563daec2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75a111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563daebb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563daebb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563daeb9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dae84be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dae84bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75a111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dae84ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2584 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(
# | ...
# `---data was truncated (10240/32505) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a85d71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a85d6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a85d7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9cc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9cc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9cc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9cc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a85d07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a85d07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a85cec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a8599be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a8599bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9cc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9cc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9cc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a8599ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (2589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3acf7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3acf7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3acf8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3356333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3356333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3acf15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3acf15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3acefa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3acba9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3acba9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f335631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3acba9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2592 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %
# | ...
# `---data was truncated (10240/20326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593b9fb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593b9fafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593b9fb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3dbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3dbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3dbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3dbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593b9f48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593b9f48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593b9f2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593b9bdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593b9bdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3dbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3dbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3dbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593b9bdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (2595 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 
# | ...
# `---data was truncated (10240/11881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cedcc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cedcc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cedcc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0792b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0792b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0792b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0792b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cedc59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cedc59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cedc3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ced8ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ced8edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0792b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0792b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0792b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ced8eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (2597 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ebe0f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ebe0f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ebe0f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07e4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07e4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07e4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07e4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ebe08cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ebe08ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ebe0718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ebdd20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ebdd20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07e4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07e4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07e4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ebdd20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (2598 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = and <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = and <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = and <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = and <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613f7e9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613f7e9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613f7ea062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5d6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5d6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5d6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5d6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f7e35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613f7e35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613f7e1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613f7ac9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613f7ac9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5d6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5d6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5d6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f7ac9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (2601 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %
# | ...
# `---data was truncated (10240/15051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055658d25beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055658d258e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055658d25c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f818e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f818e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f818e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f818e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055658d1f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055658d1f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055658d1d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055658ce85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055658ce85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f818e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f818e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f818e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055658ce85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (2603 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp ule <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp sle <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp ule <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564a96cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564a96c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564a96cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6777c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6777ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6777c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6777c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564a9662bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564a9662a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564a96478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564a92f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564a92f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6777c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6777c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6777c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564a92f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (2605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563398b8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563398b88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563398b8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf12e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf12ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf12e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf12e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563398b21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563398b21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563398b068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633987b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633987b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf12e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf12e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf12e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633987b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (2606 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |  
# | ...
# `---data was truncated (10240/15969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f510d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f510d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f510d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd40d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd40d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd40d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd40d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f5106bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f5106ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f510508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f50cffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f50cffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd40d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd40d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd40d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f50cffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (2608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b3ee12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b3ee0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b3ee1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc33b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc33b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc33b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc33b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b3eda8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b3eda8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b3ed8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b3ea3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b3ea3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc33b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc33b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc33b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b3ea3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (2610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4c176eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4c176be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4c176f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f226501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22650725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f226501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2265003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4c1704bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4c1704a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4c16e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4c1398e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4c1398b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2265004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22650050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22650050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4c1398a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (2611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5980e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5980e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5980ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ff4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ff48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ff4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ff4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e59807fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e59807fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5980648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e597d13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e597d13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ff4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ff48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ff48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e597d13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (2615 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> 
# | ...
# `---data was truncated (10240/16951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bca093eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bca090e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bca09462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb917449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb917449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb917431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bca029bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bca029a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bca00e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bc9cbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bc9cbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb917432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bc9cbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2616 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p2.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %retval = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %c = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   %coerce4 = alloca <4 x half>, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b1 = load <4 x half>, ptr %b, align 8
# |   store <2 x i32> %c.coerce, ptr %c, align 8
# |   %c2 = load <4 x half>, ptr %c, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b1, ptr %b.addr, align 8
# |   store <4 x half> %c2, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %1, ptr %coerce, align 8
# |   %3 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %2, ptr %coerce3, align 8
# |   %4 = load <2 x i32>, ptr %coerce3, align 8
# |   store <2 x i32> %3, ptr %__p1.i, align 8
# |   %__p11.i = load <4 x half>, ptr %__p1.i, align 8
# |   store <2 x i32> %4, ptr %__p2.i, align 8
# |   %__p22.i = load <4 x half>, ptr %__p2.i, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8
# |   store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %7 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %9, ptr %retval.i, align 8
# |   %10 = load <2 x i32>, ptr %retval.i, align 8
# |   store <2 x i32> %10, ptr %coerce4, align 8
# |   %11 = load <4 x half>, ptr %coerce4, align 8
# |   store <4 x half> %11, ptr %retval, align 8
# |   %12 = load <2 x i32>, ptr %retval, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p2.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %retval = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %c = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   %coerce4 = alloca <8 x half>, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b1 = load <8 x half>, ptr %b, align 16
# |   store <4 x i32> %c.coerce, ptr %c, align 16
# |   %c2 = load <8 x half>, ptr %c, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b1, ptr %b.addr, align 16
# |   store <8 x half> %c2, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %1, ptr %coerce, align 16
# |   %3 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %2, ptr %coerce3, align 16
# |   %4 = load <4 x i32>, ptr %coerce3, align 16
# |   store <4 x i32> %3, ptr %__p1.i, align 16
# |   %__p11.i = load <8 x half>, ptr %__p1.i, align 16
# |   store <4 x i32> %4, ptr %__p2.i, align 16
# |   %__p22.i = load <8 x half>, ptr %__p2.i, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16
# |   store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %7 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7)
# |   store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %9, ptr %retval.i, align 16
# |   %10 = load <4 x i32>, ptr %retval.i, align 16
# |   store <4 x i32> %10, ptr %coerce4, align 16
# |   %11 = load <8 x half>, ptr %coerce4, align 16
# |   store <8 x half> %11, ptr %retval, align 16
# |   %12 = load <4 x i32>, ptr %retval, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %a = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   store <2 x i32> %a.coerce, ptr %a, align 8
# |   %a1 = load <4 x half>, ptr %a, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b2 = load <4 x half>, ptr %b, align 8
# |   store <4 x half> %a1, ptr %a.addr, align 8
# |   store <4 x half> %b2, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %coerce, align 8
# |   %2 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %1, ptr %coerce3, align 8
# |   %3 = load <2 x i32>, ptr %coerce3, align 8
# |   call void @llvm.experimental.noalias.scope.decl(metadata !3)
# |   store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3
# |   %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3
# |   store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3
# |   %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3
# |   store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3
# |   store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3
# |   %6 = bitcast <8 x i8> %4 to <4 x i16>
# |   %7 = bitcast <8 x i8> %5 to <4 x i16>
# |   %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3
# |   %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %a = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   store <4 x i32> %a.coerce, ptr %a, align 16
# |   %a1 = load <8 x half>, ptr %a, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b2 = load <8 x half>, ptr %b, align 16
# |   store <8 x half> %a1, ptr %a.addr, align 16
# |   store <8 x half> %b2, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %coerce, align 16
# |   %2 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %1, ptr %coerce3, align 16
# |   %3 = load <4 x i32>, ptr %coerce3, align 16
# |   call void @llvm.experimental.noalias.scope.decl(metadata !6)
# |   store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6
# |   %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6
# |   store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6
# |   %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6
# |   store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6
# |   store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6
# |   %6 = bitcast <16 x i8> %4 to <8 x i16>
# |   %7 = bitcast <16 x i8> %5 to <8 x i16>
# |   %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6
# |   %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef
# | ...
# `---data was truncated (10240/35874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055ad1be39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad1be36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad1be3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3ef21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3ef2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3ef21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3ef203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad1bdcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad1bdcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad1bdb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad1ba63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad1ba63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3ef204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3ef2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3ef2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad1ba63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (2618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562046baceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562046ba9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562046bad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f7bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f7bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f7bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f7bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562046b42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562046b42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562046b278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620467d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620467d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f7bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f7bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f7bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620467d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (2621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c77509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c77506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c7750a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedbf41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedbf4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedbf41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedbf403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c7749fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c7749fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c774848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c77133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c77133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedbf404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedbf4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedbf4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c77133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (2623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f2d247eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f2d244e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f2d24862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa004533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa00458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa004533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa00451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f2d1ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f2d1dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f2d1c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f2ce71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f2ce71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa00451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa00451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa00451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f2ce71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (2624 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3)
# |   %5 = and <8 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3)
# |   %5 = and <4 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3)
# |   %5 = and <2 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3)
# |   %5 = and <16 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = xor i16 %0, -1
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = load <8 x half>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = load <4 x float>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <2 x i64>, ptr %a.addr, align 8
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   %5 = load <2 x i64>, ptr %b.addr, align 8
# |   %6 = bitcast <2 x i64> %5 to <4 x i32>
# |   %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6
# |   %8 = bitcast <4 x i32> %7 to <2 x i64>
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, ali
# | ...
# `---data was truncated (10240/13928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x00005555e4307eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555e4304e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555e430862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca4f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca4f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca4f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca4f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555e429dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555e429da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555e42828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555e3f31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555e3f31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca4f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca4f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca4f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555e3f31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/neon/perm.c (2629 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, 
# | ...
# `---data was truncated (10240/231562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055c5403edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5403eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5403ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcc3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcc358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcc3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcc351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c540383bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c540383a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5403688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c540017e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c540017b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcc351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcc351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcc351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c540017a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (2630 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %cmp = icmp eq <8 x i8> %2, %3
# |   %sext = sext <8 x i1> %cmp to <8 x i8>
# |   store <8 x i8> %sext, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i32>
# |   store <16 x i32> %sext, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <8 x i64> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i64>
# |   store <8 x i64> %sext, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x 
# | ...
# `---data was truncated (10240/78785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055db66ca3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db66ca0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db66ca462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff220b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff220b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff220b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff220b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db66c39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db66c39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db66c1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db668cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db668cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff220b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff220b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff220b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db668cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/neon-misc.c (2631 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = icmp sge <8 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %2 to <8 x i8>
# |   store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %3 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %3, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %3 = icmp sge <4 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %3 = icmp sge <2 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x i64>
# |   %3 = icmp sge <1 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = icmp sge <16 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <16 x i1> %2 to <16 x i8>
# |   store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %3 = load <16 x i8>, ptr %ref.tmp.i, align 16
# |   store <16 x i8> %3, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x i16>
# |   %3 = icmp sge <8 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x i32>
# |   %3 = icmp sge <4 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x i64>
# |   %3 = icmp sge <2 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x float>
# |   %3 = fcmp oge <2 x float> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x double>
# |   %3 = fcmp oge <1 x double> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fcmp oge <4 x float> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %3 = fcmp oge <2 x double> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, ali
# | ...
# `---data was truncated (10240/217310) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000559ceb306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ceb303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ceb30762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca55d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca55d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca55d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca55d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ceb29cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ceb29ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ceb2818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ceaf30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ceaf30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca55d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca55d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca55d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ceaf30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (2632 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0)
# |   r
# | ...
# `---data was truncated (10240/43005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055574e9f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055574e9f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055574e9f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b25d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b25d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b25d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b25d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055574e989bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055574e989a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055574e96e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055574e61de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055574e61db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b25d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b25d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b25d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055574e61da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (2633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/427575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab782edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab782eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab782ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab78283bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab78283a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab782688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab77f17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab77f17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab77f17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (2636 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b29abfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b29abce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b29ac062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39e5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39e578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39e5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39e571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b29a55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b29a55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b29a3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b296e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b296e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39e571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39e571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39e571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b296e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (2639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee47f9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee47f98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee47f9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faabfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faabfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faabfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faabfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee47f31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee47f31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee47f168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee47bc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee47bc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faabfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faabfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faabfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee47bc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (2645 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3)
# |   store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3)
# |   store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x2_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x2_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [2 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4)
# |   store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x2_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x2_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [2 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4)
# |   store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x3_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x3_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [3 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <8 x i8>, ptr %arrayidx4.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5)
# |   store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x3_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x3_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [3 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <16 x i8>, ptr %arrayidx4.i, align 16
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5)
# |   store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x4_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x4_t, align 8
# |   %b.a
# | ...
# `---data was truncated (10240/125901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055738a96beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055738a968e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055738a96c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f09b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f09b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f09b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f09b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055738a901bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055738a901a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055738a8e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055738a595e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055738a595b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f09b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f09b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f09b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055738a595a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (2651 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %and = and <8 x i8> %2, %3
# |   store <8 x i8> %and, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %and = and <8 x i64> %0, %1
# |   store <8 x i64> %and, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x
# | ...
# `---data was truncated (10240/35910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055ceb104deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ceb104ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ceb104e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b2c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b2c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b2c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b2c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceb0fe3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ceb0fe3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ceb0fc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ceb0c77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ceb0c77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b2c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b2c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b2c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ceb0c77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (2658 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi    -target-feature +neon -target-feature +bf16 -mfloat-abi soft    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_812 = alloca <4 x float>, align 8
# |   %__s0_812 = alloca <4 x float>, align 8
# |   %__s1_812 = alloca <8 x bfloat>, align 8
# |   %__s2_812 = alloca <8 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x float>, align 8
# |   %__ret = alloca <4 x float>, align 8
# |   %__s0 = alloca <4 x float>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x float>, align 8
# |   %tmp2 = alloca <4 x float>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   store <4 x float> %0, ptr %__s0_812, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   store <8 x bfloat> %1, ptr %__s1_812, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <8 x bfloat> %2, ptr %__s2_812, align 8
# |   %3 = load <4 x float>, ptr %__s0_812, align 8
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 8
# |   %5 = load <4 x float>, ptr %__s2_812, align 8
# |   store <4 x float> %5, ptr %__s0, align 8
# |   %6 = load <16 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 8
# |   store <4 x float> %8, ptr %__ret, align 8
# |   %9 = load <4 x float>, ptr %__ret, align 8
# |   store <4 x float> %9, ptr %tmp, align 8
# |   %10 = load <4 x float>, ptr %tmp, align 8
# |   store <4 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %16, ptr %__ret_812, align 8
# |   %17 = load <4 x float>, ptr %__ret_812, align 8
# |   store <4 x float> %17, ptr %tmp2, align 8
# |   %18 = load <4 x float>, ptr %tmp2, align 8
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_814 = alloca <2 x float>, al
# | ...
# `---data was truncated (10240/54174) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055cf953a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf953a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf953a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31df533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31df58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31df533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31df51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf9533ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf9533ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf953238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf94fd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf94fd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31df51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31df51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31df51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf94fd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (2660 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align
# | ...
# `---data was truncated (10240/39627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bac3dceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bac3dcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bac3dcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7b5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7b518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7b5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7b511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bac3d64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bac3d64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bac3d498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bac39f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bac39f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7b511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7b511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7b511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bac39f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (2661 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, 
# | ...
# `---data was truncated (10240/288103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1a251feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1a251ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1a252062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dd0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dd0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dd0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dd0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1a24b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1a24b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1a249a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1a2149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1a2149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dd0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dd0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dd0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1a2149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (2662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load
# | ...
# `---data was truncated (10240/410391) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a6cebaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a6ceb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a6cebb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55fd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a6ce50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a6ce50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a6ce358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a6cae4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a6cae4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a6cae4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (2677 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   ret <8 x half> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   ret <4 x float> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca half, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %3, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %3, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2,
# | ...
# `---data was truncated (10240/17297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055def38aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055def38a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055def38ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a12133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a1218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a12133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a1211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055def3842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055def3842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055def38278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055def34d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055def34d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a1211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a1211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a1211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055def34d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (2688 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504b7e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056504b7dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056504b7e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf88249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf882a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf88249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf88231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504b778bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056504b778a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056504b75d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056504b40ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056504b40cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf88232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf882330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf882330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504b40ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2689 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffe7300eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffe72fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffe730162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e88733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e8878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e88733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e8871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffe7296bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffe7296a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffe727b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffe6f2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffe6f2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e8871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e8871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e8871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffe6f2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (2691 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a149171eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a14916ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a14917262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d30133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d3018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d30133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d3011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a149107bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a149107a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1490ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a148d9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a148d9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d3011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d3011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d3011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a148d9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (2697 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %shl = shl <16 x i32> %0, %1
# |   store <16 x i32> %shl, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 imma
# | ...
# `---data was truncated (10240/51475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005562154cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562154c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562154cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd234f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd234f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd234f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd234eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556215461bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556215461a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562154468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562150f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562150f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd234eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd234eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd234eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562150f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (2701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset, i64 no
# | ...
# `---data was truncated (10240/287205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563be08f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563be08f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563be08f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7be7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7be7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7be7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7be7e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563be088ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563be088ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563be08738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563be0522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563be0522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7be7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7be7e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7be7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563be0522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (2702 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp sge <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp uge <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp sge <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6992a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b69929ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6992a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcd9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcd9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcd9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcd9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b699237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b699237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b69921c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b698ecbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b698ecbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcd9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcd9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcd9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b698ecba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (2705 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc48e81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc48e7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc48e8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd204c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd204ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd204c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd204c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc48e17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc48e17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc48dfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc48aabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc48aabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd204c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd204c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd204c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc48aaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (2710 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i3
# | ...
# `---data was truncated (10240/57708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056144c0b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056144c0b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056144c0b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff87ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff87ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff87ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff87ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056144c04abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056144c04aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056144c02f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056144bcdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056144bcdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff87ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff87ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff87ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056144bcdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (2722 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562181c0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562181c0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562181c0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8429c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8429ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8429c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8429c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562181ba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562181ba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562181b898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562181838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562181838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8429c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8429c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8429c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562181838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (2730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6ba862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6ba85fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6ba86362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc473333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc47338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc473333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc47331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6ba7f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6ba7f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6ba7dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6ba48ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6ba48cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc47331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc47331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc47331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6ba48ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (2734 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>,
# | ...
# `---data was truncated (10240/159327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a42d665eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a42d662e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a42d66662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cee51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a42d5fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a42d5fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a42d5e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a42d28fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a42d28fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cee51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a42d28fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (2737 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/12050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dc3cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562dc3ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562dc3cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87cec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dc3c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562dc3c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562dc3c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562dc38fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562dc38fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87cec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dc38faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (2745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585e0d6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585e0d6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585e0d6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb461049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4610a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb461049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb461031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585e0d03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585e0d03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585e0ce88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585e0997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585e0997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb461032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4610330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4610330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585e0997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (2753 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da82314eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da82311e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da8231562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6477333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f647738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6477333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f647731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da822aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da822aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da8228f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da81f3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da81f3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f647731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f647731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f647731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da81f3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (2754 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055beec0baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055beec0b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055beec0bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc644649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6446a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc644649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc644631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055beec050bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055beec050a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055beec0358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055beebce4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055beebce4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc644632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6446330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6446330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055beebce4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (2758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ecb508eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ecb505e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ecb50962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9e7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9e735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9e7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9e72ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ecb49ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ecb49ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ecb4838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ecb132e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ecb132b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9e72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9e72ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9e72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ecb132a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (2760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaacda5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaacda2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaacda662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff31f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff31f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff31f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff31f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaacd3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaacd3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaacd208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaac9cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaac9cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff31f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff31f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff31f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaac9cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (2761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556919e8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556919e89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556919e8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff548733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff54878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff548733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff54871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556919e22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556919e22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556919e078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556919ab6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556919ab6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff54871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff54871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff54871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556919ab6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (2765 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 
# | ...
# `---data was truncated (10240/39417) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d26da90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d26da8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d26da9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7af3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7af318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7af3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7af311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d26da26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d26da26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d26da0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d26d6bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d26d6bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7af311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7af311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7af311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d26d6baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (2772 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = or <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = or <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = or <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = or <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32
# | ...
# `---data was truncated (10240/10897) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055629c609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055629c606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055629c60a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1570a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1570aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1570a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1570a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055629c59fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055629c59fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055629c5848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055629c233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055629c233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1570a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1570a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1570a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055629c233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (2773 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7a503ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7a5039e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7a503d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1eff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1eff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1eff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1eff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7a4fd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7a4fd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7a4fb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7a4c66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7a4c66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1eff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1eff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1eff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7a4c66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (2774 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_rsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %splat.splat = shufflevector <vscale x 16 x i8> %splat.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %shl = shl <vscale x 16 x i8> %0, %splat.splat
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_lsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %0, i64 0
# |   %splat.splat
# | ...
# `---data was truncated (10240/32491) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056200a47aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056200a477e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056200a47b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dd1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dd118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dd1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dd111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056200a410bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056200a410a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056200a3f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056200a0a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056200a0a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dd111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dd111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dd111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056200a0a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (2775 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %and = and <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @or_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %or = or <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @xor_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vsca
# | ...
# `---data was truncated (10240/18831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564a68482eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a6847fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a6848362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5107933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f510798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5107933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f510791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a68418bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a68418a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a683fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a680ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a680acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f510791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f510791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f510791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a680aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2778 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i
# | ...
# `---data was truncated (10240/14644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645ac876eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645ac873e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645ac87762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19d4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19d4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19d4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19d4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645ac80cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645ac80ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645ac7f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645ac4a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645ac4a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19d4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19d4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19d4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645ac4a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (2779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feff188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feff185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feff18962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f661ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f661ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f661ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f661ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feff11ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feff11ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feff1038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fefedb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fefedb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f661ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f661ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f661ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fefedb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (2780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c36faaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c36faa9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c36faad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12f6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12f62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12f6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12f6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c36fa42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c36fa42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c36fa278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c36f6d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c36f6d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12f6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12f62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12f62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c36f6d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2784 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = al
# | ...
# `---data was truncated (10240/40137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581ff163eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581ff160e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581ff16462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c97f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c97f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c97f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c97f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581ff0f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581ff0f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581ff0de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581fed8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581fed8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c97f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c97f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c97f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581fed8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (2785 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc  -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <8 x i8>, ptr %__promote, align 8
# |   store <8 x i8> %1, ptr %__ret, align 8
# |   %2 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %2, ptr %tmp, align 8
# |   %3 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %.compoundliteral.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8>
# |   store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8
# |   store <8 x i8> %9, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %.compoundliteral.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> <i32 0, i32 1, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %9 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison
# | ...
# `---data was truncated (10240/101594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055d548995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d548992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d54899662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fda849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fda8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fda849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fda831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d54892bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d54892ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5489108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5485bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5485bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fda832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fda8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fda8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5485bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (2791 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |  
# | ...
# `---data was truncated (10240/29535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd0867beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd08678e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd0867c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd08611bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd08611a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd085f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd082a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd082a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f722eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd082a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (2796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565545997eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565545994e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056554599862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c84f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c84f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c84f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c84f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056554592dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056554592da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005655459128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005655455c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005655455c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c84f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c84f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c84f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005655455c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (2799 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local half @subscript_float16(<vscale x 8 x half> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 4 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %a.coerce, i64 0)
# |   store <16 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 2 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> %a.coerce, i64 0)
# |   store <8 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005593ae04ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593ae049e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593ae04d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe57a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe57aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe57a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe57a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593adfe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593adfe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593adfc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593adc76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593adc76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe57a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe57a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe57a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593adc76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (2801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a52312aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a523127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a52312b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9709449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9709449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9709431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5230c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5230c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5230a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a522d54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a522d54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9709432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a522d54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (2802 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e24c10eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e24c10be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e24c10f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bd3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bd32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bd3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bd3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e24c0a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e24c0a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e24c0898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e24bd38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e24bd38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bd3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bd32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bd32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e24bd38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (2804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %
# | ...
# `---data was truncated (10240/291999) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed6cafeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed6cafbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed6caff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe67fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe67fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe67fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe67fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed6ca94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed6ca94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed6ca798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed6c728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed6c728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe67fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe67fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe67fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed6c728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (2811 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5)
# |   %7 = extractvalue { i32, <4 x i32> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <4 x i32> } %6, 1
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# | 
# | ...
# `---data was truncated (10240/11454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd25aa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd25a9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd25aa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff461733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff46178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff461733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff46171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd25a38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd25a38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd25a1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd256cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd256ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff46171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff46171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff46171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd256cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (2814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8d55dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8d55dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8d55e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feedd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feedd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feedd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feedd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8d5575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8d5575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8d555a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8d5209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8d5209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feedd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feedd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feedd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8d5209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (2818 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576b21d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576b21cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576b21d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8162933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f816298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8162933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f816291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576b2166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576b2166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576b214b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576b1dfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576b1dfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f816291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f816291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f816291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576b1dfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (2820 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %
# | ...
# `---data was truncated (10240/11173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558780bc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558780bbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558780bc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c4db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c4db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c4db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c4db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558780b56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558780b56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558780b3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587807eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587807eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c4db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c4db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c4db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587807eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (2827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562869c81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562869c7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562869c8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f92505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f9255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f92505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f924ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562869c17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562869c17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562869bfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628698abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628698abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f924eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f924ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f924ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628698aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (2828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c391a00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3919fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c391a0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a5e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a5e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a5e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a5e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c391996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c391996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c39197b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c39162ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c39162ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a5e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a5e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a5e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c39162aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (2837 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab2c766eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab2c763e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab2c76762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feac2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feac278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feac2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feac271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab2c6fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab2c6fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab2c6e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab2c390e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab2c390b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feac271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feac271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feac271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab2c390a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (2842 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/11849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec8da59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec8da56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec8da5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b5cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b5cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b5cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b5caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec8d9efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec8d9efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec8d9d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec8d683e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec8d683b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b5caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b5caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b5caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec8d683a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (2844 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load ptr, ptr %carry.addr, align 4
# |   %4 = load i32, ptr %3, align 4
# |   %5 = shl i32 %4, 29
# |   %6 = load i16, ptr %p.addr, align 2
# |   %7 = zext i16 %6 to i32
# |   %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7)
# |   %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8)
# |   %10 = extractvalue { <4 x i32>, i32 } %9, 1
# |   %11 = lshr i32 %10, 29
# |   %12 = and i32 1, %11
# |   store i32 %12, ptr %3, align 4
# |   %13 = extractvalue { <4 x i32>, i32 } %9, 0
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>,
# | ...
# `---data was truncated (10240/14775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eff40e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eff40e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eff40ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4eaf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4eaf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4eaf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4eaf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eff407fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eff407fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eff40648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eff3d13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eff3d13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4eaf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4eaf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4eaf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eff3d13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (2846 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615ae2c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615ae2c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615ae2c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6706449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6706449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6706431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ae25abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615ae25aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615ae23f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615adeeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615adeeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6706432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615adeeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (2851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056550f961eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056550f95ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056550f96262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a35449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a35449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a35431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056550f8f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056550f8f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056550f8dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056550f58be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056550f58bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a35432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a354330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056550f58ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (2856 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8ac8c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8ac8bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8ac8c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f481ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f481eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f481ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f481ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8ac857bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8ac857a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8ac83c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8ac4ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8ac4ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f481ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f481ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f481ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8ac4eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (2858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae29847eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae29844e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae2984862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2c7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2c778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2c7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2c771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae297ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae297dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae297c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae29471e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae29471b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2c771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2c771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2c771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae29471a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (2869 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634511a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056345119ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634511a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6e3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6e3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6e3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6e3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563451137bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563451137a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056345111c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563450dcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563450dcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6e3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6e3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6e3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563450dcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (2890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627c1599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627c1596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627c159a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fdff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fdff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fdff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fdfeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627c152fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627c152fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627c15148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627c11c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627c11c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fdfeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fdfeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fdfeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627c11c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (2893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639c259beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639c2598e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639c259c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2983933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2983933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639c2531bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639c2531a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639c25168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639c21c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639c21c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f298391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639c21c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/neon/add.c (2898 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %add.i = add <16 x i8> %2, %3
# |   store <16 x i8> %add.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %add.i = add <8 x i16> %2, %3
# |   store <8 x i16> %add.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b
# | ...
# `---data was truncated (10240/221881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055902bcbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055902bcbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055902bcbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9275133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9275133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055902bc54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055902bc54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055902bc398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055902b8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055902b8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f927511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055902b8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (2901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c80054eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c80051e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c8005562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb842533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb84258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb842533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb84251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c7ffeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c7ffeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c7ffcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c7fc7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c7fc7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb84251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb84251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb84251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c7fc7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (2904 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp uge <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp uge <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp uge <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625c0ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625c0eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625c0ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56bf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56bf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56bf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56bf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625c0e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625c0e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625c0e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625c0ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625c0ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56bf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56bf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56bf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625c0ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (2909 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056040accfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056040accce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056040acd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8591533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f859158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8591533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f859151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056040ac65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056040ac65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056040ac4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056040a8f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056040a8f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f859151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f859151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f859151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056040a8f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (2932 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @subscript_float16(<vscale x 8 x half> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @subscript_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @subscript_float64(<vscale x 2 x double> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %1, float 1.000000e+00, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_read_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecext = extractelement <vscale x 4 x float> %1, i64 %0
# |   %add = fadd float %vecext, 1.000000e+00
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %2, float %add, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005636c5d4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636c5d4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636c5d4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f29705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f2975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f29705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f296ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636c5ce3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636c5ce3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636c5cc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636c5977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636c5977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f296eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f296ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f296ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636c5977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (2936 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = or <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = or <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = or <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = or <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, al
# | ...
# `---data was truncated (10240/11056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2f4430eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2f442de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2f443162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68a7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68a7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68a7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68a7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2f43c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2f43c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2f43ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2f405ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2f405ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68a7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68a7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68a7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2f405aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (2937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16
# | ...
# `---data was truncated (10240/338692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7b85c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7b85bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7b85c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dae031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7b8558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7b8558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7b853d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7b81ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7b81ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dae0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7b81eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (2938 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647ea2bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647ea2b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647ea2bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f801a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f801a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647ea252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647ea252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647ea2378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647e9ee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647e9ee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647e9ee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2941 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe0d4e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe0d4e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe0d4e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6aa2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6aa258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6aa2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6aa251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe0d47dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe0d47da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe0d4628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe0d111e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe0d111b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6aa251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6aa251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6aa251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe0d111a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (2943 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616817c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616817bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616817c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f358a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f358a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f358a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f358a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561681758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561681758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056168173d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616813ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616813ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f358a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f358a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f358a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616813eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (2946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f8490ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f84909e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f8490d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ee9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ee9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ee9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ee9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f848a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f848a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f848878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f84536e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f84536b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ee9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ee9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ee9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f84536a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (2948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/205805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561683615eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561683612e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056168361662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37c9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37c92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37c9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37c9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616835abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616835aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616835908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056168323fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056168323fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37c9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37c92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37c92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056168323fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (2963 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp eq <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 2 x double> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @neq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ne <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @neq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @neq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @neq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @neq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   stor
# | ...
# `---data was truncated (10240/44453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f963bbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f963bb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f963bbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ec1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ec1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ec1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ec1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f963b52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f963b52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f963b378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9637e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9637e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ec1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ec1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ec1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9637e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (2969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bbf377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bbf374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bbf37862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf13249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf132a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf13249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf13231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bbf30dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bbf30da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bbf2f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bbefa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bbefa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf13232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf132330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf132330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bbefa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (2974 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x half> %0, i32 2
# |   ret half %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x float> %0, i32 3
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 4
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 0
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 10
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 3
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 3
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 1
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 1
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca <8 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load half, ptr %a.addr, align 2
# |   %2 = insertelement <8 x half> %0, half %1, i32 4
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load float, ptr %a.addr, align 4
# |   %2 = insertelement <4 x float> %0, float %1, i32 2
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 12
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 6
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 2
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 0
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 2
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 7
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 1
# |   ret <2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055e863c20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e863c1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e863c2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa220b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa220b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa220b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa220b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e863bb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e863bb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e863b9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e86384ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e86384ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa220b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa220b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa220b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e86384aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (2978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056324730feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056324730ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056324731062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8d5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8d558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8d5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8d551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632472a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632472a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056324728a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563246f39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563246f39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8d551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8d551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8d551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563246f39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (2985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf0f7fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf0f7f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf0f7fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d7bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d7bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d7bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d7bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf0f792bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf0f792a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf0f7778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf0f426e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf0f426b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d7bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d7bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d7bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf0f426a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (2986 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9c08f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9c08f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9c08f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23cfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9c088ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9c088ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9c08738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9c0522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9c0522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9c0522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (2989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c3b1e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c3b1e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c3b1e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe828533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe82858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe828533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe82851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c3b179bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c3b179a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c3b15e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c3ae0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c3ae0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe82851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe82851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe82851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c3ae0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon-3v.c (2993 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %and.i = and <8 x i16> %2, %3
# |   store <8 x i16> %and.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %and.i = and <2 x i32> %2, %3
# |   store <2 x i32> %and.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %and.i = and <4 x i32> %2, %3
# |   store <4 x i32> %and.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %and.i = and <1 x i64> %2, %3
# |   store <1 x i64> %and.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %and.i = and <2 x i64> %2, %3
# |   store <2 x i64> %and.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, al
# | ...
# `---data was truncated (10240/70553) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c677f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c677f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c677f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4473133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4473133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f447311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c6778abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c6778aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c6776f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c6741ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c6741eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f447311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f447311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f447311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c6741ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (2995 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x 
# | ...
# `---data was truncated (10240/292007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556226008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556226005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055622600962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bfe649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bfe6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bfe649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bfe631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556225f9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556225f9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556225f838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556225c32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556225c32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bfe632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bfe6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bfe6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556225c32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (3003 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f68a57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f68a54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f68a5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5448f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5448f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5448f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5448f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f689edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f689eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f689d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f68681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f68681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5448f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5448f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5448f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f68681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (3006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e750792eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e75078fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e75079362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3deba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3debaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3deba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3deba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e750728bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e750728a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e75070d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7503bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7503bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3deba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3deba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3deba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7503bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (3009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebab977eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebab974e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebab97862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab3121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab312725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab3121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab31203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebab90dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebab90da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebab8f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebab5a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebab5a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab31204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab312050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab312050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebab5a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (3013 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/176535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559d54cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559d54c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559d54cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33f1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33f158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33f1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33f151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559d5461bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559d5461a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559d54468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559d50f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559d50f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33f151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33f151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33f151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559d50f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (3014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec6a8deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec6a8dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec6a8df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e80f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e80f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e80f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e80f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec6a874bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec6a874a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec6a8598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec6a508e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec6a508b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e80f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e80f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e80f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec6a508a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (3015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e06081aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e060817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e06081b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff0e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff0e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff0e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff0e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0607b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0607b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0607958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e060444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e060444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff0e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff0e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff0e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e060444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (3024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bf4980eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bf497de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bf498162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11a1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11a1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11a1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11a1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bf4916bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bf4916a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bf48fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bf45aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bf45aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11a1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11a1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11a1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bf45aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (3032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e50b7feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e50b7fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e50b7ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbe2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbe22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbe2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbe2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e50b794bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e50b794a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e50b7798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e50b428e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e50b428b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbe2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbe22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbe22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e50b428a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (3033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset
# | ...
# `---data was truncated (10240/287213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605c3696eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605c3693e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605c369762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65efb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65efb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65efb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65efaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605c362cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605c362ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605c36118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605c32c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605c32c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65efaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65efaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65efaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605c32c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (3041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c019981eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c01997ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c01998262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67d3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67d3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67d3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67d3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c019917bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c019917a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0198fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0195abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0195abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67d3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67d3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67d3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0195aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (3046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e91862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e9185fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e9186362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7707049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77070a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7707049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7707031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e917f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e917f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e917dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e9148ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e9148cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7707032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77070330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77070330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e9148ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (3052 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   
# | ...
# `---data was truncated (10240/223129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b416c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b416c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b416c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7ba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7ba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7ba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7ba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b416c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b416c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b416bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4168a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4168a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7ba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7ba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7ba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4168a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (3053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a82c8feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a82c8fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a82c8ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f975b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f975b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f975b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f975b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a82c894bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a82c894a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a82c8798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a82c528e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a82c528b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f975b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f975b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f975b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a82c528a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (3063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d3c3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d3c3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d3c3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa438933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa43898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa438933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa43891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d3bd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d3bd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d3bb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d3867e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d3867b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa43891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa43891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa43891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d3867a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (3066 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5abec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5abec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5abec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f889f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f889f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f889f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f889f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5abe5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5abe5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5abe418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5abaf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5abaf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f889f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f889f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f889f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5abaf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (3075 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bbec8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bbec87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bbec8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc34449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc34449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc34431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bbec20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bbec20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bbec058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bbe8b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bbe8b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc34432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc344330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bbe8b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (3078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591daa7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591daa7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591daa7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc856a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc856aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc856a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc856a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591daa13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591daa13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591da9f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591da6a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591da6a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc856a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc856a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc856a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591da6a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (3080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc49d09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc49d06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc49d0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c41049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c410a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c41049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c41031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc49c9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc49c9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc49c848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc49933e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc49933b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c41032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c410330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c410330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc49933a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (3089 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i
# | ...
# `---data was truncated (10240/215478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571044e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571044e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571044e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62c1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62c178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62c1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62c171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055710447ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055710447ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571044638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557104112e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557104112b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62c171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62c171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62c171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557104112a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (3090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | ...
# `---data was truncated (10240/66298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056456f370eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056456f36de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056456f37162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb784f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb784f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb784f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb784eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056456f306bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056456f306a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056456f2eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056456ef9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056456ef9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb784eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb784eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb784eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056456ef9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (3091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8b3a54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8b3a51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8b3a5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f18933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f1898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f18933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f1891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8b39eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8b39eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8b39cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8b367ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8b367eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f1891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f1891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f1891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8b367ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (3093 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6)
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <4 x float> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load <4 x float>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %10, ptr %__ret.i, align 16
# |   %11 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %c.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6)
# |   store <2 x double> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %10, ptr %__ret.i, align 16
# |   %11 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x float>
# |   %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> <i32 1, i32 1>
# |   %fmla = bitcast <8 x i8> %4 to <2 x float>
# |   %fmla1 = bitcast <8 x i8> %3 to <2 x float>
# |   %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1)
# |   store <2 x float> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/80179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b3d8816eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3d8813e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3d881762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb17533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb1758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb17533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb1751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3d87acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3d87aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3d87918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3d8440e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3d8440b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb1751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb1751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb1751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3d8440a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (3095 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   
# | ...
# `---data was truncated (10240/17536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562909bf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562909bf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562909bf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcc6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcc615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcc6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcc60ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562909b89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562909b89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562909b6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056290981de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056290981db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcc60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcc60ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcc60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056290981da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (3096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564644d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564644cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564644d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e3de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e3dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e3de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e3de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564644c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564644c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564644c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056464492ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056464492ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e3de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e3de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e3de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056464492aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (3097 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 =
# | ...
# `---data was truncated (10240/19190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ceebf96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ceebf93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ceebf9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1932d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1932d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1932d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1932ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceebf2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ceebf2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ceebf118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ceebbc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ceebbc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1932ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1932cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1932cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ceebbc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (3099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056110fd46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056110fd43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056110fd4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84f111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056110fcdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056110fcdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056110fcc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056110f970e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056110f970b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84f111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056110f970a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (3108 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b2bb71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b2bb6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b2bb7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4fee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4fee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4fee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4fee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b2bb07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b2bb07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b2baec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b2b79be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b2b79bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4fee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4fee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4fee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b2b79ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (3110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055806f9a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055806f99ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055806f9a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4205a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4205aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4205a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4205a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055806f937bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055806f937a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055806f91c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055806f5cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055806f5cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4205a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4205a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4205a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055806f5cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/poly128.c (3118 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   ret i128 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__s1 = alloca i128, align 16
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   store i128 %4, ptr %__s1, align 16
# |   %5 = load ptr, ptr %ptr.addr, align 8
# |   %add.ptr = getelementptr inbounds i128, ptr %5, i64 1
# |   %6 = load i128, ptr %__s1, align 16
# |   store i128 %6, ptr %add.ptr, align 16
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca i128, align 16
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load i64, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3)
# |   %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128
# |   store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16
# |   %4 = load i128, ptr %ref.tmp.i, align 16
# |   store i128 %4, ptr %__ret.i, align 16
# |   %5 = load i128, ptr %__ret.i, align 16
# |   ret i128 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
# | entry:
# |   %__p0.addr.i3 = alloca <2 x i64>, align 16
# |   %__ret.i4 = alloca <1 x i64>, align 8
# |   %__p0.addr.i1 = alloca <2 x i64>, align 16
# |   %__ret.i2 = alloca <1 x i64>, align 8
# |   %__p0.addr.i.i = alloca i64, align 8
# |   %__p1.addr.i.i = alloca i64, align 8
# |   %__ret.i.i = alloca i128, align 16
# |   %ref.tmp.i.i = alloca i128, align 16
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %ref.tmp1.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %2, ptr %__p0.addr.i3, align 16
# |   %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i4, align 8
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load i64, ptr %ref.tmp.i, align 8
# |   %7 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   store <2 x i64> %7, ptr %__p0.addr.i1, align 16
# |   %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8
# |   %10 = load <1 x i64>, ptr %__ret.i2, align 8
# |   store <1 x i64> %10, ptr %ref.tmp1.i, align 8
# |   %11 = load i64, ptr %ref.tmp1.i, align 8
# |   store i64 %6, ptr %__p0.addr.i.i, align 8
# |   store i64 %11, ptr %__p1.addr.i.i, align 8
# |   %12 = load i64, ptr %__p0.addr.i.i, align 8
# |   %13 = load i64, ptr %__p1.addr.i.i, align 8
# |   %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13)
# |   %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128
# |   store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16
# |   %14 = load i128, ptr %ref.tmp.i.i, align 16
# |   store i128 %14, ptr %__ret.i.i, align 16
# |   %15 = load i128, ptr %__ret.i.i, align 16
# |   store i128 %15, ptr %__ret.i, align 16
# |   %16 = load i128, ptr %__ret.i, align 16
# |   ret i128 %16
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.ad
# | ...
# `---data was truncated (10240/19795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555879963eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555879960e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055587996462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6064b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6064b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6064b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6064aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558798f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558798f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558798de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055587958de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055587958db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6064aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6064aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6064aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055587958da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (3126 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6)
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6)
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__p1.addr.i.i = alloca <4 x half>, align 8
# |   %__p2.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %13, ptr %__ret.i.i, align 8
# |   %14 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <8 x half>, align 16
# |   %__p1.addr.i.i = alloca <8 x half>, align 16
# |   %__p2.addr.i.i = alloca <8 x half>, align 16
# |   %__ret.i.i = alloca <8 x half>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i.i, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i.i, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16
# |   store <8 x half> %13, ptr %__ret.i.i, align 16
# |   %14 = load <8 x half>, ptr %__ret.i.i, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1)
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1
# | ...
# `---data was truncated (10240/42739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bb78ec5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb78ec2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb78ec662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23a1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23a1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23a1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23a1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb78e5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb78e5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb78e408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb78aefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb78aefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23a1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23a1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23a1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb78aefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (3133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vs
# | ...
# `---data was truncated (10240/210427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb84111eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb8410ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb8411262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb898333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb89838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb898333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb89831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb840a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb840a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb8408c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb83d3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb83d3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb89831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb89831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb89831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb83d3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (3137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/235596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e928f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e928efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e928f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9181733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f918178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9181733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f918171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e92888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e92888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e9286d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e9251ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e9251cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f918171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f918171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f918171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e9251ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (3139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec2e55feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec2e55ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec2e56062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aac133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aac18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aac133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aac11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec2e4f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec2e4f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec2e4da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec2e189e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec2e189b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aac11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aac11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aac11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec2e189a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (3143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561db2addeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561db2adae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561db2ade62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3070e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3070ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3070e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3070e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561db2a73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561db2a73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561db2a588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561db2707e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561db2707b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3070e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3070e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3070e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561db2707a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (3144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4a489ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4a4899e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4a489d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc411933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc41198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc411933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc41191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4a4832bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4a4832a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4a48178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4a44c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4a44c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc41191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc41191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc41191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4a44c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (3146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056215cba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056215cba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056215cba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb9e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb9e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb9e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb9e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056215cb3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056215cb3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056215cb208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056215c7cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056215c7cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb9e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb9e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb9e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056215c7cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (3153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dd1c9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555dd1c97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555dd1c9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a05249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a05249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a05231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dd1c30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555dd1c30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555dd1c158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555dd18c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555dd18c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a05232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dd18c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (3154 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16  -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_812 = alloca <4 x float>, align 16
# |   %__s0_812 = alloca <4 x float>, align 16
# |   %__s1_812 = alloca <8 x bfloat>, align 16
# |   %__s2_812 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <4 x float>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp2 = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0_812, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1_812, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <8 x bfloat> %2, ptr %__s2_812, align 16
# |   %3 = load <4 x float>, ptr %__s0_812, align 16
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 16
# |   %5 = load <4 x float>, ptr %__s2_812, align 16
# |   store <4 x float> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 16
# |   store <4 x float> %8, ptr %__ret, align 16
# |   %9 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %9, ptr %tmp, align 16
# |   %10 = load <4 x float>, ptr %tmp, align 16
# |   store <4 x float> %10, ptr %ref.tmp, align 16
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %15, ptr %__ret.i, align 16
# |   %16 = load <4 x float>, ptr %__ret.i, align 16
# |   store <4 x float> %16, ptr %__ret_812, align 16
# |   %17 = load <4 x float>, ptr %__ret_812, align 16
# |   store <4 x float> %17, ptr %tmp2, align 16
# |   %18 = load <4 x float>, ptr %tmp2, align 16
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>,
# | ...
# `---data was truncated (10240/54685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563176a9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563176a9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563176aa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8931e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8931ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8931e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8931e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563176a35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563176a35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563176a1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631766c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631766c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8931e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8931e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8931e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631766c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (3164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568faf4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568faf4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568faf4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f696dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f696dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f696dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f696dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568faee4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568faee4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568faec98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568fab78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568fab78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f696dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f696dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f696dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568fab78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (3168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577c14aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577c14a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577c14ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0cf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0cf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0cf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0cf0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577c1440bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577c1440a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577c14258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577c10d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577c10d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0cf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0cf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0cf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577c10d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (3174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560730a22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560730a1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560730a2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae57831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607309b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607309b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056073099d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056073064ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056073064cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056073064ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (3175 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i)
# |   store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i)
# |   store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i)
# |   store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i)
# |   store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i)
# |   store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i)
# |   store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/162735) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005653ff322eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653ff31fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653ff32362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15d2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15d28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15d2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15d2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653ff2b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653ff2b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653ff29d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653fef4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653fef4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15d2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15d28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15d28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653fef4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm64_vcopy.c (3177 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_336 = alloca <16 x i8>, align 16
# |   %__s0_336 = alloca <16 x i8>, align 16
# |   %__s2_336 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_336, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_336, align 16
# |   %2 = load <16 x i8>, ptr %__s2_336, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_336, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_336, align 16
# |   %13 = load <16 x i8>, ptr %__ret_336, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_328 = alloca <16 x i8>, align 16
# |   %__s0_328 = alloca <16 x i8>, align 16
# |   %__s2_328 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_328, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_328, align 16
# |   %2 = load <16 x i8>, ptr %__s2_328, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_328, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_328, align 16
# |   %13 = load <16 x i8>, ptr %__ret_328, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_346 = alloca <8 x i16>, align 16
# |   %__s0_346 = alloca <8 x i16>, align 16
# |   %__s2_346 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_346, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_346, align 16
# |   %2 = load <8 x i16>, ptr %__s2_346, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_346, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_346, align 16
# |   %13 = load <8 x i16>, ptr %__ret_346, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_334 = alloca <8 x i16>, align 16
# |   %__s0_334 = alloca <8 x i16>, align 16
# |   %__s2_334 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_334, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_334, align 16
# |   %2 = load <8 x i16>, ptr %__s2_334, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_334, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_334, align 16
# |   %13 = load <8 x i16>, ptr %__ret_334, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <4 x i32>, align 16
# |   %a2.addr = alloca <4 x i32>, align 16
# |   %__ret_340 = alloca <4 x i32>, align 16
# |   %__s0_340 = alloca <4 x i32>, align 16
# |   %__s2_340 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca i32, align 4
# |   %__ret1 = alloca i32, align 4
# |   %__s02 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp3 = alloca <4 x i32>, align 16
# |   %tmp4 = alloca <4 x i32>, align 16
# |   %tmp5 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a1, ptr %a1.addr, align 16
# |   store <4 x i32> %a2, ptr %a2.addr, align 16
# |   %0 = load <4 x i32>, ptr %a1.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_340, align 16
# |   %1 = load <4 x i32>, ptr %a2.addr, align 16
# |   store <4 x i32> %1, ptr %__s2_340, align 16
# |   %2 = load <4 x i32>, ptr %__s2_340, align 16
# |   store <4 x i32> %2, ptr %__s02, align 16
# |   %3 = load <4 x i32>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <4 x i32> %3, i32 3
# |   store i32 %vgetq_lane, ptr %ref.tmp, align 4
# |   %4 = load i32, ptr %ref.tmp, align 4
# |   store i32 %4, ptr %__ret1, align 4
# |   %5 = load i32, ptr %__ret1, align 4
# |   store i32 %5, ptr %tmp, align 4
# |   %6 = load i32, ptr %tmp, align 4
# |   store i32 %6, ptr %__s0, align 4
# |   %7 = load <4 x i32>
# | ...
# `---data was truncated (10240/22011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4ad53beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4ad538e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4ad53c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2109733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f210978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2109733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f210971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4ad4d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4ad4d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4ad4b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4ad165e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4ad165b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f210971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f210971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f210971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4ad165a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (3181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555abacbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555abacbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555abacbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e47705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e4775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e47705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e476ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555abac53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555abac53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555abac388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555aba8e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555aba8e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e476eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e476ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e476ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aba8e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (3198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056001c11beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056001c118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056001c11c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056001c0b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056001c0b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056001c0968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056001bd45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056001bd45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056001bd45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (3199 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566986b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566986b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566986b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9585b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9585b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9585b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9585b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556698649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556698649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055669862e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566982dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566982ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9585b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9585b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9585b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566982dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (3203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ca2ccbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ca2cc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ca2ccc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9acee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9acee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9acee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ca2c61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ca2c61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ca2c468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ca28f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ca28f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9acee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9acee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9acee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ca28f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (3209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560638a00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606389fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560638a0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f26ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560638996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560638996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056063897b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056063862ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056063862ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16f26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f26ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056063862aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (3213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b37c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b37c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b37c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2253f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2253f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2253f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2253f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b37bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b37bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b37bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b3785de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b3785db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2253f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2253f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2253f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b3785da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (3215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056093207aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560932077e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056093207b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9c331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560932010bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560932010a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560931ff58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560931ca4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560931ca4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9c331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560931ca4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (3218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dace20aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dace207e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dace20b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0bf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dace1a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dace1a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dace1858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dacde34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dacde34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dacde34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (3220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558845271eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055884526ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055884527262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57eef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57eef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57eef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57eef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558845207bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558845207a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588451ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558844e9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558844e9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57eef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57eef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57eef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558844e9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (3226 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e42d40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e42d3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e42d4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b92533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b9258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b92533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b9251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e42cd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e42cd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e42cbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e4296ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e4296ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b9251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b9251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b9251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e4296aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon-fma.c (3228 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %sub.i = fsub <4 x float> %3, %mul.i
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %sub.i = fsub <2 x float> %3, %mul.i
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_68 = alloca <2 x float>, align 8
# |   %__s0_68 = alloca <2 x float>, align 8
# |   %__s1_68 = alloca <2 x float>, align 8
# |   %__s2_68 = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp1 = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0_68, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_68, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_68, align 8
# |   %3 = load <2 x float>, ptr %__s0_68, align 8
# |   %4 = load <2 x float>, ptr %__s1_68, align 8
# |   %5 = load <2 x float>, ptr %__s2_68, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   %mul = fmul <2 x float> %4, %10
# |   %add = fadd <2 x float> %3, %mul
# |   store <2 x float> %add, ptr %__ret_68, align 8
# |   %11 = load <2 x float>, ptr %__ret_68, align 8
# |   store <2 x float> %11, ptr %tmp1, align 8
# |   %12 = load <2 x float>, ptr %tmp1, align 8
# |   ret <2 x float> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_58 = alloca <4 x float>, align 16
# |   %__s0_58 = alloca <4 x float>, align 16
# |   %__s1_58 = alloca <4 x float>, align 16
# |   %__s2_58 = alloca <2 x float>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp1 = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__s0_58, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_58, align 16
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_58, align 8
# |   %3 = load <4 x float>, ptr %__s0_58, align 16
# |   %4 = load <4 x float>, ptr %__s1_58, align 16
# |   %5 = load <2 x float>, ptr %__s2_58, align 8
# |   store <2 x f
# | ...
# `---data was truncated (10240/44730) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a0f8812eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0f880fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0f881362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f8a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f8a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f8a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f8a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0f87a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0f87a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0f878d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0f843ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0f843cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f8a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f8a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f8a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0f843ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (3234 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e93239deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e93239ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e93239e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bf3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bf358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bf3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bf351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e932333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e932333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9323188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e931fc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e931fc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bf351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bf351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bf351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e931fc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (3235 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583fa003eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583fa000e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583fa00462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583f9f99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583f9f99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583f9f7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583f9c2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583f9c2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f982b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583f9c2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (3237 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582cce8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582cce88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582cce8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf6e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf6e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf6e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf6e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582cce21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582cce21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582cce068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582ccab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582ccab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf6e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf6e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf6e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582ccab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (3241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e328271eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e32826ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e32827262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa25cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa25cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa25cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa25cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e328207bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e328207a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3281ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e327e9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e327e9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa25cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa25cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa25cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e327e9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (3244 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, ali
# | ...
# `---data was truncated (10240/280217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b4654aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b46547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b4654b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe555049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe555049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe555031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b464e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b464e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b464c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b46174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b46174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe555032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5550330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b46174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (3249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b233eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b233ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b233ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f840f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f840f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f840f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f840f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b23384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b23384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b233698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b23018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b23018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f840f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f840f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f840f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b23018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (3252 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1a7e99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1a7e96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1a7e9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff25a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff25a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff25a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff25a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1a7e2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1a7e2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1a7e148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1a7ac3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1a7ac3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff25a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff25a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff25a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1a7ac3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (3254 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d51473ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d514739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d51473d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6588333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f658838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6588333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f658831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5146d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5146d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5146b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d514366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d514366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f658831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f658831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f658831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d514366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (3255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621cd32aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621cd327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621cd32b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20c7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20c718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20c7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20c711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621cd2c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621cd2c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621cd2a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621ccf54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621ccf54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20c711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20c711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20c711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621ccf54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (3256 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3a4a52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3a4a4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3a4a5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb55041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5504725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb55041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb550403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3a49e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3a49e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3a49cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3a467ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3a467cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb550404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5504050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5504050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3a467ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/AArch64/neon/getset.c (3259 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <1 x i8>, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <1 x i8>, align 1
# |   %tmp = alloca <1 x i8>, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load <1 x i8>, ptr %ref.tmp, align 1
# |   store <1 x i8> %2, ptr %__ret, align 1
# |   %3 = load <1 x i8>, ptr %__ret, align 1
# |   store <1 x i8> %3, ptr %tmp, align 1
# |   %4 = load <1 x i8>, ptr %tmp, align 1
# |   ret <1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_847 = alloca half, align 2
# |   %__s0_847 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp1 = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %tmp2 = alloca half, align 2
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_847, align 8
# |   %1 = load <4 x i16>, ptr %__s0_847, align 8
# |   store <4 x i16> %1, ptr %__s0, align 8
# |   %2 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %2, i32 1
# |   store i16 %vget_lane, ptr %ref.tmp1, align 2
# |   %3 = load i16, ptr %ref.tmp1, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   store i16 %5, ptr %ref.tmp, align 2
# |   %6 = load half, ptr %ref.tmp, align 2
# |   store half %6, ptr %__ret_847, align 2
# |   %7 = load half, ptr %__ret_847, align 2
# |   store half %7, ptr %tmp2, align 2
# |   %8 = load half, ptr %tmp2, align 2
# |   %conv = fpext half %8 to float
# |   ret float %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %1, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %1, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align
# | ...
# `---data was truncated (10240/76998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555e635caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e635c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e635cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ae3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ae3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ae3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ae3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e63560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e63560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e635458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e631f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e631f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ae3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ae3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ae3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e631f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (3264 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f817951eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f81794ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f81795262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c07c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c07ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c07c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c07c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8178e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8178e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8178cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f81757be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f81757bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c07c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c07c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c07c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f81757ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (3265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559017249eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559017246e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055901724a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73a5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73a5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73a5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73a5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590171dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590171dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590171c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559016e73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559016e73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73a5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73a5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73a5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559016e73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (3267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bce8dd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bce8dd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bce8dd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ad7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ad758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ad7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ad751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bce8d6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bce8d6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bce8d538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bce8a02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bce8a02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ad751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ad751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ad751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bce8a02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (3270 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp ule <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp ule <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp ule <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596c9184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596c9181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596c918562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b8a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b8a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b8a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b8a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596c911abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596c911aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596c90ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596c8daee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596c8daeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b8a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b8a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b8a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596c8daea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (3271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055928365eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055928365be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055928365f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a3d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a3d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a3d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a3d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592835f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592835f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592835d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559283288e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559283288b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a3d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a3d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a3d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559283288a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (3273 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc5739ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc57399e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc5739d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d1a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d1a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc57332bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc57332a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc573178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc56fc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc56fc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d1a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d1a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d1a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc56fc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (3285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d0dedfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d0dedce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d0dee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35ec41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35ec4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35ec41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35ec403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d0de75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d0de75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d0de5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d0db09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d0db09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35ec404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35ec4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35ec4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d0db09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (3288 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x 
# | ...
# `---data was truncated (10240/18674) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9a7f30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9a7f2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9a7f3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9e6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9e6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9e6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9e6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9a7ec6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9a7ec6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9a7eab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9a7b5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9a7b5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9e6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9e6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9e6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9a7b5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (3290 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056133c231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056133c22ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056133c23262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde50049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde500a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde50049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde50031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056133c1c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056133c1c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056133c1ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056133be5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056133be5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde50032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde500330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde500330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056133be5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (3300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwi
# | ...
# `---data was truncated (10240/235604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597895adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597895aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597895ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e8ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e8aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e8ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e8ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559789543bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559789543a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597895288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597891d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597891d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e8ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e8ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e8ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597891d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (3301 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> <i32 1>
# |   store <1 x double> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/20383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647fa6a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647fa6a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647fa6a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8463f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8463f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8463f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8463f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647fa63abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647fa63aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647fa61f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647fa2cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647fa2ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8463f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8463f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8463f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647fa2cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (3302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9864caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9864c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9864cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f986460bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f986460a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9864458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9860f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9860f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9860f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (3307 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   
# | ...
# `---data was truncated (10240/169917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556acf00eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556acf00be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556acf00f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89b781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89b78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89b781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89b7803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556acefa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556acefa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556acef898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556acec38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556acec38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89b7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89b78050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89b78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556acec38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (3314 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_571 = alloca float, align 4
# |   %__s0_571 = alloca float, align 4
# |   %__s1_571 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_571, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_571, align 8
# |   %2 = load float, ptr %__s0_571, align 4
# |   %3 = load <2 x float>, ptr %__s1_571, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_571, align 4
# |   %8 = load float, ptr %__ret_571, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret_570 = alloca double, align 8
# |   %__s0_570 = alloca double, align 8
# |   %__s1_570 = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_570, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_570, align 8
# |   %2 = load double, ptr %__s0_570, align 8
# |   %3 = load <1 x double>, ptr %__s1_570, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %4, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_570, align 8
# |   %8 = load double, ptr %__ret_570, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_577 = alloca float, align 4
# |   %__s0_577 = alloca float, align 4
# |   %__s1_577 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_577, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_577, align 16
# |   %2 = load float, ptr %__s0_577, align 4
# |   %3 = load <4 x float>, ptr %__s1_577, align 16
# |   store <4 x float> %3, ptr %__s0, align 16
# |   %4 = load <4 x float>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <4 x float> %4, i32 3
# |   store float %vgetq_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_577, align 4
# |   %8 = load float, ptr %__ret_577, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret_575 = alloca double, align 8
# |   %__s0_575 = alloca double, align 8
# |   %__s1_575 = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_575, align 8
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1_575, align 16
# |   %2 = load double, ptr %__s0_575, align 8
# |   %3 = load <2 x double>, ptr %__s1_575, align 16
# |   store <2 x double> %3, ptr %__s0, align 16
# |   %4 = load <2 x double>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <2 x double> %4, i32 1
# |   store double %vgetq_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_575, align 8
# |   %8 = load double, ptr %__ret_575, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca double, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store double %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x double>, ptr %__p0.addr.i, align 8
# |   %3 = load double, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <1 x double> %2 to double
# |   %5 = fmul double %4, %3
# |   store double %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_626 = alloca float, align 4
# |   %__s0_626 = alloca float, align 4
# |   %__s1_626 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_626, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_626, align 8
# |   %2 = load float, ptr %__s0_626, align 4
# |   %3 = load <2 x float>, ptr %__s1_626, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   store float %2, ptr %__p0.addr.i, align 4
# |   store float %7, ptr %__p1.addr.i, align 4
# |   %8 = load float, ptr %__p0.addr.i, align 4
# |   %9 = load float, ptr %__p1.addr.i, align 4
# |   %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9)
# |   store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4
# |   %10 = load float, ptr %ref.tmp.i, align 4
# |   store float %10, ptr %__ret.i, align 4
# |   %11 = load float, ptr %__ret.i, align 4
# |   store float %11, ptr %__ret_626, align 4
# |   %12 = load float, ptr %__ret_626, align 4
# |   store float %12, ptr %tmp1, align 4
# |   %13 = load float, ptr %tmp1, align 4
# |   ret float %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_636 = alloca float, align 4
# |   %__s0_636 = alloca float, align 4
# |   %__s1_636 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_636, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_636, align 16
# |   %2 = load float, ptr %__s0_636, align 4
# |   %3 = load <4 x float>, ptr %__s1_636, align 16
# |   store <4 x float> %3, ptr %
# | ...
# `---data was truncated (10240/74804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556ecb362eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ecb35fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ecb36362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2570049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25700a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2570049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2570031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ecb2f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ecb2f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ecb2dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ecaf8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ecaf8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2570032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25700330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25700330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ecaf8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (3315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb19ddaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb19dd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb19ddb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f4a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f4a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f4a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f4a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb19d70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb19d70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb19d558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb19a04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb19a04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f4a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f4a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f4a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb19a04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (3327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cdd105eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cdd102e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cdd10662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cb9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cb9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cb9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cb9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cdd09bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cdd09ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cdd0808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cdcd2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cdcd2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cb9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cb9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cb9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cdcd2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (3330 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %low.addr = alloca <4 x half>, align 8
# |   %high.addr = alloca <4 x half>, align 8
# |   store <4 x half> %low, ptr %low.addr, align 8
# |   store <4 x half> %high, ptr %high.addr, align 8
# |   %0 = load <4 x half>, ptr %low.addr, align 8
# |   %1 = load <4 x half>, ptr %high.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
# | entry:
# |   %__p0.addr.
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a04935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a04932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a0493662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c5c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c5c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c5c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c5c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a048cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a048cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a048b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a0455fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a0455fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c5c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c5c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c5c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a0455fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (3332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# | ...
# `---data was truncated (10240/170489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593fceb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593fceb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593fceb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff42d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff42d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff42d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff42d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593fce4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593fce4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593fce308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593fcadfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593fcadfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff42d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff42d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff42d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593fcadfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (3334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056267bdb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056267bdaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056267bdb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66d4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66d478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66d4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66d471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056267bd47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056267bd47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056267bd2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056267b9dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056267b9dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66d471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66d471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66d471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056267b9dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (3335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633e57e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633e57e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633e57ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f6ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f6ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f6ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f6ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633e577fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633e577fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633e57648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633e5413e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633e5413b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f6ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f6ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f6ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633e5413a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (3339 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/246606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8e8c77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8e8c74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8e8c7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febb0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febb08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febb0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febb0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8e8c0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8e8c0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8e8bf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8e88a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8e88a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febb0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febb08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febb08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8e88a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (3341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb5fef1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb5feeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb5fef262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e8621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e862725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e8621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e86203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb5fe87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb5fe87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb5fe6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb5fb1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb5fb1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e86204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e862050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e862050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb5fb1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (3346 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ac726deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ac726ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ac726e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f2eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f2eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f2eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f2eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ac7203bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ac7203a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ac71e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ac6e97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ac6e97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f2eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f2eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f2eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ac6e97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (3349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558312f04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558312f01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558312f0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5195105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f519515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5195105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51950ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558312e9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558312e9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558312e7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558312b2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558312b2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51950eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51950ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51950ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558312b2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (3352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7a6917eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7a6914e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7a691862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa40d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa40d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa40d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa40d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7a68adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7a68ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7a68928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7a6541e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7a6541b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa40d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa40d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa40d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7a6541a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (3360 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1
# |   store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %5, ptr %__ret, align 16
# |   %6 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %6, ptr %tmp, align 16
# |   %7 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0
# |   store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %5, ptr %__ret, align 8
# |   %6 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %6, ptr %tmp, align 8
# |   %7 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca 
# | ...
# `---data was truncated (10240/14230) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d29688aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d296887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d29688b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2449c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2449ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2449c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2449c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d296820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d296820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2968058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2964b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2964b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2449c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2449c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2449c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2964b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (3363 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to double
# |   %7 = bitcast <8 x i8> %4 to double
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %extract = extractelement <2 x double> %8, i32 0
# |   %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   %10 = bitcast double %9 to <1 x double>
# |   store <1 x double> %10, ptr %ref.tmp, align 8
# |   %11 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %11, ptr %__ret, align 8
# |   %12 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %12, ptr %tmp, align 8
# |   %13 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %13
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__s0, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1, align 16
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> <i32 1, i32 1>
# |   %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %9, ptr %ref.tmp, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %10, ptr %__ret, align 16
# |   %11 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %11, ptr %tmp, align 16
# |   %12 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load float, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %5, i32 1
# |   %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store float %6, ptr %ref.tmp, align 4
# |   %7 = load float, ptr %ref.tmp, align 4
# |   store float %7, ptr %__ret, align 4
# |   %8 = load float, ptr %__ret, align 4
# |   store float %8, ptr %tmp, align 4
# |   %9 = load float, ptr %tmp, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ac2f763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac2f760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac2f76462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bd961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bd96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bd961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bd9603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac2f6f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac2f6f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac2f6de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac2f38de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac2f38db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bd9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bd96050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bd96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac2f38da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (3368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e183adeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e183adbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e183adf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc693533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc69358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc693533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc69351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e183a74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e183a74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e183a598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e183708e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e183708b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc69351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc69351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc69351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e183708a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (3369 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.ad
# | ...
# `---data was truncated (10240/16274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056075035aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560750357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056075035b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70be305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70be35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70be305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70be2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607502f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607502f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607502d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056074ff84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056074ff84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70be2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70be2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70be2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074ff84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (3386 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be54079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be54076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be5407a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6a861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6a86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6a861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6a8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be5400fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be5400fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be53ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be53ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be53ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6a8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6a86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6a86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be53ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (3402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bbb076eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bbb073e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bbb07762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efeaa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efeaa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efeaa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efeaa631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bbb00cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bbb00ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bbaff18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bbaca0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bbaca0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efeaa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efeaa6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efeaa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bbaca0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (3405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8
# | ...
# `---data was truncated (10240/215036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564868e47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564868e44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564868e4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc120733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc12078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc120733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc12071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564868dddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564868ddda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564868dc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564868a71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564868a71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc12071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc12071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc12071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564868a71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (3407 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa3a8c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa3a8c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa3a8c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde47449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde47449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde47431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa3a85cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa3a85ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa3a8418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa3a4f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa3a4f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde47432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde474330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa3a4f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (3410 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717d705eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055717d702e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055717d70662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fb6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fb658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fb6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fb651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717d69bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055717d69ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055717d6808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055717d32fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055717d32fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fb651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fb651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fb651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717d32fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (3422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe8f0d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe8f0cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe8f0d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f43d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f43d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f43d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f43ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe8f066bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe8f066a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe8f04b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe8ecfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe8ecfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f43ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f43cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f43cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe8ecfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (3424 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %p0.addr = alloca <4 x float>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <4 x float> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <4 x float>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562a83091eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a8308ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a8309262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f435e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f435e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f435e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f435e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a83027bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a83027a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a8300c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a82cbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a82cbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f435e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f435e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f435e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a82cbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (3432 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i)
# |   %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i)
# |   %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i)
# |   %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i)
# |   %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i)
# |   %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i)
# |   %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i)
# |   %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i)
# |   %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i)
# |   %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i)
# |   %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f64.i = bitcast <8 x i8> %1 
# | ...
# `---data was truncated (10240/18543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d15133feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d15133ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d15134062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36a761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36a76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36a761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36a7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1512d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1512d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1512ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d150f69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d150f69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36a7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36a76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36a76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d150f69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (3434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c662014eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c662011e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c66201562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8008849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8008849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8008831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c661faabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c661faaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c661f8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c661c3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c661c3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8008832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80088330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c661c3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (3439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a68fad6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a68fad3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a68fad762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5445449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5445449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5445431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a68fa6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a68fa6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a68fa518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a68f700e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a68f700b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5445432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54454330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a68f700a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (3444 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vsc
# | ...
# `---data was truncated (10240/207075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2faf01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2faefee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2faf0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bbbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bbbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bbbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bbbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2fae97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2fae97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2fae7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2fab2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2fab2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bbbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bbbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bbbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2fab2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (3448 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# | 
# | ...
# `---data was truncated (10240/211223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9ba00feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9ba00ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9ba01062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ef31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9b9fa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9b9fa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9b9f8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9b9c39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9b9c39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9b9c39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (3457 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load 
# | ...
# `---data was truncated (10240/31171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563879a61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563879a5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563879a6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aec01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aec0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aec01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aec003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638799f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638799f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638799dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056387968be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056387968bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0aec004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aec0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aec0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056387968ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (3459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056176757eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056176757be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056176757f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff273849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff273849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff273831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561767514bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561767514a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617674f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617671a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617671a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff273832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2738330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617671a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (3469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1,
# | ...
# `---data was truncated (10240/223801) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570d95c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570d95c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570d95c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d1e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d1e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d1e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d1e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570d955dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570d955da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570d95428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570d91f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570d91f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d1e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d1e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d1e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570d91f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (3475 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a48f7feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a48f7fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a48f7ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe07cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe07cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe07cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe07cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a48f794bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a48f794a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a48f7798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a48f428e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a48f428b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe07cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe07cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe07cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a48f428a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (3479 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %w.addr = alloca float, align 4
# |   store float %w, ptr %w.addr, align 4
# |   %0 = load float, ptr %w.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %1, i32 0
# |   %2 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1
# |   %3 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2
# |   %4 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %5 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   store <4 x float> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
# | entry:
# |   %V.addr = alloca <1 x double>, align 8
# |   %__ret_379 = alloca <2 x double>, align 16
# |   %__s0_379 = alloca <1 x double>, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   %tmp1 = alloca <2 x double>, align 16
# |   store <1 x double> %V, ptr %V.addr, align 8
# |   %0 = load <1 x double>, ptr %V.addr, align 8
# |   store <1 x double> %0, ptr %__s0_379, align 8
# |   %1 = load <1 x double>, ptr %__s0_379, align 8
# |   store <1 x double> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer
# |   store <2 x double> %lane, ptr %ref.tmp, align 16
# |   %4 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %4, ptr %__ret, align 16
# |   %5 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %5, ptr %tmp, align 16
# |   %6 = load <2 x double>, ptr %tmp, align 16
# |   store <2 x double> %6, ptr %__ret_379, align 16
# |   %7 = load <2 x double>, ptr %__ret_379, align 16
# |   store <2 x double> %7, ptr %tmp1, align 16
# |   %8 = load <2 x double>, ptr %tmp1, align 16
# |   ret <2 x double> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %6 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %6, ptr %__ret, align 8
# |   %7 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %7, ptr %tmp, align 8
# |   %8 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6
# |   %9 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %10 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %10, ptr %__ret, align 16
# |   %11 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %11, ptr %tmp, align 16
# |   %12 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %12
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b38690eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b38690be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b38690f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f598fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f598fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f598fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f598fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3868a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3868a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3868898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b386538e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b386538b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f598fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f598fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f598fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b386538a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (3488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558273941eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055827393ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055827394262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c25249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c25249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c25231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582738d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582738d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582738bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055827356be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055827356bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c25232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055827356ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (3491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af6732deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af6732ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af6732e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e97e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e97ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e97e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e97e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af672c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af672c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af672a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af66f57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af66f57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e97e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e97e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e97e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af66f57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (3492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576154a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576154a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576154a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3df7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3df738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3df7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3df731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055761543cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055761543ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576154218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576150d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576150d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3df731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3df731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3df731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576150d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/poly64.c (3497 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %cmp.i = icmp eq <1 x i64> %2, %3
# |   %sext.i = sext <1 x i1> %cmp.i to <1 x i64>
# |   store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %cmp.i = icmp eq <2 x i64> %2, %3
# |   %sext.i = sext <2 x i1> %cmp.i to <2 x i64>
# |   store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %6 = and <1 x i64> %4, %5
# |   %7 = icmp ne <1 x i64> %6, zeroinitializer
# |   %vtst.i = sext <1 x i1> %7 to <1 x i64>
# |   store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8
# |   %8 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %8, ptr %__ret.i, align 8
# |   %9 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %6 = and <2 x i64> %4, %5
# |   %7 = icmp ne <2 x i64> %6, zeroinitializer
# |   %vtst.i = sext <2 x i1> %7 to <2 x i64>
# |   store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16
# |   %8 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %8, ptr %__ret.i, align 16
# |   %9 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_913 = alloca <1 x i64>, align 8
# |   %__s0_913 = alloca <1 x i64>, align 8
# |   %__s2_913 = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp3 = alloca <1 x i64>, align 8
# |   %tmp4 = alloca <1 x i64>, align 8
# |   %tmp5 = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0_913, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_913, align 8
# |   %2 = load <1 x i64>, ptr %__s2_913, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <1 x i64>, ptr %__s0_913, align 8
# |   store <1 x i64> %7, ptr %__s1, align 8
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <1 x i64>, ptr %__s1, align 8
# |   %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0
# |   store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <1 x i64>, ptr %ref.tmp3, align 8
# |   store <1 x i64> %10, ptr %__ret, align 8
# |   %11 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %11, ptr %tmp4, align 8
# |   %12 = load <1 x i64>, ptr %tmp4, align 8
# |   store <1 x i64> %12, ptr %__ret_913, align 8
# |   %13 = load <1 x i64>, ptr %__ret_913, align 8
# |   store <1 x i64> %13, ptr %tmp5, align 8
# |   %14 = load <1 x i64>, ptr %tmp5, align 8
# |   ret <1 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_909 = alloca <2 x i64>, align 16
# |   %__s0_909 = alloca <2 x i64>, align 16
# |   %__s2_909 = alloca <1 x i64>, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_909, align 16
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_909, align 8
# |   %2 = load <1 x i64>, ptr %__s2_909, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <2 x i64>, ptr %__s0_909, align 16
# |   store <2 x i64> %7, ptr %__s1, align 16
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <2 x i64>, ptr %__s1, align 16
# |   %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1
# |   store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <2 x i64>, ptr %ref.tmp3, align 16
# |   store <2 x i64> %10, ptr %__ret, align 16
# |   %11 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %11, ptr %tmp4, align 16
# |   %12 = load <2 x i64>, ptr %tmp4, align 16
# |   store <2 x i64> %12, ptr %__ret_909, align 16
# |   %13 = load <2 x i64>, ptr %__ret_909, align 16
# |   store <2 x i64> %13, ptr %tmp5, align 16
# |   %14 = load <2 x i64>, ptr %tmp5, align 16
# |   ret <2 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret_915 = alloca <2 x i64>, align 16
# |   %__s0_915 = alloca <2 x i64>, align 16
# |   %__s2_915 = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_915, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s2_915, align 16
# |   %2 = load <2 x i64>, ptr %__s2_915, align 16
# |   store <2 x i64> %2, ptr %__s02, align 16
# |   %3 = load <2 x i64>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <2 x i64> %3, i32 1
# |   store i64 %vgetq_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = 
# | ...
# `---data was truncated (10240/22456) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055adf9698eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adf9695e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adf969962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cd3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cd398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cd3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cd391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adf962ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adf962ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adf96138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adf92c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adf92c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cd391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cd391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cd391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adf92c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (3501 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.a
# | ...
# `---data was truncated (10240/174713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf6fc91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf6fc8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf6fc9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4e3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4e3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4e3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4e3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf6fc27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf6fc27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf6fc0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf6f8bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf6f8bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4e3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4e3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4e3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf6f8bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (3502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612d69aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612d69a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612d69ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b9a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b9a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b9a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b9a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612d6940bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612d6940a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612d69258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612d65d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612d65d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b9a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b9a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b9a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612d65d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (3506 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x bfloat> %1, i32 1
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x bfloat> %1, i32 7
# |   store bfloat %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_48 = alloca <4 x bfloat>, align 8
# |   %__s0_48 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_48, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_48, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_48, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_48, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_46 = alloca <8 x bfloat>, align 16
# |   %__s0_46 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_46, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_46, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_46, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_46, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_52 = alloca <4 x bfloat>, align 8
# |   %__s0_52 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_52, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_52, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_52, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_52, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_50 = alloca <8 x bfloat>, align 16
# |   %__s0_50 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_50, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_50, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_50, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_50, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %.compoundliteral.i = alloca <4 x bfloat>, align 8
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8
# |   store <4 x bfloat> %5, ptr %__ret.i, align 8
# |   %6 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %.compoundliteral.i = alloca <8 x bfloat>, align 16
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   %5 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4
# |   %6 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5
# |   %7 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6
# |   %8 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7
# |   store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/13833) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056284510deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056284510ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056284510e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cfa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cfa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cfa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cfa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628450a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628450a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628450888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562844d37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562844d37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cfa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cfa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cfa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562844d37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (3508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0086e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0086dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0086e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce44f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce44f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce44f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce44f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a008676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a008676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a00865b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a00830ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a00830ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce44f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce44f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce44f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a00830aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (3512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556be0616eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556be0613e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556be061762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effaf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effaf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effaf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effaf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556be05acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556be05aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556be05918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556be0240e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556be0240b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effaf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effaf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effaf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556be0240a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (3515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b94d399eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b94d396e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b94d39a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae5b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b94d32fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b94d32fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b94d3148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b94cfc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b94cfc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae5b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b94cfc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (3518 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %p0.addr = alloca <8 x half>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <8 x half> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <8 x half>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056314d886eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056314d883e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056314d88762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef3cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef3cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef3cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef3ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056314d81cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056314d81ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056314d8018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056314d4b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056314d4b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef3ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef3ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef3ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056314d4b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (3520 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %sr
# | ...
# `---data was truncated (10240/288111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627d9f4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627d9f49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627d9f4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f349e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f349e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f349e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f349e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627d9ee2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627d9ee2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627d9ec78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627d9b76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627d9b76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f349e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f349e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f349e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627d9b76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (3521 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebb60aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebb60a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebb60ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31bed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31bed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31bed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31bed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebb6040bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebb6040a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebb60258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebb5cd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebb5cd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31bed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31bed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31bed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebb5cd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (3526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056140da30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056140da2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056140da3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a9ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a9ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a9ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a9ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056140d9c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056140d9c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056140d9ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056140d65ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056140d65ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a9ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a9ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a9ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056140d65aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (3527 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <8 x i8>, al
# | ...
# `---data was truncated (10240/26059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055eabdb71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eabdb6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eabdb7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d23f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d23f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d23f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d23f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eabdb07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eabdb07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eabdaec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eabd79be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eabd79bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d23f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d23f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d23f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eabd79ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (3530 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# | 
# | ...
# `---data was truncated (10240/31781) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055690ebfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055690ebf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055690ebfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8001705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f800175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8001705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80016ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055690eb90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055690eb90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055690eb758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055690e824e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055690e824b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80016eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80016ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80016ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055690e824a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (3531 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646bdd82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646bdd7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646bdd8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ad1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ad155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ad1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ad14ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646bdd18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646bdd18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646bdcfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646bd9ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646bd9acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ad14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ad14ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ad14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646bd9aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (3532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598c6635eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598c6632e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598c663662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab47333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab4738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab47333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab4731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598c65cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598c65cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598c65b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598c625fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598c625fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab4731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab4731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab4731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598c625fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (3536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056388f37aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056388f377e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056388f37b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf87133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf8718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf87133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf8711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056388f310bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056388f310a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056388f2f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056388efa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056388efa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf8711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf8711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf8711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056388efa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (3537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c761aaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c761aabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c761aaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd648449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd648449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd648431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c761a44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c761a44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c761a298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7616d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7616d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd648432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6484330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7616d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (3538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0b5b13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0b5b10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0b5b1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f190a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f190a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f190a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f190a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0b5aa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0b5aa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0b5a8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0b573de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0b573db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f190a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f190a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f190a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0b573da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (3549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056139a004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056139a001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056139a00562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab2f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561399f9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561399f9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561399f7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561399c2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561399c2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561399c2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (3561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ca3150eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ca314de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ca315162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faba5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faba598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faba5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faba591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ca30e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ca30e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ca30cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ca2d7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ca2d7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faba591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faba591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faba591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ca2d7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (3562 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i)
# |   store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i)
# |   store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i)
# |   store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i)
# |   store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i)
# |   store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i)
# |   store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i)
# |   store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i)
# |   store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vrndns_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vrndn.i = call float @llvm.roundeven.f32(float %1)
# |   store float %vrndn.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i)
# |   store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndm.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i)
# |   store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i)
# |   store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a
# | ...
# `---data was truncated (10240/29785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557f84361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f8435ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f8436262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f842f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f842f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f842dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f83f8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f83f8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f83f8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (3563 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d397351eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d39734ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d39735262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd865533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd86558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd865533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd86551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3972e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3972e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3972cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d396f7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d396f7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd86551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd86551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd86551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d396f7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (3567 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/273705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563593015eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563593012e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056359301662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa678133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa67818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa678133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa67811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563592fabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563592faba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563592f908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563592c3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563592c3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa67811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa67811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa67811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563592c3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (3571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056362774eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056362774be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056362774f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facbb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facbb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facbb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facbb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636276e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636276e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636276c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563627378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563627378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facbb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facbb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facbb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563627378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (3577 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_and_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.and
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_or_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.or
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_xor_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.xor
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smax_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smin_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umax_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umin_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmax_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmin_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmaximum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.maximum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fminimum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.minimum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32_m8(<vscale x 16 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i32>, align 4
# |   store <vscale x 16 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 16 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @reduce_add_i64(<vscale x 1 x i64> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 1 x i64>, align 8
# |   store <vscale x 1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %a.addr, align 8
# |   %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %0)
# |   ret i64 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_mul_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.mul
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000560f1efc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f1efbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f1efc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9708849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9708849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9708831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f1ef56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f1ef56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f1ef3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f1ebeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f1ebeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9708832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97088330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f1ebeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (3586 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561083f37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561083f34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561083f3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4caed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4caed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4caed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4caed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561083ecdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561083ecda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561083eb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561083b61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561083b61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4caed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4caed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4caed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561083b61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (3587 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e622914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e622911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e62291562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c8e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c8e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6228aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6228aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e62288f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e62253ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e62253eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c8e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e62253ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (3593 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563468fb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563468fafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563468fb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf2c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf2c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf2c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf2c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563468f48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563468f48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563468f2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563468bdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563468bdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf2c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf2c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf2c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563468bdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (3594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dad9ea8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dad9ea5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dad9ea962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e93333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e9338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e93333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e9331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dad9e3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dad9e3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dad9e238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dad9ad2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dad9ad2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e9331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e9331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e9331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dad9ad2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (3598 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <4 x bfloat>, ptr %__promote, align 8
# |   store <4 x bfloat> %1, ptr %__ret, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %2, ptr %tmp, align 8
# |   %3 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x bfloat>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %low.addr = alloca <4 x bfloat>, align 8
# |   %high.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %low, ptr %low.addr, align 8
# |   store <4 x bfloat> %high, ptr %high.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %low.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %high.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x bfloat>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1, align 8
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x bfloat>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1, align 16
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055698790beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556987908e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055698790c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05d2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05d218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05d2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05d211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569878a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569878a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569878868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556987535e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556987535b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05d211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05d211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05d211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556987535a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (3600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b98c2e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b98c2e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b98c2e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb61933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb6198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb61933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb6191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b98c279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b98c279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b98c25e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b98bf0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b98bf0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb6191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb6191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb6191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b98bf0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (3601 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7aed66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7aed63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7aed6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c01a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c01aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c01a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c01a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7aecfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7aecfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7aece18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7ae990e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7ae990b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c01a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c01a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c01a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7ae990a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (3602 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d944c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d944bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d944c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c2f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c2f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c2f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c2f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d94456bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d94456a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d9443b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d940eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d940eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c2f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c2f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c2f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d940eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (3603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fc21d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561fc21d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561fc21d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ceda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cedaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ceda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ceda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fc2169bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561fc2169a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561fc214e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561fc1dfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561fc1dfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ceda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ceda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ceda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fc1dfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (3611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565197046eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565197043e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056519704762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff525a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff525aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff525a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff525a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565196fdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565196fdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565196fc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565196c70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565196c70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff525a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff525a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff525a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565196c70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (3614 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a0d13beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a0d138e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a0d13c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a0d0d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a0d0d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a0d0b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a0cd65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a0cd65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a0cd65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (3618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e90358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e90355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e9035962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a89849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a89849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a89831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e902eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e902eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e902d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e8ff82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e8ff82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a89832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a898330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e8ff82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (3620 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c43c549eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c43c546e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c43c54a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aa0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aa098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aa0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aa091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c43c4dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c43c4dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c43c4c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c43c173e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c43c173b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aa091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aa091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aa091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c43c173a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (3631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562eb468deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562eb468ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562eb468e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562eb4623bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562eb4623a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562eb46088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562eb42b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562eb42b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f093c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562eb42b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (3632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c75fb40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c75fb3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c75fb4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba39e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba39ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba39e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba39e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c75fad6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c75fad6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c75fabb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c75f76ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c75f76ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba39e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba39e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba39e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c75f76aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (3633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610f3dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610f3dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610f3dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb826305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb82635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb826305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8262ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610f3d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610f3d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610f3d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610f39f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610f39f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8262eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8262ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8262ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610f39f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (3640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ae4e2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ae4e29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ae4e2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e72449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e72449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e72431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ae4dc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ae4dc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ae4da78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ae4a56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ae4a56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e72432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ae4a56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (3646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae26802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae267ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae2680362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadc9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadc90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadc9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadc9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae26798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae26798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae2677d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae2642ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae2642cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadc9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadc90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadc90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae2642ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (3647 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f2657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567f2654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567f265862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc98c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc98c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc98c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc98c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f25edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567f25eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567f25d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567f2281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567f2281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc98c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc98c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc98c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f2281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (3649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6cf0d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6cf0d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6cf0d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f485a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f485a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f485a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f485a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6cf06bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6cf06ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6cf0508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6cecffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6cecffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f485a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f485a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f485a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6cecffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (3653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe9d1ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe9d1cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe9d1cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa225b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa225b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa225b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa225b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe9d164bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe9d164a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe9d1498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe9cdf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe9cdf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa225b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa225b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa225b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe9cdf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (3656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebff53feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebff53ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebff54062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb092b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb092b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb092b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb092b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebff4d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebff4d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebff4ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebff169e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebff169b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb092b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb092b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb092b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebff169a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (3657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383f3ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056383f3e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056383f3ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1a1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1a1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1a1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1a1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383f381bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056383f381a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056383f3668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056383f015e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056383f015b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1a1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1a1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1a1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056383f015a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (3660 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync
# | ...
# `---data was truncated (10240/183423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ef0eadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ef0eaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ef0eae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcc4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcc478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcc4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcc471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ef0e43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ef0e43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ef0e288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ef0ad7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ef0ad7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcc471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcc471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcc471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ef0ad7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (3662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055575e009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055575e006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055575e00a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22a5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22a595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22a5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22a58ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055575df9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055575df9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055575df848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055575dc33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055575dc33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22a58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22a58ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22a58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055575dc33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (3668 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564593eaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564593ea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564593ead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8845505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f884555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8845505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88454ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564593e42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564593e42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564593e278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564593ad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564593ad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88454eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88454ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88454ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564593ad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (3669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571989a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571989a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571989a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e17449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e17449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e17431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055719893cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055719893ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571989218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571985d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571985d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e17432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571985d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (3671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0ea72ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0ea729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0ea72d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1f051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0ea6c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0ea6c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0ea6a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0ea356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0ea356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1f051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0ea356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/arm64_vcreate.c (3679 of 27910)
******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca i64, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store i64 %a1, ptr %a1.addr, align 8
# |   %0 = load i64, ptr %a1.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <2 x float>, ptr %__promote, align 8
# |   store <2 x float> %1, ptr %__ret, align 8
# |   %2 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %2, ptr %tmp, align 8
# |   %3 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff92a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ff92a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ff92a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e16133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e1618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e16133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e1611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff923bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ff923ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ff92208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ff8ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ff8ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e1611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e1611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e1611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff8ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (3687 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 16
# |   %__s0_827 = alloca <4 x i32>, align 16
# |   %__s1_827 = alloca <16 x i8>, align 16
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp2 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_827, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1_827, align 16
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 16
# |   %4 = load <16 x i8>, ptr %__s1_827, align 16
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__
# | ...
# `---data was truncated (10240/29862) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x0000559a96bb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a96bafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a96bb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff71bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff71bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff71bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff71bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a96b48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a96b48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a96b2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a967dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a967dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff71bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff71bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff71bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a967dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (3689 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ee2ef8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ee2ef5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ee2ef962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff21ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff21ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff21ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff21ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ee2e8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ee2e8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ee2e738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ee2b22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ee2b22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff21ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff21ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff21ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ee2b22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (3692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca49770eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca4976de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca4977162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a5b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca49706bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca49706a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca496eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca4939ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca4939ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a5b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca4939aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (3697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598171ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598171dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598171de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f286c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f286c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f286c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f286c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559817173bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559817173a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598171588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559816e07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559816e07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f286c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f286c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f286c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559816e07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (3703 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon   -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_790 = alloca <4 x i16>, align 8
# |   %__s0_790 = alloca <4 x i16>, align 8
# |   %__s1_790 = alloca <4 x i16>, align 8
# |   %__s2_790 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_790, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_790, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_790, align 16
# |   %3 = load <4 x i16>, ptr %__s0_790, align 8
# |   %4 = load <4 x i16>, ptr %__s1_790, align 8
# |   %5 = load <8 x i16>, ptr %__s2_790, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_790, align 8
# |   %16 = load <4 x i16>, ptr %__ret_790, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_788 = alloca <2 x i32>, align 8
# |   %__s0_788 = alloca <2 x i32>, align 8
# |   %__s1_788 = alloca <2 x i32>, align 8
# |   %__s2_788 = alloca <4 x i32>, align 16
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_788, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_788, align 8
# |   %2 = load <4 x i32>, ptr %v.addr, align 16
# |   store <4 x i32> %2, ptr %__s2_788, align 16
# |   %3 = load <2 x i32>, ptr %__s0_788, align 8
# |   %4 = load <2 x i32>, ptr %__s1_788, align 8
# |   %5 = load <4 x i32>, ptr %__s2_788, align 16
# |   store <4 x i32> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x i32>
# |   %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> <i32 3, i32 3>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %14 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %14, ptr %__ret.i, align 8
# |   %15 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %15, ptr %__ret_788, align 8
# |   %16 = load <2 x i32>, ptr %__ret_788, align 8
# |   store <2 x i32> %16, ptr %tmp1, align 8
# |   %17 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_786 = alloca <8 x i16>, align 16
# |   %__s0_786 = alloca <8 x i16>, align 16
# |   %__s1_786 = alloca <8 x i16>, align 16
# |   %__s2_786 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_786, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_786, align 16
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_786, align 16
# |   %3 = load <8 x i16>, ptr %__s0_786, align 16
# |   %4 = load <8 x i16>, ptr %__s1_786, align 16
# |   %5 = load <8 x i16>, ptr %__s2_786, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   store <8 x i16> %3, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %4, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %10, ptr %__p2.addr.i, align 16
# |   %11 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %14 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %15, ptr %__ret_786, align 16
# |   %16 = load <8 x i16>, ptr %__ret_786, align 16
# |   store <8 x i16> %16, ptr %tmp1, align 16
# |   %17 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_784 = alloca <4 x i32>, align 16
# |   %__s0_784 = alloca <4 x i32>, align 16
# |   %__s1_784 = alloca <4 x i32>, align 16
# |   %__s2_784 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <4
# | ...
# `---data was truncated (10240/50621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000055e4c989eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4c989be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4c989f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7adf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7adf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7adf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7adf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4c9834bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4c9834a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4c98198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4c94c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4c94c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7adf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7adf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7adf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4c94c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (3707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8f561aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8f5617e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8f561b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8b2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8b298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8b2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8b291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8f55b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8f55b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8f55958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8f5244e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8f5244b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8b291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8b291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8b291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8f5244a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (3712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ee1b38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ee1b35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ee1b3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabef305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabef35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabef305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabef2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ee1acebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ee1acea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ee1ab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ee1762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ee1762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabef2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabef2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabef2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ee1762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (3714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd4830eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cd482de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cd483162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa26c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa26c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa26c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa26c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd47c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cd47c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cd47ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cd445ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cd445ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa26c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa26c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa26c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd445aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (3720 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d5ea4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d5ea4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d5ea4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc512733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc51278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc512733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc51271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d5e9e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d5e9e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d5e9c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d5e678e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d5e678b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc51271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc51271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc51271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d5e678a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (3722 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590e8d41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590e8d3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590e8d4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9573b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9573b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9573b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9573b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590e8cd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590e8cd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590e8cbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590e896be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590e896bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9573b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9573b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9573b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590e896ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (3725 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = c
# | ...
# `---data was truncated (10240/207083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644ab186eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644ab183e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644ab18762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1fe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1fe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1fe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1fe31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644ab11cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644ab11ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644ab1018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644aadb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644aadb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1fe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1fe31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1fe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644aadb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon-extract.c (3731 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
# |   store <8 x i8> %vext, ptr %ref.tmp, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %4, ptr %__ret, align 8
# |   %5 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %5, ptr %tmp, align 8
# |   %6 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   %5 = bitcast <8 x i8> %3 to <4 x i16>
# |   %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
# |   store <4 x i16> %vext, ptr %ref.tmp, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %6, ptr %__ret, align 8
# |   %7 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %7, ptr %tmp, align 8
# |   %8 = load <4 x i16>, ptr %tmp, align 8
# |   ret <4 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %__s1 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <2 x i32>
# |   %5 = bitcast <8 x i8> %3 to <2 x i32>
# |   %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i32> %vext, ptr %ref.tmp, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %6, ptr %__ret, align 8
# |   %7 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %7, ptr %tmp, align 8
# |   %8 = load <2 x i32>, ptr %tmp, align 8
# |   ret <2 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer
# |   store <1 x i64> %vext, ptr %ref.tmp, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %6, ptr %__ret, align 8
# |   %7 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %7, ptr %tmp, align 8
# |   %8 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca <16 x i8>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
# |   store <16 x i8> %vext, ptr %ref.tmp, align 16
# |   %4 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %4, ptr %__ret, align 16
# |   %5 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %5, ptr %tmp, align 16
# |   %6 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x i16>
# |   %5 = bitcast <16 x i8> %3 to <8 x i16>
# |   %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
# |   store <8 x i16> %vext, ptr %ref.tmp, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %6, ptr %__ret, align 16
# |   %7 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %7, ptr %tmp, align 16
# |   %8 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <4 x i32>
# |   %5 = bitcast <16 x i8> %3 to <4 x i32>
# |   %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
# |   store <4 x i32> %vext, ptr %ref.tmp, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %6, ptr %__ret, align 16
# |   %7 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %7, ptr %tmp, align 16
# |   %8 = load <4 x i32>, ptr %tmp, align 16
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i64> %vext, ptr %ref.tmp, align 16
# |   %6 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %6, ptr %__ret, align 16
# |   %7 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %7, ptr %tmp, align 16
# |   %8 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8>
# | ...
# `---data was truncated (10240/29598) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f2d0ffceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2d0ff9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2d0ffd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6882d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6882d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6882d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6882d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2d0f92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2d0f92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2d0f778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2d0c26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2d0c26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6882d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6882d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6882d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2d0c26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (3737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650b9ef6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650b9ef3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650b9ef762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9730f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9730f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9730f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9730f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650b9e8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650b9e8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650b9e718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650b9b20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650b9b20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9730f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9730f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9730f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650b9b20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (3753 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaab390eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaab38de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaab39162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92dd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92dd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92dd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92dd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaab326bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaab326a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaab30b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaaafbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaaafbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92dd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92dd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92dd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaaafbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (3754 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vsqaddb_u8() #0 {
# | entry:
# |   %__p0.addr.i = alloca i8, align 1
# |   %__p1.addr.i = alloca i8, align 1
# |   %__ret.i = alloca i8, align 1
# |   %ref.tmp.i = alloca i8, align 1
# |   store i8 1, ptr %__p0.addr.i, align 1
# |   store i8 -1, ptr %__p1.addr.i, align 1
# |   %0 = load i8, ptr %__p0.addr.i, align 1
# |   %1 = load i8, ptr %__p1.addr.i, align 1
# |   %2 = insertelement <8 x i8> poison, i8 %0, i64 0
# |   %3 = insertelement <8 x i8> poison, i8 %1, i64 0
# |   %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3)
# |   %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0
# |   store i8 %4, ptr %ref.tmp.i, align 1
# |   %5 = load i8, ptr %ref.tmp.i, align 1
# |   store i8 %5, ptr %__ret.i, align 1
# |   %6 = load i8, ptr %__ret.i, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vsqaddh_u16() #0 {
# | entry:
# |   %__p0.addr.i = alloca i16, align 2
# |   %__p1.addr.i = alloca i16, align 2
# |   %__ret.i = alloca i16, align 2
# |   %ref.tmp.i = alloca i16, align 2
# |   store i16 1, ptr %__p0.addr.i, align 2
# |   store i16 -1, ptr %__p1.addr.i, align 2
# |   %0 = load i16, ptr %__p0.addr.i, align 2
# |   %1 = load i16, ptr %__p1.addr.i, align 2
# |   %2 = insertelement <4 x i16> poison, i16 %0, i64 0
# |   %3 = insertelement <4 x i16> poison, i16 %1, i64 0
# |   %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3)
# |   %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0
# |   store i16 %4, ptr %ref.tmp.i, align 2
# |   %5 = load i16, ptr %ref.tmp.i, align 2
# |   store i16 %5, ptr %__ret.i, align 2
# |   %6 = load i16, ptr %__ret.i, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vsqadds_u32() #0 {
# | entry:
# |   %__p0.addr.i = alloca i32, align 4
# |   %__p1.addr.i = alloca i32, align 4
# |   %__ret.i = alloca i32, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   store i32 1, ptr %__p0.addr.i, align 4
# |   store i32 -1, ptr %__p1.addr.i, align 4
# |   %0 = load i32, ptr %__p0.addr.i, align 4
# |   %1 = load i32, ptr %__p1.addr.i, align 4
# |   %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1)
# |   store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4
# |   %2 = load i32, ptr %ref.tmp.i, align 4
# |   store i32 %2, ptr %__ret.i, align 4
# |   %3 = load i32, ptr %__ret.i, align 4
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vsqaddd_u64() #0 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i64, align 8
# |   %ref.tmp.i = alloca i64, align 8
# |   store i64 1, ptr %__p0.addr.i, align 8
# |   store i64 -1, ptr %__p1.addr.i, align 8
# |   %0 = load i64, ptr %__p0.addr.i, align 8
# |   %1 = load i64, ptr %__p1.addr.i, align 8
# |   %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1)
# |   store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8
# |   %2 = load i64, ptr %ref.tmp.i, align 8
# |   store i64 %2, ptr %__ret.i, align 8
# |   %3 = load i64, ptr %__ret.i, align 8
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# |  #0 0x000055868d584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055868d581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055868d58562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb00da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb00daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb00da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb00da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055868d51abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055868d51aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055868d4ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055868d1aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055868d1aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb00da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb00da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb00da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055868d1aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon/widen.c (3757 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = sext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = sext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = sext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = zext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = zext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = zext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i1 = alloca <8 x i8>, align 8
# |   %__p0_561.addr.i = alloca <16 x i8>, align 16
# |   %__ret_561.i = alloca <8 x i16>, align 16
# |   %__a1_561.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %__s0.i = alloca <8 x i8>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0_561.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i1, align 8
# |   store <8 x i8> %4, ptr %__a1_561.i, align 8
# |   %5 = load <8 x i8>, ptr %__a1_561.i, align 8
# |   store <8 x i8> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = sext <8 x i8> %6 to <8 x i16>
# |   store <8 x i16> %7, ptr %ref.tmp1.i, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16
# |   store <8 x i16> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %9, ptr %tmp.i, align 16
# |   %10 = load <8 x i16>, ptr %tmp.i, align 16
# |   store <8 x i16> %10, ptr %ref.tmp.i, align 16
# |   %11 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %11, ptr %__ret_561.i, align 16
# |   %12 = load <8 x i16>, ptr %__ret_561.i, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i1 = alloca <4 x i16>, align 8
# |   %__p0_567.addr.i = alloca <8 x i16>, align 16
# |   %__ret_567.i = alloca <4 x i32>, align 16
# |   %__a1_567.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0_567.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i1, align 8
# |   store <4 x i16> %4, ptr %__a1_567.i, align 8
# |   %5 = load <4 x i16>, ptr %__a1_567.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = sext <4 x i16> %7 to <4 x i32>
# |   store <4 x i32> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %12, ptr %__ret_567.i, align 16
# |   %13 = load <4 x i32>, ptr %__ret_567.i, align 16
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i1 = alloca <2 x i32>, align 8
# |   %__p0_564.addr.i = alloca <4 x i32>, align 16
# |   %__ret_564.i = alloca <2 x i64>, align 16
# |   %__a1_564.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %__s0.i = alloca <2 x i32>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0_564.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i1, align 8
# |   store <2 x i32> %4, ptr %__a1_564.i, align 8
# |   %5 = load <2 x i32>, ptr %__a1_564.i, align 8
# |   store <2 x i32> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %8 = sext <2 x i32> %7 to <2 x i64>
# |   store <2 x i64> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16
# |   store <2 x i64> %9, ptr %__ret.i, align 16
# |   %10 = load <2 x i64>, ptr %__ret.i, align 16
# |   store <2 x i64> %10, ptr %tmp.i, align 16
# |   %11 = load <2 x i64>, ptr %tmp.i, align 16
# |   store <2 x i64> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <2 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005577d1a6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577d1a68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577d1a6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff607a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff607a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff607a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff607a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577d1a01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577d1a01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577d19e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577d1695e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577d1695b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff607a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff607a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff607a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577d1695a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (3758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9705deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9705dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9705df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbae6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbae695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbae6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbae68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f970574bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f970574a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9705598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f970208e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f970208b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbae68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbae68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbae68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f970208a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (3759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d71bb99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d71bb96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d71bb9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbb6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbb618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbb6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbb611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d71bb2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d71bb2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d71bb148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d71b7c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d71b7c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbb611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbb611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbb611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d71b7c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (3760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a73e9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a73e98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a73e9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e3aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e3aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e3aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e3aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a73e31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a73e31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a73e168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a73ac5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a73ac5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e3aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e3aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e3aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a73ac5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (3762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec49ee3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec49ee0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec49ee462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0250449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0250449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0250431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec49e79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec49e79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec49e5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec49b0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec49b0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0250432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec49b0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (3764 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa4cc59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa4cc56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa4cc5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc36f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc36f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc36f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc36f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa4cbefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa4cbefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa4cbd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa4c883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa4c883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc36f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc36f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc36f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa4c883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (3768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5eb20beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5eb208e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5eb20c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f948a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f948a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f948a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f948a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5eb1a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5eb1a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5eb1868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5eae35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5eae35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f948a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f948a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f948a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5eae35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (3770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a73160eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a7315de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a7316162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0eb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0eb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0eb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0eb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a730f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a730f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a730db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a72d8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a72d8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0eb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0eb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0eb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a72d8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (3771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588f2ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588f2ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588f2ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ca6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ca64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ca6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ca6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588f2e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588f2e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588f2e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588f2aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588f2aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ca6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ca64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ca64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588f2aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (3774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %
# | ...
# `---data was truncated (10240/201226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559aa8ddfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559aa8ddce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559aa8de062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1391849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1391849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1391831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559aa8d75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559aa8d75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559aa8d5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559aa8a09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559aa8a09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1391832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559aa8a09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (3777 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %5 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %5, ptr %__ret, align 8
# |   %6 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %6, ptr %tmp, align 8
# |   %7 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %9 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_39 = alloca <4 x half>, align 8
# |   %__s0_39 = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_39, align 8
# |   %1 = load <4 x half>, ptr %__s0_39, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_39, align 8
# |   %7 = load <4 x half>, ptr %__ret_39, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_20 = alloca <8 x half>, align 16
# |   %__s0_20 = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_20, align 8
# |   %1 = load <4 x half>, ptr %__s0_20, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_20, align 16
# |   %7 = load <8 x half>, ptr %__ret_20, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_432 = alloca <4 x half>, align 8
# |   %__s0_432 = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_432, align 16
# |   %1 = load <8 x half>, ptr %__s0_432, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_432, align 8
# |   %7 = load <4 x half>, ptr %__ret_432, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_408 = alloca <8 x half>, align 16
# |   %__s0_408 = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_408, align 16
# |   %1 = load <8 x half>, ptr %__s0_408, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_408, align 16
# |   %7 = load <8 x half>, ptr %__ret_408, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <4 x half>, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <4 x half> %vec, ptr %vec.addr, align 8
# |   %0 = load <4 x half>, ptr %vec.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x half> %1, i32 3
# |   store half %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <8 x half>, align 16
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <8 x half> %vec, ptr %vec.addr, align 16
# |   %0 = load <8 x half>, ptr %vec.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x half> %1, i32 7
# |   store half %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-s
# | ...
# `---data was truncated (10240/10414) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d47a1feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d47a1fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d47a1ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f485061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48506725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f485061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4850603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d47a194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d47a194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d47a1798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d479e28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d479e28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4850604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48506050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48506050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d479e28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (3779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2a7c88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2a7c85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2a7c8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16d931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2a7c1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2a7c1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2a7c038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2a78b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2a78b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16d931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2a78b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (3783 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr =
# | ...
# `---data was truncated (10240/154509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6496eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6496ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6496ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8daee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8daeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8daee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8daee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b649684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b649684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6496698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b649318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b649318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8daee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8daee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8daee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b649318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (3787 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f68556eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f68553e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f6855762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f684ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f684eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f684d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f68180e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f68180b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f68180a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (3794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618fb28feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618fb28ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618fb29062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa498533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa49858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa498533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa49851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618fb225bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618fb225a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618fb20a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618faeb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618faeb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa49851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa49851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa49851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618faeb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (3796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eee1aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561eee1a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561eee1ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9087049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90870a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9087049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9087031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eee142bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561eee142a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561eee1278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561eeddd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561eeddd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9087032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90870330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90870330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eeddd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (3801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x
# | ...
# `---data was truncated (10240/164783) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b0796eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632b0793e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632b079762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6af11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b072cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632b072ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632b07118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632b03c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632b03c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6af11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b03c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (3809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563b48a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563b48a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563b48a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad45b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad45b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad45b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad45aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563b483ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563b483ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563b48238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563b44d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563b44d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad45aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad45aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad45aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563b44d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (3814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, al
# | ...
# `---data was truncated (10240/223137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565173781eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056517377ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056517378262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53fbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565173717bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565173717a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651736fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651733abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651733abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53fbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651733aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (3818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/210435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563b21c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563b21c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563b21c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8af2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8af218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8af2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8af211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563b215cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563b215ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563b21418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563b1df0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563b1df0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8af211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8af211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8af211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563b1df0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (3822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8985deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8985dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8985df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc9bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc9bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a898574bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a898574a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8985598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a898208e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a898208b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc9bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a898208a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (3824 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4dd7b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4dd7b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4dd7b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e7ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e7ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e7ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e7ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4dd749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4dd749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4dd72e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4dd3dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4dd3ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e7ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e7ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e7ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4dd3dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (3827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ba2fafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ba2face85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ba2fb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f354ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f354eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f354ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f354ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ba2f45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ba2f45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ba2f2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ba2bd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ba2bd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f354ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f354ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f354ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ba2bd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (3828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1300c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1300bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1300c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a130057bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a130057a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a13003c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a12fcebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a12fcebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06a5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a12fceba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (3834 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b58dc11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b58dc0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b58dc1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7a3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7a32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7a3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7a3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b58dba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b58dba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b58db8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b58d83be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b58d83bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7a3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7a32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7a32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b58d83ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (3835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec9543eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bec9540e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bec954462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f305c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f305c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f305c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f305c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec94d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bec94d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bec94be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bec916de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bec916db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f305c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f305c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f305c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec916da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (3836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c648e31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c648e2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c648e3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac59f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac59f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac59f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac59f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c648dc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c648dc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c648dac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c648a5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c648a5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac59f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac59f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac59f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c648a5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (3841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, a
# | ...
# `---data was truncated (10240/98437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a0c344eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a0c341e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a0c34562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f102a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f102a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f102a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f102a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a0c2dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a0c2daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a0c2bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a0bf6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a0bf6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f102a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f102a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f102a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a0bf6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (3842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4898f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4898ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4898f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8f1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8f1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8f1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8f1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b489886bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b489886a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b48986b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b48951ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b48951ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8f1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8f1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8f1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b48951aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (3843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd1585eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd1585be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd1585f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab86849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab868a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab86849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab86831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd157f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd157f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd157d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd15488e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd15488b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab86832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab868330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab868330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd15488a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (3848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056465b73ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056465b739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056465b73d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8ceb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8ceb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8ceb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8ceb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056465b6d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056465b6d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056465b6b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056465b366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056465b366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8ceb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8ceb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8ceb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056465b366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (3850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @test_vlenb() #0 {
# | entry:
# |   %0 = call i32 @llvm.read_register.i32(metadata !4)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.read_register.i32(metadata) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"vlenb"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x000055cbb40c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbb40c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbb40c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa451c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa451ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa451c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa451c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbb405abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbb405aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbb403f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbb3ceee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbb3ceeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa451c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa451c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa451c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbb3ceea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (3851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b916e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b916e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b916e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6a9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6a995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6a9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6a98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b916df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b916df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b916ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b916a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b916a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6a98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6a98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6a98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b916a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (3854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055622cb20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055622cb1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055622cb2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc107133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc10718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc107133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc10711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055622cab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055622cab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055622ca9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055622c74ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055622c74ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc10711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc10711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc10711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055622c74aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (3857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso
# | ...
# `---data was truncated (10240/148012) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e094f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e094f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e094f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb323933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb32398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb323933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb32391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e0948abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e0948aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e0946f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e0911ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e0911eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb32391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb32391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb32391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e0911ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (3860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590a8ac5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590a8ac2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590a8ac662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f556c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f556c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f556c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f556c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590a8a5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590a8a5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590a8a408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590a86efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590a86efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f556c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f556c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f556c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590a86efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (3861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 4 x 
# | ...
# `---data was truncated (10240/142016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fecada9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fecada6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fecadaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe95e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe95e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe95e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe95e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fecad3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fecad3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fecad248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feca9d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feca9d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe95e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe95e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe95e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feca9d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (3871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648a6081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648a607ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648a608262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6999733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6999733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648a6017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648a6017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648a5ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648a5cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648a5cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648a5caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (3872 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b08672eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b0866fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b0867362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6798133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f679818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6798133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f679811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b08608bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b08608a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b085ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b0829ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b0829cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f679811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f679811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f679811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b0829ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (3873 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056023bf13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056023bf10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056023bf1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdef3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdef3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdef3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdef3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056023bea9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056023bea9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056023be8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056023bb3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056023bb3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdef3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdef3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdef3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056023bb3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (3874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b6bef7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b6bef4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b6bef862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcb1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcb1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcb1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcb1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b6be8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b6be8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b6be728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b6bb21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b6bb21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcb1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcb1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcb1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b6bb21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (3879 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654ffe85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654ffe82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654ffe8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc73505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc7355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc73505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc734ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654ffe1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654ffe1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654ffe008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654ffaafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654ffaafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc734eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc734ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc734ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654ffaafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (3889 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c34056eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c34053e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c3405762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a00449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a00449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a00431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c33fecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c33feca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c33fd18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c33c80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c33c80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a00432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a004330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c33c80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (3891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ca6845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ca6842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ca684662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4dcf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4dcf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4dcf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4dceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ca67dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ca67dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ca67c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ca646fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ca646fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4dceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4dceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4dceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ca646fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (3895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7ddb29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7ddb26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7ddb2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f974dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f974dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7ddabfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7ddabfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7ddaa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7dd753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7dd753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f974dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7dd753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (3898 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a4debeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a4debbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a4debf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a4de54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a4de54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a4de398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a4dae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a4dae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a4dae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (3899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i6
# | ...
# `---data was truncated (10240/182165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579b950ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579b9509e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579b950d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f873aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f873aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f873aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f873aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579b94a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579b94a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579b94878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579b9136e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579b9136b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f873aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f873aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f873aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579b9136a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (3900 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0683beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea06838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea0683c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16c2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16c24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16c2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16c2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea067d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea067d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea067b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea06465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea06465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16c2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16c24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16c24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea06465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (3901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd2514ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd25149e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd2514d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ff4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ff44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ff4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ff4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd250e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd250e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd250c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd24d76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd24d76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ff4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ff44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ff44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd24d76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (3902 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/201234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580e4329eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580e4326e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580e432a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580e42bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580e42bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580e42a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580e3f53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580e3f53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580e3f53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (3904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofre
# | ...
# `---data was truncated (10240/183431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598486c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598486bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598486c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe90f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe90f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe90f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe90f203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559848656bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559848656a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055984863b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598482eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598482eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe90f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe90f2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe90f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598482eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (3905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e75aef1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e75aeeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e75aef262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde3fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde3fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde3fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde3fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e75ae87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e75ae87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e75ae6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e75ab1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e75ab1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde3fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde3fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde3fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e75ab1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (3910 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0a3f54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0a3f51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0a3f5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb6af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb6af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb6af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb6af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0a3eeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0a3eeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0a3ecf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0a3b7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0a3b7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb6af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb6af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb6af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0a3b7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (3911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fe26e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fe26dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fe26e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dbf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dbf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dbf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dbf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fe2678bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fe2678a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fe265d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fe230ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fe230cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1dbf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dbf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dbf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fe230ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (3912 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/223809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582fd5c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582fd5c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582fd5c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6265133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f626518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6265133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f626511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582fd55abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582fd55aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582fd53f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582fd1eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582fd1eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f626511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f626511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f626511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582fd1eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (3915 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <8 x half>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <4 x float>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ddb856aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddb8567e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddb856b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94be231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddb8500bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddb8500a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddb84e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddb8194e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddb8194b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94be2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddb8194a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (3916 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563d6c15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563d6c12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563d6c1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb610305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb61035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb610305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6102ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563d6babbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563d6baba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563d6b908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563d683fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563d683fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6102eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6102ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6102ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563d683fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (3919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564877578eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564877575e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056487757962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f7ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f7cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f7ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f7ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056487750ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056487750ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648774f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648771a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648771a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f7ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f7ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f7ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648771a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (3922 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561efebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561efeb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561efebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7028249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70282a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7028249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7028231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561efe51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561efe51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561efe368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561efae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561efae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7028232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70282330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70282330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561efae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (3923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056358d81beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056358d818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056358d81c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc130133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc13018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc130133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc13011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056358d7b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056358d7b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056358d7968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056358d445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056358d445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc13011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc13011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc13011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056358d445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (3926 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/153905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595fab20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595fab1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595fab2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd156249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1562a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd156249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd156231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595faab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595faab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595faa9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595fa74ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595fa74ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd156232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1562330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1562330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595fa74aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (3928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/124506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0b7d77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0b7d74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0b7d7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff02b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff02b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff02b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff02b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0b7d0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0b7d0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0b7cf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0b79a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0b79a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff02b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff02b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff02b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0b79a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (3930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622374f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622374ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622374f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae66505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae6655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae66505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae664ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562237486bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562237486a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056223746b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056223711ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056223711ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae664eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae664ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae664ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056223711aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (3932 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu
# | ...
# `---data was truncated (10240/156765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f772afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f772ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f772b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f391cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f391cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f391cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f391cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f77245bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f77245a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f7722a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f76ed9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f76ed9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f391cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f391cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f391cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f76ed9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (3936 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4178baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4178b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4178bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a417850bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a417850a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4178358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4174e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4174e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4174e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (3938 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0652e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0652e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0652e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3610505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f361055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3610505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36104ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d06527cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d06527ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0652618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d064f10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d064f10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36104eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36104ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36104ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d064f10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (3947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558714bfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558714bfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558714bfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7330c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7330ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7330c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7330c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558714b93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558714b93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558714b788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558714827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558714827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7330c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7330c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7330c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558714827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (3948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv
# | ...
# `---data was truncated (10240/165238) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a784a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a784a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a784aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff76bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff76bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff76bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff76bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a7843fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a7843fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a784248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a780d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a780d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff76bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff76bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff76bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a780d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (3949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555844333eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555844330e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055584433462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35b7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35b7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35b7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35b7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558442c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558442c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558442ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555843f5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555843f5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35b7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35b7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35b7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555843f5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (3951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale 
# | ...
# `---data was truncated (10240/215486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7d7cb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7d7cb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7d7cb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc278449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc278449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc278431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7d7c4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7d7c4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7d7c338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7d78e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7d78e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc278432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2784330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7d78e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (3956 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fafdbc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fafdbc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fafdbca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f9de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f9dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f9de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f9de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fafdb5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fafdb5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fafdb448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fafd7f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fafd7f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f9de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f9de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f9de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fafd7f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (3959 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <v
# | ...
# `---data was truncated (10240/157467) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a29772eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a2976fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a2977362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa352333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa35238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa352333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa35231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a29708bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a29708a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a296ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a2939ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a2939cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa35231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa35231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa35231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a2939ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (3964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b83170deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b83170ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b83170e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b41133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b41133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8316a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8316a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8316888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b831337e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b831337b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b4111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b831337a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (3973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589671cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589671c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589671cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ac8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ac838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ac8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ac831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558967161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558967161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589671468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558966df5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558966df5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ac831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ac831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ac831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558966df5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (3977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056076ab46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056076ab43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056076ab4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ed5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ed598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ed5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ed591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056076aadcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056076aadca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056076aac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056076a770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056076a770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ed591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ed591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ed591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056076a770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (3978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd1f08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddd1f05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddd1f0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4824449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4824449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4824431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd1e9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddd1e9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddd1e838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddd1b32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddd1b32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4824432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48244330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd1b32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (3983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559571215eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559571212e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055957121662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99dc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99dc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99dc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99dc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595711abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595711aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595711908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559570e3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559570e3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99dc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99dc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99dc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559570e3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (3984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, pt
# | ...
# `---data was truncated (10240/174721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651fdd39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651fdd36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651fdd3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3454e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3454ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3454e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3454e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651fdccfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651fdccfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651fdcb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651fd963e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651fd963b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3454e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3454e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3454e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651fd963a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (3987 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560205a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560205a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560205a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d48133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d4818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d48133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d4811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055602053abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055602053aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055602051f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560201cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560201ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d4811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d4811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d4811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560201cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (3988 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8de93deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8de93ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8de93e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63a1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63a1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63a1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63a1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8de8d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8de8d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8de8b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8de567e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8de567b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63a1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63a1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63a1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8de567a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (4000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a32deceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a32de9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a32ded62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a32d82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a32d82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a32d678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a32a16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a32a16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a32a16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (4001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd27bb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd27bade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd27bb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94a2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94a22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94a2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94a2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd27b46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd27b46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd27b2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd277dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd277dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94a2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94a22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94a22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd277daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (4002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/151245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16043eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c16043be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c16043f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5167e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5167ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5167e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5167e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1603d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1603d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1603b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c160068e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c160068b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5167e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5167e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5167e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c160068a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (4007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055648cd43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055648cd40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055648cd4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6852b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6852b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6852b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6852b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055648ccd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055648ccd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055648ccbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055648c96de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055648c96db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6852b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6852b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6852b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055648c96da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (4013 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648ce688eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648ce685e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648ce68962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f711be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f711be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f711be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f711be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648ce61ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648ce61ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648ce6038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648ce2b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648ce2b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f711be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f711be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f711be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648ce2b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (4015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b21457ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b214579e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b21457d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe91d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe91d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe91d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe91d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b214512bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b214512a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2144f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2141a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2141a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe91d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe91d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe91d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2141a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (4017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592a2e0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592a2e0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592a2e0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e26b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e26b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e26b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e26b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592a2da4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592a2da4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592a2d898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592a2a38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592a2a38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e26b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e26b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e26b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592a2a38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (4018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fc0340eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fc033de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fc034162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcbd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcbd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcbd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcbd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fc02d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fc02d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fc02bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fbff6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fbff6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcbd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcbd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcbd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fbff6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (4019 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dac73e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dac73e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dac73e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8b0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dac7379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dac7379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dac735e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dac700de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dac700db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dac700da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (4025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ea971aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ea9717e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ea971b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e19049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e190a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e19049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e19031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ea96b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ea96b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ea96958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ea9344e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ea9344b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e19032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e190330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e190330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ea9344a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (4026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/205813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c1600beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c16008e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c1600c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6716e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6716ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6716e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6716e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c15fa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c15fa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c15f868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c15c35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c15c35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6716e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6716e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6716e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c15c35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (4036 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloc
# | ...
# `---data was truncated (10240/122004) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b20cb14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b20cb11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b20cb1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ffad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ffad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ffad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ffad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b20caaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b20caaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b20ca8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b20c73ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b20c73eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ffad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ffad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ffad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b20c73ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (4038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4316e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4316e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4316e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f813e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f813e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f813e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f813e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f43167bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f43167ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4316608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f43130fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f43130fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f813e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f813e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f813e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f43130fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (4039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d86b273eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d86b270e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d86b27462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d86b209bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d86b209a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d86b1ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d86ae9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d86ae9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a1f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d86ae9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (4041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646d7a3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646d7a38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646d7a3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc149e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc149ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc149e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc149e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646d79d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646d79d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646d79b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646d7665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646d7665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc149e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc149e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc149e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646d7665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (4042 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @foo() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @bar() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @baz(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @quux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %call = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %call
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646dc587eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646dc584e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646dc58862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f011aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f011aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f011aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f011aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646dc51dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646dc51da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646dc5028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646dc1b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646dc1b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f011aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f011aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f011aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646dc1b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (4043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <
# | ...
# `---data was truncated (10240/117389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bf240feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bf240ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bf241062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aacb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aacb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aacb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aacb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bf23a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bf23a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bf238a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bf2039e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bf2039b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aacb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aacb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aacb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bf2039a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (4047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d1f759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d1f756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1f75a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1dc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d1f6efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d1f6efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d1f6d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d1f383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d1f383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1dc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d1f383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (4051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ae868feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ae868ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ae869062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8efb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8efb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8efb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8efb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ae8625bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ae8625a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ae860a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ae82b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ae82b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8efb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8efb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8efb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ae82b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (4053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a304b8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a304b89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a304b8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9835333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f983538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9835333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f983531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a304b22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a304b22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a304b078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3047b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3047b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f983531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f983531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f983531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3047b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (4056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575226efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575226ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575226f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7840333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f784038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7840333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f784031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557522685bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557522685a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055752266a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557522319e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557522319b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f784031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f784031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f784031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557522319a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (4057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be1e36aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be1e367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be1e36b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be1e300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be1e300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be1e2e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be1df94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be1df94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be1df94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/arm-neon-vst.c (4071 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon      -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <4 x i16>
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x3_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0
# |   store [3 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %4 = bitcast <8 x i8> %1 to <4 x i16>
# |   %5 = bitcast <8 x i8> %2 to <4 x i16>
# |   %6 = bitcast <8 x i8> %3 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x4_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0
# |   store [4 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3
# |   %4 = load <8 x i8>, ptr %arrayidx6, align 8
# |   %5 = bitcast <8 x i8> %1 to <4 x i16>
# |   %6 = bitcast <8 x i8> %2 to <4 x i16>
# |   %7 = bitcast <8 x i8> %3 to <4 x i16>
# |   %8 = bitcast <8 x i8> %4 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float32x2x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <2 x float>
# |   %4 = bitcast <8 x i8> %2 to <2 x float>
# |   call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %s
# | ...
# `---data was truncated (10240/108866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e96b284eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e96b281e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e96b28562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f263ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f263ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e96b21abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e96b21aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e96b1ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e96aeaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e96aeaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f263ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e96aeaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (4073 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faf4f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faf4f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faf4f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5dd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faf4f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faf4f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faf4f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faf4bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faf4bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faf4bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (4074 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f
# | ...
# `---data was truncated (10240/165246) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0f67b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0f67b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0f67b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59f7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0f674dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0f674da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0f67328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0f63e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0f63e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0f63e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (4076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b29195eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b29192e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b2919662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd170c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd170ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd170c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd170c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b2912bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b2912ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b291108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b28dbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b28dbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd170c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd170c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd170c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b28dbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (4077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, 
# | ...
# `---data was truncated (10240/211231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1d5557eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1d5554e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1d555862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6ef133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6ef18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6ef133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6ef11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1d54edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1d54eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1d54d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1d5181e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1d5181b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6ef11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6ef11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6ef11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1d5181a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (4085 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a76bc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a76bbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a76bc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85b2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85b258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85b2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85b251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a76b57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a76b57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a76b3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a767ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a767ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85b251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85b251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85b251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a767eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (4090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, alig
# | ...
# `---data was truncated (10240/150641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b51e18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b51e15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b51e1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1196b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1196b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1196b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1196b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b51daebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b51daea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b51d938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b51a42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b51a42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1196b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1196b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1196b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b51a42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (4091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.
# | ...
# `---data was truncated (10240/164791) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563fb7c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563fb7c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563fb7c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f026a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f026a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f026a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f026a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563fb75bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563fb75ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563fb7408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563fb3efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563fb3efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f026a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f026a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f026a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563fb3efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (4093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056355f324eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056355f321e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056355f32562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff63cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff63cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff63cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff63cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056355f2babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056355f2baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056355f29f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056355ef4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056355ef4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff63cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff63cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff63cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056355ef4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (4094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f75100eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f750fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f7510162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddf8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddf8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddf8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddf8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f75096bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f75096a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f7507b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f74d2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f74d2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddf8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddf8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddf8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f74d2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (4095 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c840225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c840222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c84022662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd010305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd01035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd010305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0102ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8401bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8401bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8401a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c83fe4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c83fe4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0102eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0102ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0102ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c83fe4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (4096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3e8f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd3e8f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd3e8f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f914b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f914b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f914b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f914b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3e88bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd3e88ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd3e8708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd3e51fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd3e51fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f914b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f914b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f914b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3e51fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (4098 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055858409feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055858409ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585840a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa99c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa99c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558584035bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558584035a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055858401a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558583cc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558583cc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa99c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558583cc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (4099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618c2d9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618c2d99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618c2d9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f784d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f784d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f784d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f784d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618c2d32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618c2d32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618c2d178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618c29c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618c29c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f784d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f784d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f784d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618c29c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (4100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f194617eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f194614e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f19461862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff67941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6794725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff67941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff679403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1945adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1945ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1945928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f194241e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f194241b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff679404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6794050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6794050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f194241a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (4104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a25c74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a25c71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a25c7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4750049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47500a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4750049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4750031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a25c0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a25c0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a25bef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a2589ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a2589eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4750032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47500330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47500330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a2589ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (4106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e84c306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e84c303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e84c30762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60c8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60c82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60c8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60c8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e84c29cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e84c29ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e84c2818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e84bf30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e84bf30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60c8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60c82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60c82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e84bf30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (4111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e908c3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e908c3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e908c4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd71fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd71fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd71fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd71fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e908bd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e908bd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e908bba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e908869e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e908869b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd71fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd71fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd71fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e908869a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (4113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b634ed2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b634ecfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b634ed362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae6fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae6fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae6fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae6fc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b634e68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b634e68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b634e4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b634afce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b634afcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae6fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae6fc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae6fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b634afca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (4119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561daa161eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561daa15ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561daa16262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31acb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31acb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31acb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31acb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561daa0f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561daa0f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561daa0dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561da9d8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561da9d8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31acb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31acb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31acb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561da9d8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (4124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d88405aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d884057e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d88405b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d74c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d74ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d74c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d74c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d883ff0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d883ff0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d883fd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d883c84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d883c84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d74c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d74c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d74c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d883c84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (4125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale x 16 x 
# | ...
# `---data was truncated (10240/156463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd35b96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd35b93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd35b9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc710c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc710ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc710c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc710c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd35b2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd35b2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd35b118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd357c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd357c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc710c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc710c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc710c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd357c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (4131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645f1875eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645f1872e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645f187662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3aa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3aa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3aa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3aa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645f180bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645f180ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645f17f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645f149fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645f149fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3aa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3aa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3aa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645f149fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (4134 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056049ec01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056049ebfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056049ec0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ba9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ba9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ba9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ba9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056049eb97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056049eb97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056049eb7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056049e82be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056049e82bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ba9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ba9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ba9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056049e82ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (4135 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c07ff82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c07ff7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c07ff8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec0a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec0a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec0a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec0a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c07ff18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c07ff18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c07fefd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c07fbace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c07fbacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec0a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec0a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec0a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c07fbaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (4136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf97a0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf97a0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf97a0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1379a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1379aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1379a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1379a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf979a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf979a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf979898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf97638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf97638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1379a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1379a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1379a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf97638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (4138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d4d120eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d4d11de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d4d12162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74c591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d4d0b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d4d0b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d4d09b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d4cd4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d4cd4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74c591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d4cd4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (4139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645b905aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645b9057e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645b905b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78f601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78f60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78f601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78f6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645b8ff0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645b8ff0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645b8fd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645b8c84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645b8c84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78f6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78f60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78f60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645b8c84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (4141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504b0dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056504b0d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056504b0dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2084c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2084ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2084c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2084c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504b071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056504b071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056504b0568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056504ad05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056504ad05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2084c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2084c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2084c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504ad05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (4142 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ea9f87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ea9f84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ea9f8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8fa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8fa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8fa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8fa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ea9f1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ea9f1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ea9f028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ea9bb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ea9bb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8fa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8fa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8fa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ea9bb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (4150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/126428) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d47e2a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d47e29ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d47e2a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64eae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64eaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64eae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64eae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d47e237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d47e237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d47e21c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d47decbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d47decbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64eae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64eae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64eae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d47decba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (4154 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a1a899eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a1a896e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a1a89a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6142049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6142049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6142031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a1a82fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a1a82fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a1a8148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a1a4c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a1a4c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6142032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a1a4c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (4155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630b050eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630b050be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630b050f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4053c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4053ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4053c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4053c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630b04a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630b04a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630b04898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630b0138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630b0138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4053c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4053c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4053c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630b0138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (4156 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/246614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a63fdfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a63fdfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a63fdfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bb3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bb358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bb3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bb351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a63fd93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a63fd93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a63fd788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a63fa27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a63fa27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bb351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bb351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bb351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a63fa27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (4159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563412f33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563412f30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563412f3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563412ec9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563412ec9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563412eae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563412b5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563412b5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563412b5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (4160 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599b61b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599b61b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599b61b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1345849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13458a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1345849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1345831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599b614abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599b614aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599b612f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599b5ddee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599b5ddeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1345832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13458330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13458330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599b5ddea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (4161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561be14dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561be14dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561be14e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fe1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fe14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fe1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fe1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561be1475bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561be1475a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561be145a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561be1109e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561be1109b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fe1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fe14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fe14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561be1109a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (4162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cbfdc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cbfdc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cbfdca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef15449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef154a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef15449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef15431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cbfd5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cbfd5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cbfd448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cbf9f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cbf9f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef15432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef154330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef154330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cbf9f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (4163 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642d0206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642d0203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642d020762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8608049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8608049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8608031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642d019cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642d019ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642d01818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642cfe30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642cfe30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8608032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642cfe30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (4171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64, i64,
# | ...
# `---data was truncated (10240/120460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4c4d28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4c4d25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4c4d2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad06e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad06ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad06e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad06e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4c4cbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4c4cbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4c4ca38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4c4952e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4c4952b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad06e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad06e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad06e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4c4952a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (4179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b26e3abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b26e3a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b26e3ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc50d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc50d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc50d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc50d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b26e341bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b26e341a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b26e3268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b26dfd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b26dfd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc50d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc50d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc50d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b26dfd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (4180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a42115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a42112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a4211662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72fa81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72fa8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72fa81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72fa803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a420abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a420aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a420908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a41d3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a41d3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72fa804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72fa8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72fa8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a41d3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (4191 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056474c690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056474c68de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056474c69162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1081849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1081849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1081831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056474c626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056474c626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056474c60b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056474c2bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056474c2bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1081832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056474c2baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (4192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7c4d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b7c4cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b7c4d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa874d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa874d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa874d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa874d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7c467bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b7c467a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b7c44c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b7c0fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b7c0fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa874d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa874d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa874d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7c0fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (4193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/148020) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563be9db8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563be9db5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563be9db962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14a2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14a2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14a2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14a2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563be9d4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563be9d4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563be9d338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563be99e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563be99e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14a2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14a2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14a2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563be99e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (4197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055894eb6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055894eb6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055894eb6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15a4505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15a455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15a4505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15a44ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055894eb03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055894eb03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055894eae88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055894e797e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055894e797b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15a44eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15a44ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15a44ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055894e797a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/arm_acle_swp.c (4200 of 27910)
******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7m-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret i32 %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640fe2aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640fe2abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640fe2af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640fe244bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640fe244a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640fe2298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640fded8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640fded8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdde351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640fded8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (4207 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056331f975eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056331f972e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056331f97662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3083333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f308338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3083333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f308331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056331f90bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056331f90ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056331f8f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056331f59fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056331f59fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f308331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f308331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f308331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056331f59fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (4217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608cbae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608cbae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608cbae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b8f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608cba79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608cba79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608cba5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608cb70de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608cb70db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608cb70da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (4218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586731f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586731f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586731f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e45333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e4538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e45333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e4531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055867318bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055867318ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586731708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558672e1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558672e1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e4531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e4531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e4531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558672e1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (4225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/150951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056375f80aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056375f807e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056375f80b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd76dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd76dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd76dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd76dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056375f7a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056375f7a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056375f7858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056375f434e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056375f434b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd76dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd76dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd76dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056375f434a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (4230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae9d4afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae9d4ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae9d4b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8890d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8890d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8890d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8890d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae9d445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae9d445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae9d42a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae9d0d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae9d0d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8890d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8890d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8890d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae9d0d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (4235 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# |  #0 0x0000557f9f2cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f9f2c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f9f2cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd89ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd89ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd89ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd89ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9f262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f9f262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f9f2478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f9eef6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f9eef6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd89ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd89ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd89ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9eef6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (4238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d814331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d81432ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d81433262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dce249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dce2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dce249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dce231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8142c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8142c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8142ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d813f5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d813f5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dce232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dce2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dce2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d813f5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (4239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsa
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056313a6d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056313a6d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056313a6d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a1c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a1c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a1c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a1c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056313a66bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056313a66ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056313a6508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056313a2ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056313a2ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a1c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a1c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a1c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056313a2ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (4240 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558313bfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558313bfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558313bff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0034649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00346a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0034649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0034631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558313b94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558313b94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558313b798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558313828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558313828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0034632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00346330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00346330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558313828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (4242 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd
# | ...
# `---data was truncated (10240/215044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055883661eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055883661be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055883661f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77ed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588365b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588365b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588365998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558836248e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558836248b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558836248a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (4247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632615a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632615a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632615a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa645a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa645aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa645a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa645a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056326153ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056326153ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632615238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632611d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632611d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa645a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa645a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa645a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632611d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (4258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a2484beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a24848e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a2484c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f031b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f031b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f031b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f031b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a247e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a247e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a247c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a24475e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a24475b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f031b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f031b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f031b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a24475a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (4263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 8 x 
# | ...
# `---data was truncated (10240/124028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b56006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b56003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b5600762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3939449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39394a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3939449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3939431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b55f9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b55f9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b55f818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b55c30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b55c30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3939432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39394330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39394330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b55c30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (4265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf6634aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf66347e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf6634b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf662e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf662e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf662c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf65f74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf65f74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7f7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf65f74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (4266 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568efdbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568efdbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568efdbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb2221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb222725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb2221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb22203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568efd54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568efd54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568efd398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568ef9e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568ef9e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb22204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb222050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb222050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568ef9e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (4267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556282e2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556282e2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556282e2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556282dc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556282dc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556282da98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556282a58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556282a58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556282a58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (4279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b167149eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b167146e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b16714a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1670dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1670dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1670c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b166d73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b166d73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b166d73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (4280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c1ccafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c1ccace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c1ccb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2932d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2932d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2932d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2932d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c1cc45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c1cc45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c1cc2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c1c8d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c1c8d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2932d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2932d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2932d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c1c8d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (4284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vsc
# | ...
# `---data was truncated (10240/69951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625535bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625535b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625535bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e09933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e09933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562553551bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562553551a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625535368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625531e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625531e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625531e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (4286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577e478eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577e478be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577e478f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc09f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc09f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc09f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc09f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577e4724bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577e4724a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577e47098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577e43b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577e43b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc09f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc09f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc09f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577e43b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (4292 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582444eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582444e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582444ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2886d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2886d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2886d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2886d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558244482bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558244482a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582444678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558244116e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558244116b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2886d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2886d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2886d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558244116a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (4294 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652b920aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652b9207e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652b920b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfe0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfe0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfe0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfe0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652b91a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652b91a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652b91858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652b8e34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652b8e34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfe0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfe0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfe0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652b8e34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (4296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a29a42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a29a3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a29a4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74c3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74c3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74c3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74c3c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a299d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a299d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a299bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a2966ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a2966cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74c3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74c3c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74c3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a2966ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (4298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f00d8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f00d87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f00d8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4304133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f430418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4304133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f430411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f00d20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f00d20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f00d058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f009b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f009b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f430411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f430411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f430411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f009b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (4300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 
# | ...
# `---data was truncated (10240/126436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eb4798eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564eb4795e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564eb479962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f250f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f250f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f250f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f250f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eb472ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564eb472ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564eb47138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564eb43c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564eb43c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f250f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f250f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f250f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eb43c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (4303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0a097ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0a0979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0a097d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fcfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fcfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fcfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fcfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0a0912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0a0912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0a08f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0a05a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0a05a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fcfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fcfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fcfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0a05a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (4304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/154207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560527e5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560527e5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560527e5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd82dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd82dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd82dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd82dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560527df3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560527df3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560527dd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560527a87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560527a87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd82dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd82dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd82dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560527a87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (4305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, al
# | ...
# `---data was truncated (10240/169925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a8d48beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a8d488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a8d48c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5718849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5718849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5718831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a8d421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a8d421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a8d4068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a8d0b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a8d0b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5718832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57188330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a8d0b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (4311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a227ab1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a227aaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a227ab262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8223c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8223ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8223c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8223c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a227a47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a227a47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a227a2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2276dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2276dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8223c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8223c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8223c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2276dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (4314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmac
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564dbf56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564dbf53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564dbf5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd582f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd582f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd582f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd582f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564dbeecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564dbeeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564dbed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564dbb80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564dbb80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd582f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd582f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd582f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564dbb80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (4315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, 
# | ...
# `---data was truncated (10240/142319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b13805eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b13802e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b1380662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46b021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46b02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46b021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46b0203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b1379bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b1379ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b137808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b1342fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b1342fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46b0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46b02050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46b02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b1342fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (4321 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2adf07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2adf04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2adf0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f347ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f347cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f347ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f347ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2ade9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2ade9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2ade828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2adb31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2adb31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f347ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f347ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f347ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2adb31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (4322 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5a7544eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5a7541e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5a754562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5a74dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5a74daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5a74bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5a716ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5a716eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7f231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5a716ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (4324 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599cf284eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599cf281e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599cf28562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dab733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dab78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dab733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dab71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599cf21abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599cf21aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599cf1ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599ceeaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599ceeaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dab71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dab71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dab71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599ceeaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (4328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c525959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c525956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c52595a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd253249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd253249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd253231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5258efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5258efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5258d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c525583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c525583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd253232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2532330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c525583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (4329 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afe2cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afe2cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afe2cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f575f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f575f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f575f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f575f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afe2c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afe2c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afe2c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afe2926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afe2926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f575f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f575f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f575f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afe2926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (4331 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6b77f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6b77eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6b77f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ac41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ac4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ac41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ac403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6b7787bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6b7787a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6b776c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6b741be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6b741bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31ac404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ac4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ac4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6b741ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (4332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4350dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4350d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4350dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcecf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcecf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcecf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcecf4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b435071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b435071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4350568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b434d05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b434d05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcecf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcecf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcecf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b434d05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (4337 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8be717eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8be714e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8be71862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1646533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f164658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1646533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f164651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8be6adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8be6ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8be6928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8be341e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8be341b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f164651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f164651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f164651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8be341a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (4338 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<vscale x
# | ...
# `---data was truncated (10240/119289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bb9348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bb9345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bb934962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe36cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe36cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe36cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe36cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bb92debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bb92dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bb92c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bb8f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bb8f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe36cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe36cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe36cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bb8f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (4340 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c4e71deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c4e71ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c4e71e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb529f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb529f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb529f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb529f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c4e6b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c4e6b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c4e6988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c4e347e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c4e347b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb529f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb529f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb529f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c4e347a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (4341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624ee274eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624ee271e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624ee27562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3abd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3abd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3abd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3abd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624ee20abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624ee20aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624ee1ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624ede9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624ede9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3abd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3abd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3abd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624ede9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (4351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe318f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe318eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe318f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1502849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1502849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1502831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe31887bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe31887a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe3186c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe3151be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe3151bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1502832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15028330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe3151ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (4352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563558c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563558c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563558c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563558c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563558c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563558c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635588b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635588b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dd531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635588b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (4357 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/81756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564aaeefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564aaeece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564aaef062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564aae85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564aae85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564aae6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564aab19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564aab19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56f011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564aab19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (4362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/151253) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556797412eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055679740fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055679741362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f685da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f685da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f685da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f685da03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567973a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567973a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055679738d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055679703ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055679703cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f685da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f685da050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f685da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055679703ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (4368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4a1d16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4a1d13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4a1d1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac15649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac156a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac15649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac15631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4a1cacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4a1caca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4a1c918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4a1940e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4a1940b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac15632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac156330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac156330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4a1940a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (4373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7ac669eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7ac666e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7ac66a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba9901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba990725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba9901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba99003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7ac5ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7ac5ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7ac5e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7ac293e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7ac293b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba99004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba990050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba990050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7ac293a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (4375 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff5a367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff5a364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff5a36862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73fca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73fcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73fca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73fca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff5a2fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff5a2fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff5a2e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff59f91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff59f91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73fca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73fca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73fca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff59f91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (4386 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f3ecd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f3ecd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f3ecd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f595f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f595f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f595f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f595f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f3ec6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f3ec6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f3ec528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f3e901e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f3e901b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f595f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f595f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f595f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f3e901a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (4394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %v
# | ...
# `---data was truncated (10240/142327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e05248ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e052489e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e05248d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0281b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0281b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0281b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0281b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e052422bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e052422a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0524078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0520b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0520b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0281b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0281b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0281b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0520b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (4400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale
# | ...
# `---data was truncated (10240/156471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d1f192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d1f18fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d1f19362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c1d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c1d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c1d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c1d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d1f128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d1f128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d1f10d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d1edbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d1edbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c1d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c1d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c1d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d1edbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (4401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b07f9ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b07f9cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b07f9cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f441aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f441aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f441aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f441aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b07f964bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b07f964a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b07f9498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b07f5f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b07f5f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f441aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f441aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f441aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b07f5f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (4405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdfb83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdfb80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdfb8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bb505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17bb55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bb505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bb4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdfb19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdfb19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdfafe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bdf7ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bdf7adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17bb4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bb4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bb4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdf7ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (4406 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056245cb91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056245cb8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056245cb9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0636b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0636b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0636b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0636b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056245cb27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056245cb27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056245cb0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056245c7bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056245c7bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0636b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0636b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0636b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056245c7bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (4424 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d25ad54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d25ad51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d25ad5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bd3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bd358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bd3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bd351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d25aceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d25aceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d25accf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d25a97ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d25a97eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bd351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bd351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bd351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d25a97ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (4427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/72143) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608322f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608322f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608322f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e60733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e6078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e60733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e6071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056083228abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056083228aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056083226f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560831f1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560831f1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e6071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e6071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e6071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560831f1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (4431 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556601fc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556601fc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556601fc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc02449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc02449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc02431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556601f59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556601f59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556601f3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556601bede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556601bedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc02432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc024330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556601beda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (4447 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/134736) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056231ef48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056231ef45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056231ef4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a65933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a6598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a65933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a6591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056231eedebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056231eedea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056231eec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056231eb72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056231eb72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a6591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a6591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a6591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056231eb72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (4449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d03331aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d033317e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d03331b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bb4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bb4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bb4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bb4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0332b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0332b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0332958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d032f44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d032f44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bb4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bb4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bb4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d032f44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (4452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563776fa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563776fa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563776fa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58bd105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58bd15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58bd105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58bd0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563776f3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563776f3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563776f238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563776bd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563776bd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58bd0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58bd0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58bd0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563776bd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (4454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3b8c32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3b8c2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3b8c3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe025249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe025249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe025231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3b8bc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3b8bc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3b8bad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3b885ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3b885cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe025232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3b885ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (4455 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca7e23deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca7e23ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca7e23e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff24c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff24c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff24c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff24c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca7e1d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca7e1d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca7e1b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca7de67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca7de67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff24c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff24c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff24c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca7de67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (4457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.add
# | ...
# `---data was truncated (10240/153913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf2818beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf28188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf2818c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf28121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf28121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf281068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf27db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf27db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf27db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (4461 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec3d5deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec3d5dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec3d5df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee71d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee71d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee71d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee71d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec3d574bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec3d574a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec3d5598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec3d208e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec3d208b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee71d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee71d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee71d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec3d208a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (4465 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.a
# | ...
# `---data was truncated (10240/73947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb6a79deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb6a79ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb6a79e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02de41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02de4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02de41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02de403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb6a733bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb6a733a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb6a7188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb6a3c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb6a3c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02de404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02de4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02de4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb6a3c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (4470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055744965beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557449658e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055744965c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4997f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4997f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4997f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4997f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574495f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574495f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574495d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557449285e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557449285b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4997f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4997f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4997f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557449285a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (4471 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717b88beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055717b888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055717b88c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06e3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06e34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06e3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06e3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717b821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055717b821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055717b8068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055717b4b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055717b4b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06e3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06e34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06e34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717b4b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (4474 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646bcd6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646bcd6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646bcd6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fc8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fc8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fc8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fc8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646bcd03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646bcd03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646bcce88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646bc997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646bc997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fc8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fc8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fc8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646bc997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (4476 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055861d667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055861d664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055861d66862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49f491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055861d5fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055861d5fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055861d5e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055861d291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055861d291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49f491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055861d291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (4477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eadfd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563eadfd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563eadfd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f425a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f425a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f425a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f425a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eadf69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563eadf69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563eadf4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eadbfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eadbfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f425a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f425a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f425a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eadbfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (4479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1
# | ...
# `---data was truncated (10240/154215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580dbddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580dbdd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580dbddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f849c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f849c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f849c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f849c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580dbd72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580dbd72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580dbd578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580dba06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580dba06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f849c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f849c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f849c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580dba06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (4481 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563533cfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563533cf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563533cfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71c6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71c695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71c6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71c68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563533c91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563533c91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563533c768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563533925e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563533925b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71c68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71c68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71c68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563533925a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (4485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f32bb68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f32bb65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f32bb6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f826aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f826aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f826aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f826aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f32bafebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f32bafea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f32bae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f32b792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f32b792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f826aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f826aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f826aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f32b792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (4490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i1
# | ...
# `---data was truncated (10240/182173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d0e994eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d0e991e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d0e99562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f475ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f475eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f475ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f475ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d0e92abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d0e92aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d0e90f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d0e5bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d0e5beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f475ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f475ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f475ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d0e5bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (4492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a51034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a51031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a5103562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed6b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed6b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6b603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a50fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a50fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a50faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a50c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a50c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed6b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6b6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a50c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (4495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dee5d68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dee5d65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dee5d6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff984933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff98498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff984933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff98491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dee5cfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dee5cfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dee5ce38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dee5992e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dee5992b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff98491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff98491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff98491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dee5992a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (4499 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op
# | ...
# `---data was truncated (10240/154517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572f5e21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572f5e1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572f5e2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad22733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad2278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad22733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad2271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572f5db7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572f5db7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572f5d9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572f5a4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572f5a4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad2271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad2271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad2271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572f5a4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (4505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632ef3b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632ef3afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632ef3b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05cda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05cdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05cda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05cda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632ef348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632ef348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632ef32d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632eefdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632eefdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05cda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05cda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05cda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632eefdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (4512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056113a2e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056113a2dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056113a2e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2214249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22142a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2214249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2214231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056113a276bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056113a276a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056113a25b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561139f0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561139f0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2214232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22142330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22142330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561139f0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (4514 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c69b687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c69b684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c69b68862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd49a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd49a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd49a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd49a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c69b61dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c69b61da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c69b6028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c69b2b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c69b2b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd49a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd49a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd49a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c69b2b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (4516 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b35aa3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b35aa0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b35aa462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b35a39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b35a39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b35a1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b356cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b356cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b356cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (4519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align 8
# |   sto
# | ...
# `---data was truncated (10240/102864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562067d9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562067d98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562067d9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6995e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6995ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6995e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6995e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562067d31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562067d31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562067d168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620679c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620679c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6995e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6995e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6995e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620679c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (4521 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565392145eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565392142e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056539214662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ebc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ebca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ebc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ebc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653920dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653920dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653920c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565391d6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565391d6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31ebc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ebc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ebc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565391d6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (4522 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055971377eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055971377be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055971377f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559713714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559713714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597136f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597133a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597133a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597133a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (4523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/88436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a29d1a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a29d1a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a29d1a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7fb705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7fb75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7fb705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7fb6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a29d13dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a29d13da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a29d1228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a29cdd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a29cdd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7fb6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7fb6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7fb6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a29cdd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (4524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/150943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce464e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce464e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce464e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b5b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b5b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b5b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b5b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce4647cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce4647ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce464618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce46110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce46110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b5b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b5b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b5b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce46110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (4526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559170943eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559170940e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055917094462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f451cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f451cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f451cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f451cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591708d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591708d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591708be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055917056de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055917056db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f451cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f451cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f451cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055917056da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (4527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cd3e50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cd3e4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cd3e5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86cf305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86cf35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86cf305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86cf2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cd3de6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cd3de6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cd3dcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cd3a7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cd3a7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86cf2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86cf2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86cf2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cd3a7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (4533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>
# | ...
# `---data was truncated (10240/153805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056292b2a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056292b29de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056292b2a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4508649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45086a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4508649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4508631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292b236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056292b236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056292b21b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056292aecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056292aecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4508632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45086330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45086330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056292aecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (4534 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a117adaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a117ad7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a117adb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f691bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f691bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f691bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f691bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a117a70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a117a70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a117a558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a117704e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a117704b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f691bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f691bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f691bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a117704a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (4539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/80640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faa12ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faa12dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faa12de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d06b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d06b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d06b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d06b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faa1273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faa1273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faa12588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faa0f07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faa0f07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d06b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d06b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d06b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faa0f07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (4540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdf61a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdf61a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdf61a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff95049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff95049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff95031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdf613cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdf613ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdf61218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdf5dd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdf5dd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff95032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff950330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdf5dd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (4541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563493ecaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563493ec7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563493ecb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cb5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cb5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cb5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cb5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563493e60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563493e60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563493e458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563493af4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563493af4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cb5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cb5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cb5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563493af4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (4543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056235a1e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056235a1e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056235a1e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f75049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f75049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f75031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056235a17dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056235a17da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056235a1628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562359e11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562359e11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f75032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f750330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562359e11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (4545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4d853feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4d853ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4d854062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4d84d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4d84d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4d84ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4d8169e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4d8169b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dc2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4d8169a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (4546 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <
# | ...
# `---data was truncated (10240/84810) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ff08b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ff08ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ff08b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5fdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ff0846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ff0846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ff082b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ff04dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ff04dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ff04daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (4547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb3daf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb3daede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb3daf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2042649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2042649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2042631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb3da86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb3da86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb3da6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb3d71ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb3d71ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2042632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20426330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb3d71aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (4548 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561844dc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561844dc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561844dc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21a771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561844d5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561844d5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561844d428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618449f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618449f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21a771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618449f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (4549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6428e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6428e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6428e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64a7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64a7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64a7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64a7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c64287cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c64287ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6428618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c642510e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c642510b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64a7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64a7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64a7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c642510a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (4550 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605aac79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605aac76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605aac7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f064df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f064df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f064df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f064df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605aac0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605aac0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605aabf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605aa8a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605aa8a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f064df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f064df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f064df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605aa8a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (4553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590d6598eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590d6595e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590d659962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0aba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0abaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0aba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0aba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d652ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590d652ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590d65138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590d61c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590d61c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0aba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0aba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0aba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d61c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (4557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/153813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558be5197eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558be5194e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558be519862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf0a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf0a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf0a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf0a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558be512dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558be512da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558be51128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558be4dc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558be4dc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf0a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf0a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf0a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558be4dc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (4562 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b64588deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b64588ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b64588e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde78133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde7818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde78133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde7811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b645823bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b645823a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6458088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6454b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6454b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde7811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde7811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde7811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6454b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (4564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   
# | ...
# `---data was truncated (10240/135119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb319a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb3199de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb319a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe83849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe838a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe83849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe83831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb31936bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb31936a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb3191b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb315cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb315cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe83832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe838330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe838330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb315caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (4566 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16
# | ...
# `---data was truncated (10240/84971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cdb9b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cdb9b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cdb9b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf1e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf1e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf1e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf1e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cdb94abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cdb94aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cdb92f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cdb5dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cdb5deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf1e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf1e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf1e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cdb5dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (4571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ffde81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ffde7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ffde8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54d6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54d62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54d6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54d6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ffde17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ffde17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ffddfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ffdaabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ffdaabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54d6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54d62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54d62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ffdaaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (4578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd2ea03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd2ea00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd2ea0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbaf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbaf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbaf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbaf0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd2e999bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd2e999a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd2e97e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd2e62de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd2e62db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbaf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbaf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbaf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd2e62da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (4579 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 
# | ...
# `---data was truncated (10240/98445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056082cacaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056082cac7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056082cacb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8454649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8454649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8454631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056082ca60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056082ca60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056082ca458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056082c6f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056082c6f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8454632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84546330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056082c6f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (4580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babfc13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055babfc10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055babfc1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa27241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2724725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa27241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa272403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babfba9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055babfba9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055babfb8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055babf83de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055babf83db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa272404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2724050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2724050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babf83da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (4583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/72501) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8337efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8337ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8337f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fb8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fb878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fb8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fb871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d833785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d833785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d83376a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d833419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d833419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fb871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fb871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fb871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d833419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (4585 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ce19f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ce19f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ce19f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ce1989bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ce1989a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ce196e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ce161de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ce161db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5de851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ce161da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (4590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561570dd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561570dcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561570dd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dd0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dd055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dd0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dd04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561570d67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561570d67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561570d4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615709fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615709fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dd04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dd04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dd04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615709fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (4595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cae2d21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cae2d1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cae2d2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb67d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb67d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb67d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb67d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cae2cb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cae2cb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cae2c9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cae294be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cae294bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb67d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb67d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb67d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cae294ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (4597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x
# | ...
# `---data was truncated (10240/112817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c35be56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c35be53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c35be5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd653705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd65375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd653705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6536ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c35bdecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c35bdeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c35bdd18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c35ba80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c35ba80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6536eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6536ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6536ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c35ba80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (4598 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f68ba3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f68ba0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f68ba462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64e151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f68b39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f68b39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f68b1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f687cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f687cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64e151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f687cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (4607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4a8e65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4a8e62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4a8e6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bb1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bb195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bb1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bb18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4a8dfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4a8dfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4a8de08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4a8a8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4a8a8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bb18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bb18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bb18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4a8a8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (4608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d44d979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d44d976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d44d97a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c18249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c18249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c18231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d44d90fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d44d90fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d44d8f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d44d5a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d44d5a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c18232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c182330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d44d5a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (4613 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/150649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558db0576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558db0573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558db057762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2809133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2809133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558db050cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558db050ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558db04f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558db01a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558db01a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f280911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db01a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (4616 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e636b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e636b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e636b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f202ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f202ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f202ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f202ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e63649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e63649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e6362e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e632dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e632ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f202ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f202ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f202ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e632dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (4618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556890339eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556890336e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055689033a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5f5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5f595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5f5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5f58ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568902cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568902cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568902b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055688ff63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055688ff63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5f58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5f58ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5f58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055688ff63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (4622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/142024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd1cc75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd1cc72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd1cc7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a4cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a4cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a4cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a4cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd1cc0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd1cc0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd1cbf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd1c89fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd1c89fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a4cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a4cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a4cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd1c89fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (4625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test
# | ...
# `---data was truncated (10240/156773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e81998feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e81998ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e81999062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f740f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f740f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f740f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f740f4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e819925bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e819925a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e81990a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8195b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8195b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f740f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f740f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f740f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8195b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (4626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617e5548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617e5545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617e554962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41a8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41a8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41a8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41a8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617e54debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617e54dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617e54c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617e5172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617e5172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41a8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41a8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41a8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617e5172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (4627 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559234f42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559234f3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559234f4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1a071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559234ed8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559234ed8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559234ebd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559234b6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559234b6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1a071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559234b6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (4633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5be86feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5be86ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5be87062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96e8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96e80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96e8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96e8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5be805bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5be805a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5be7ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5be499e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5be499b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96e8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96e80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96e80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5be499a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (4641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/116949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3aad72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3aad6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3aad7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb94ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb94eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb94ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb94ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3aad08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3aad08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3aaced8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3aa99ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3aa99cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb94ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb94ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb94ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3aa99ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (4643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056449c19beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056449c198e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056449c19c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbee3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbee32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbee3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbee3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056449c131bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056449c131a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056449c1168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056449bdc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056449bdc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbee3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbee32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbee32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056449bdc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (4645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/98581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055951348feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055951348ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055951349062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d73533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d7358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d73533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d7351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559513425bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559513425a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055951340a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595130b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595130b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d7351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d7351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d7351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595130b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (4649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/135345) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1accf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1accede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1accf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8772f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8772f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8772f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8772f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1acc86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1acc86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1acc6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1ac91ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1ac91ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8772f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8772f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8772f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1ac91aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (4651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c636072eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c63606fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c63607362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bf7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bf738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bf7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bf731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c636008bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c636008a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c635fed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c635c9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c635c9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bf731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bf731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bf731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c635c9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (4652 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dec085eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dec082e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dec08662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4d4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4d44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4d4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4d4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dec01bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dec01ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dec0008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557debcafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557debcafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4d4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4d44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4d44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557debcafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (4653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc3095deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc3095ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc3095e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2437249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24372a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2437249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2437231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc308f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc308f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc308d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc30587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc30587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2437232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24372330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24372330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc30587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (4655 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_i8m1_i8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m1_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m2_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m1_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m2_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m4_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 32 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> %0, <vscale x 32 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8>, <vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_u8m1_u8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m1_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m2_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m1_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m2_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m4_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, p
# | ...
# `---data was truncated (10240/54546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a661bcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a661bc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a661bcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3e641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3e64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3e641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3e6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a661b61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a661b61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a661b468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6617f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6617f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3e6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3e64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3e64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6617f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (4656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056069b9e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056069b9e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056069b9e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d44b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d44b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d44b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d44b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056069b97dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056069b97da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056069b9628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056069b611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056069b611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d44b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d44b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d44b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056069b611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (4658 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx
# | ...
# `---data was truncated (10240/75125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7e5d32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7e5d2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7e5d3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05ef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05ef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05ef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05ef71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7e5cc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7e5cc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7e5cad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7e595ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7e595cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05ef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05ef71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05ef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7e595ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (4662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056123d708eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056123d705e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056123d70962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd0c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd0c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd0c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd0c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056123d69ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056123d69ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056123d6838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056123d332e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056123d332b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd0c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd0c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd0c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056123d332a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (4664 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624fa80deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624fa80ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624fa80e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfdef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfdef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfdef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfdef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624fa7a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624fa7a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624fa7888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624fa437e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624fa437b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfdef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfdef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfdef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624fa437a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (4666 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b51eeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b51eebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b51eef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f350ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f350aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f350ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f350ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b51e84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b51e84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b51e698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b51b18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b51b18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f350ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f350ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f350ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b51b18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (4669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4d278deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4d278ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4d278e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd538f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd538f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd538f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd538eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4d2723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4d2723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4d27088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4d23b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4d23b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd538eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd538eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd538eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4d23b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (4671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556db183aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556db1837e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556db183b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd1bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556db17d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556db17d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556db17b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556db1464e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556db1464b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556db1464a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (4675 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ffe649eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ffe646e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ffe64a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ab0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ab0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ab0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ab0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ffe5dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ffe5dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ffe5c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ffe273e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ffe273b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ab0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ab0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ab0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ffe273a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (4680 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d88a1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d88a1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d88a1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f339ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f339eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f339ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f339ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d889b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d889b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d889998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d88648e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d88648b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f339ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f339ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f339ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d88648a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (4682 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsmul_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b130c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b130c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b130c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f900f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f900f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f900f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f900f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b130bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b130bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b130bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b13085de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b13085db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f900f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f900f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f900f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b13085da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (4692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da50643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da50640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da5064462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b2c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b2c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da505d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da505d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da505be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da5026de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da5026db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b2c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da5026da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (4694 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba9b513eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba9b510e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba9b51462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff175133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff17518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff175133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff17511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba9b4a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba9b4a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba9b48e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba9b13de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba9b13db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff17511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff17511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff17511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba9b13da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (4701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631a1f1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631a1f18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631a1f1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe71781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7178725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe71781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe717803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631a1eb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631a1eb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631a1e968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631a1b45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631a1b45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe717804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7178050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7178050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631a1b45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (4707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601db293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601db290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601db29462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33e6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33e698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33e6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33e691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601db229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601db229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601db20e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601daebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601daebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33e691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33e691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33e691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601daebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (4710 of 27910)
******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou
# | ...
# `---data was truncated (10240/28396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055e5694bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5694b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5694bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ecd21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ecd2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ecd21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ecd203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e569451bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e569451a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5694368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5690e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5690e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ecd204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ecd2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ecd2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5690e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (4712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613f9ed2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613f9ecfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613f9ed362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9a1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9a1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9a1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9a1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f9e68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613f9e68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613f9e4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613f9afce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613f9afcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9a1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9a1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9a1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f9afca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (4713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f40d60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f40d5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f40d6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7fd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7fd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7fd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7fd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f40cf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f40cf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f40cdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f4098ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f4098ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7fd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7fd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7fd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f4098aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (4714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/176543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055569a9fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055569a9f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055569a9fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b14049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b14049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b14031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055569a992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055569a992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055569a9778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055569a626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055569a626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b14032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b140330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055569a626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (4718 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588f98b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588f98b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588f98b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588f9849bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588f9849a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588f982e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588f94dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588f94ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588f94dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (4723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1
# | ...
# `---data was truncated (10240/87183) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d1af69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d1af66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d1af6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f547a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f547a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f547a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f547a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d1aeffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d1aeffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d1aee48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d1ab93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d1ab93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f547a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f547a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f547a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d1ab93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (4724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 
# | ...
# `---data was truncated (10240/117397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563898dbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563898dbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563898dbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa074733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa07478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa074733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa07471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563898d53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563898d53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563898d388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638989e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638989e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa07471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa07471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa07471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638989e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (4729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4
# | ...
# `---data was truncated (10240/96257) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8e500ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8e5009e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8e500d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd94b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd94b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd94b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd94b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8e4fa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8e4fa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8e4f878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8e4c36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8e4c36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd94b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd94b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd94b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8e4c36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (4730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7dd101eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7dd0fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7dd10262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe095b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe095b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe095b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe095b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7dd097bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7dd097a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7dd07c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7dcd2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7dcd2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe095b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe095b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe095b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7dcd2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (4731 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6394d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6394d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6394d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1261d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1261d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1261d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1261ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a63946dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a63946da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6394528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a639101e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a639101b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1261ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1261cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1261cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a639101a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (4737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfb5f24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfb5f21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfb5f2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfb5ebabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfb5ebaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfb5e9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfb5b4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfb5b4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfb5b4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (4738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7bd9bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7bd9bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7bd9be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b7ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b7ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b7ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b7ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7bd953bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7bd953a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7bd9388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7bd5e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7bd5e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b7ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b7ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b7ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7bd5e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (4740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = e
# | ...
# `---data was truncated (10240/100513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f14f491eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f14f48ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f14f49262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9116c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9116ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9116c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9116c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f14f427bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f14f427a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f14f40c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f14f0bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f14f0bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9116c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9116c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9116c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f14f0bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (4744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf7a714eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf7a711e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf7a71562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f620d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f620d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f620d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f620d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf7a6aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf7a6aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf7a68f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf7a33ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf7a33eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f620d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f620d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f620d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf7a33ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (4745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <v
# | ...
# `---data was truncated (10240/98125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4b14e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4b14dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4b14e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b1478bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4b1478a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4b145d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4b110ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4b110cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f442b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b110ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (4748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/100952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559853db2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559853dafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559853db362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ef1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ef14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ef1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ef1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559853d48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559853d48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559853d2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598539dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598539dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ef1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ef14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ef14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598539dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (4749 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dc4465eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dc4462e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dc446662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae26631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dc43fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dc43fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dc43e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dc408fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dc408fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dc408fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (4752 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaadd_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dc0441eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dc043ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dc044262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e07849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e07849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e07831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dc03d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dc03d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dc03bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dc006be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dc006bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e07832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e078330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dc006ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (4753 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a2768aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a27687e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a2768b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa65849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa658a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa65849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa65831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a27620bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a27620a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a276058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a272b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a272b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa65832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa658330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa658330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a272b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (4754 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570c9bf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570c9bf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570c9bfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd900533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd90058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd900533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd90051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570c9b8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570c9b8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570c9b748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570c9823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570c9823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd90051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd90051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd90051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570c9823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (4761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a051e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a051e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a051e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2924049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29240a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2924049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2924031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a0517ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a0517ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a051638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a04e12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a04e12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2924032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29240330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29240330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a04e12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (4763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ca252eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ca252be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ca252f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e0fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e0fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e0fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e0fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ca24c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ca24c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ca24a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ca2158e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ca2158b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e0fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e0fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e0fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ca2158a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (4765 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 
# | ...
# `---data was truncated (10240/97506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056427509ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564275099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056427509d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae58933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae5898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae58933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae5891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564275032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564275032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642750178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564274cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564274cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae5891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae5891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae5891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564274cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (4767 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563310df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563310df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563310dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb4a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb4a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb4a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb4a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563310d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563310d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563310d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563310a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563310a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb4a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb4a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb4a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563310a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (4776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645bd894eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645bd891e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645bd89562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc21a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc21a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc21a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc21a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645bd82abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645bd82aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645bd80f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645bd4bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645bd4beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc21a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc21a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc21a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645bd4bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (4784 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717e9b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055717e9b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055717e9b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cdb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cdb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cdb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cdb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717e94bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055717e94ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055717e9308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055717e5dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055717e5dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cdb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cdb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cdb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717e5dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (4785 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056421341aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564213417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056421341b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac5da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac5daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac5da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac5da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642133b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642133b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642133958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564213044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564213044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac5da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac5da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac5da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564213044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (4788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210585aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562105857e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210585b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5110249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5110249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5110231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621057f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621057f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621057d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562105484e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562105484b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5110232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51102330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562105484a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (4794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bi
# | ...
# `---data was truncated (10240/136481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619ef4eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619ef4e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619ef4eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cfcd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cfcd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cfcd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cfcced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619ef480bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619ef480a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619ef4658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619ef114e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619ef114b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cfcceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cfccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cfccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619ef114a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (4796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056141ff15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056141ff12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056141ff1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2d8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2d8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2d8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2d8ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056141feabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056141feaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056141fe908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056141fb3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056141fb3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2d8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2d8cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2d8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056141fb3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (4801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055addeda4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055addeda1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055addeda562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd86a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd86a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd86a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd86a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055added3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055added3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055added1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adde9cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adde9ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd86a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd86a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd86a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adde9cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (4805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cae8debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cae8de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cae8dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0853733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0853733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cae8d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cae8d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cae8d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cae8a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cae8a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f085371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cae8a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (4812 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558419fe0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558419fdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558419fe162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c3c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c3c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c3c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c3c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558419f76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558419f76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558419f5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558419c0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558419c0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c3c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c3c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c3c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558419c0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (4813 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569bd375eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569bd372e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569bd37662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07a0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07a0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07a0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07a0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569bd30bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569bd30ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569bd2f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569bcf9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569bcf9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07a0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07a0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07a0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569bcf9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (4819 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd19448eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd19445e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd1944962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feec3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feec32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feec3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feec3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd193debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd193dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd193c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd19072e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd19072b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feec3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feec32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feec32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd19072a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (4821 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b15404eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b15401e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b1540562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f892a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f892a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f892a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f892a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b1539abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b1539aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b1537f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b1502ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b1502eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f892a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f892a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f892a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b1502ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (4822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055724f2ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055724f2e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055724f2ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2edee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2edeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2edee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2edee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055724f281bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055724f281a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055724f2668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055724ef15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055724ef15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2edee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2edee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2edee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055724ef15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (4825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf9cd06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf9cd03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf9cd0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1866c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1866ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1866c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1866c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf9cc9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf9cc9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf9cc818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf9c930e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf9c930b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1866c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1866c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1866c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf9c930a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (4826 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a1423feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a1423ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a1424062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3598c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3598ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3598c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3598c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a141d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a141d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a141ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a13e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a13e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3598c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3598c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3598c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a13e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (4830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/54488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c67573ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c675739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c67573d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40e7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40e74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40e7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40e7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6756d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6756d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6756b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c675366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c675366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40e7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40e74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40e74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c675366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (4832 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056437f5edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056437f5eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056437f5ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6484733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f648478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6484733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f648471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056437f583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056437f583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056437f5688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056437f217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056437f217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f648471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f648471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f648471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056437f217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (4833 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bca941eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bca93ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bca94262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4fc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bca8d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bca8d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bca8bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bca56be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bca56bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4fc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bca56ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (4840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/110284) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb055eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb055be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb055f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f453541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45354725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f453541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4535403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb04f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb04f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb04d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb0188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb0188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4535404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45354050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45354050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb0188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (4842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613dfdd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613dfdcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613dfdd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613dfd68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613dfd68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613dfd4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613df9fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613df9fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613df9fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (4844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0c88efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c88ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c88f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9640333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f964038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9640333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f964031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c8885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c8885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c886a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c8519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c8519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f964031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f964031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f964031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c8519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (4847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/94149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055711b9fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055711b9fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055711b9fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5a4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5a4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5a4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5a4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055711b993bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055711b993a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055711b9788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055711b627e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055711b627b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5a4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5a4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5a4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055711b627a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (4849 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/78164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651f00abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651f00a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651f00ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02b2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02b218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02b2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02b211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651f0041bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651f0041a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651f00268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651efcd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651efcd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02b211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02b211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02b211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651efcd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (4854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>
# | ...
# `---data was truncated (10240/76635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a5851aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a58517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a5851b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f013ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f013cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f013ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f013ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a584b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a584b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a584958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a58144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a58144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f013ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f013ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f013ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a58144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (4859 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c48a94feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c48a94ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c48a95062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9590c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9590c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9590c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9590c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c48a8e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c48a8e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c48a8ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c48a579e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c48a579b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9590c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9590c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9590c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c48a579a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (4861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584ee2f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584ee2efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584ee2f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b4a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b4a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584ee288bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584ee288a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584ee26d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584edf1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584edf1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b4a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584edf1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (4862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c89a123eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c89a120e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c89a12462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c97849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c97849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c97831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c89a0b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c89a0b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c89a09e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c899d4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c899d4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c97832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c899d4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (4864 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576c8e61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576c8e5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576c8e6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c58333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c5838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c58333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c5831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576c8df7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576c8df7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576c8ddc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576c8a8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576c8a8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c5831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c5831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c5831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576c8a8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (4865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055decc41aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055decc417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055decc41b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e6d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e6d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e6d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e6d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055decc3b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055decc3b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055decc3958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055decc044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055decc044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e6d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e6d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e6d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055decc044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (4866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bb5990eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bb598de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bb599162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe625933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe62598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe625933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe62591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bb5926bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bb5926a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bb590b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bb55bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bb55bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe62591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe62591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe62591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bb55baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (4868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055930cd30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055930cd2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055930cd3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab42b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab42b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab42b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab42b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055930ccc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055930ccc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055930ccab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055930c95ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055930c95ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab42b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab42b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab42b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055930c95aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (4872 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055beab582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055beab57fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055beab58362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6187533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f618758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6187533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f618751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055beab518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055beab518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055beab4fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055beab1ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055beab1acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f618751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f618751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f618751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055beab1aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (4873 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bebbfddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bebbfdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bebbfde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa07df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa07df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa07df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa07df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bebbf73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bebbf73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bebbf588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bebbc07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bebbc07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa07df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa07df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa07df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bebbc07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (4877 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1c6aa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1c6aa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1c6aa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1556333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f155638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1556333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f155631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1c6a3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1c6a3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1c6a218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1c66d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1c66d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f155631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f155631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f155631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1c66d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (4882 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b66120feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b66120ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b66121062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f170d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f170d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f170d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f170d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6611a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6611a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b66118a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b660e39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b660e39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f170d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f170d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f170d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b660e39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (4883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vasub_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a27bd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a27bcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a27bd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6fd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a27b67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a27b67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a27b4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a277fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a277fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6fd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a277fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (4884 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f24eca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f24ec9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f24eca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0550c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0550c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0550c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0550c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f24ec38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f24ec38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f24ec1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f24e8cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f24e8ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0550c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0550c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0550c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f24e8cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (4885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd194a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd194a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd194a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f678e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f678e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f678e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f678e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd1943cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd1943ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd194218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd190d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd190d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f678e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f678e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f678e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd190d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (4888 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9b883aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9b8837e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9b883b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fa2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fa218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fa2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fa211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9b87d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9b87d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9b87b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9b8464e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9b8464b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fa211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fa211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fa211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9b8464a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (4890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056195172aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561951727e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056195172b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619516c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619516c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619516a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561951354e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561951354b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561951354a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (4895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbf2e23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbf2e20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbf2e2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f165c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f165c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f165c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f165c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbf2db9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbf2db9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbf2d9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbf2a4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbf2a4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f165c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f165c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f165c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbf2a4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (4896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf05079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf05076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf0507a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9146333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f914638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9146333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f914631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf0500fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf0500fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf04ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf04ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf04ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f914631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f914631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f914631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf04ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (4897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# | 
# | ...
# `---data was truncated (10240/100521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056524ba0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056524ba09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056524ba0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e53c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e53ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e53c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e53c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056524b9a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056524b9a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056524b9878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056524b636e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056524b636b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e53c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e53c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e53c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056524b636a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (4906 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2b3a0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2b3a0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2b3a1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f656b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f656b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f656b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f656b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2b39a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2b39a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2b398a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2b3639e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2b3639b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f656b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f656b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f656b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2b3639a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (4907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/110070) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8921d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8921d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8921d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f76b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f76b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f76b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f76b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a89216dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a89216da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8921528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a891e01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a891e01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f76b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f76b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f76b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a891e01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (4908 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %
# | ...
# `---data was truncated (10240/67150) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f18bcbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f18bcb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f18bcbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42a6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42a698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42a6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42a691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f18bc50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f18bc50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f18bc358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f18b8e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f18b8e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42a691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42a691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42a691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f18b8e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (4911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fa5feeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fa5febe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fa5fef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bb2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bb2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bb2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bb2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fa5f84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fa5f84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fa5f698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fa5c18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fa5c18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bb2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bb2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bb2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fa5c18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (4914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557244478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557244475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055724447962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055724440ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055724440ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572443f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572440a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572440a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25e7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572440a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (4916 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, 
# | ...
# `---data was truncated (10240/62087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8e4f8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8e4f89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8e4f8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8e4f22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8e4f22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8e4f078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8e4bb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8e4bb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8e4bb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (4919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e002c8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e002c88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e002c8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80dba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80dbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80dba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80dba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e002c21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e002c21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e002c068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0028b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0028b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80dba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80dba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80dba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0028b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (4922 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef
# | ...
# `---data was truncated (10240/78336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bb4f98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bb4f95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bb4f9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8411533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f841158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8411533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f841151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bb4f2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bb4f2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bb4f138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bb4bc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bb4bc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f841151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f841151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f841151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bb4bc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (4926 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055866bcf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055866bcf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055866bcf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fc0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fc0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fc0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fc0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055866bc8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055866bc8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055866bc728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055866b921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055866b921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fc0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fc0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fc0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055866b921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (4928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4abf69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4abf66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4abf6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3357d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3357d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3357d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3357d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4abeffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4abeffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4abee48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4abb93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4abb93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3357d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3357d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3357d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4abb93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (4935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f7b753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f7b750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f7b75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0496a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0496aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0496a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0496a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f7b6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f7b6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f7b6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f7b37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f7b37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0496a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0496a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0496a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f7b37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (4936 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584aa01ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584aa019e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584aa01d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc99d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc99d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc99d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc99d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584a9fb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584a9fb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584a9f978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584a9c46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584a9c46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc99d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc99d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc99d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584a9c46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (4937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580221a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580221a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580221a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe71fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe71fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe71fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe71fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055802213cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055802213ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580221218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558021dd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558021dd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe71fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe71fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe71fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558021dd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (4942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x
# | ...
# `---data was truncated (10240/78032) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595e6334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595e6331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595e633562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff233533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff23358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff233533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff23351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e62cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595e62caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595e62af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595e5f5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595e5f5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff23351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff23351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff23351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e5f5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (4945 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c44e2c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c44e2bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c44e2c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f298a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f298a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c44e258bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c44e258a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c44e23d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c44deece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c44deecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f298a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c44deeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (4946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/135111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e20d90ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e20d909e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e20d90d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68ca41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68ca4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68ca41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68ca403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e20d8a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e20d8a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e20d8878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e20d536e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e20d536b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68ca404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68ca4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68ca4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e20d536a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (4949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7341dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7341d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7341dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faba5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faba5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faba5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faba5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d734172bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d734172a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7341578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d733e06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d733e06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faba5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faba5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faba5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d733e06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (4954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c58dcb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c58dcb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c58dcb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac6511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c58dc4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c58dc4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c58dc2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c58d8dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c58d8deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac6511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c58d8dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (4955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eb0ff8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558eb0ff5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558eb0ff962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f833b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f833b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f833b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f833b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eb0f8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558eb0f8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558eb0f738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558eb0c22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558eb0c22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f833b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f833b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f833b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eb0c22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (4961 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056276a24feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056276a24ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056276a25062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda2cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda2cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda2cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda2cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056276a1e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056276a1e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056276a1ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562769e79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562769e79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda2cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda2cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda2cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562769e79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (4966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1fe99ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1fe999e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1fe99d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc34ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc34cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc34ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc34ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1fe932bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1fe932a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1fe9178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1fe5c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1fe5c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc34ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc34ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc34ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1fe5c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (4969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d445dc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d445dbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d445dc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8049f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8049f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8049f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8049f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d445d57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d445d57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d445d3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4459ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4459ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8049f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8049f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8049f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4459eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (4970 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556189681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055618967ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055618968262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42c2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42c22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42c2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42c2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556189617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556189617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561895fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561892abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561892abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42c2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42c22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42c22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561892aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (4971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c9ebe3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c9ebe0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c9ebe462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2101849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2101849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2101831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c9eb79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c9eb79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c9eb5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c9e80de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c9e80db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2101832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21018330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c9e80da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (4973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615f6fafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615f6face85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615f6fb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1601f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1601f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1601f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1601eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615f6f45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615f6f45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615f6f2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615f6bd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615f6bd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1601eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1601eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1601eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615f6bd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (4974 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8f481ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8f4819e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8f481d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8b1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8b158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8b1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8b151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8f47b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8f47b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8f47978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8f4446e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8f4446b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8b151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8b151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8b151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8f4446a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (4975 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc959cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc959cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc959d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb451533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb45158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb451533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb45151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc95965bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc95965a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc9594a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc955f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc955f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb45151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb45151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb45151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc955f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (4976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055561207beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555612078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055561207c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff01ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff01ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff01ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555612011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555612011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555611ff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555611ca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555611ca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff01ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff01ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff01ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555611ca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (4984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559336c40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559336c3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559336c4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f196d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f196d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f196d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f196d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559336bd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559336bd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559336bbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055933686ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055933686ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f196d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f196d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f196d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055933686aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (4989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b293a25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b293a22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b293a2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1104333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f110438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1104333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f110431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2939bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2939bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2939a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b29364fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b29364fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f110431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f110431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f110431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b29364fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (4991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631e6d71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631e6d6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631e6d7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6238b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6238b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6238b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6238aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631e6d07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631e6d07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631e6cec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631e699be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631e699bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6238aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6238aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6238aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631e699ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (4993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x
# | ...
# `---data was truncated (10240/84802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589c7d4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589c7d49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589c7d4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe422333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe42238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe422333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe42231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589c7ce2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589c7ce2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589c7cc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589c7976e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589c7976b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe42231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe42231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe42231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589c7976a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (4996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4597beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd45978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd4597c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f100b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f100b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f100b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f100b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd45911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd45911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd458f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd455a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd455a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f100b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f100b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f100b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd455a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (4997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a824681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a82467ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a82468262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c92733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c9278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c92733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c9271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a824617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a824617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8245fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8242abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8242abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c9271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c9271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c9271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8242aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (5000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f6a43ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f6a439e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f6a43d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c84649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c846a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c84649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c84631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f6a3d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f6a3d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f6a3b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f6a066e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f6a066b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c84632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c846330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c846330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f6a066a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (5001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/101483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611bddc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611bddbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611bddc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb616049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb616049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb616031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611bdd57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611bdd57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611bdd3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611bd9ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611bd9ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb616032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611bd9eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (5002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055596158aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555961587e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055596158b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f58849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f588a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f58849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f58831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555961520bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555961520a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559615058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559611b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559611b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f58832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f588330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f588330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559611b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (5005 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626c389aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626c3897e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626c389b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f900c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f900c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f900c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f900c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626c3830bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626c3830a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626c38158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626c34c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626c34c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f900c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f900c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f900c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626c34c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (5007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651bb474eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651bb471e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651bb47562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78e9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78e998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78e9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78e991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651bb40abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651bb40aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651bb3ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651bb09ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651bb09eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78e991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78e991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78e991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651bb09ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (5012 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560fb5d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560fb5cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560fb5d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4695133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f469518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4695133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f469511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560fb566bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560fb566a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560fb54b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560fb1fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560fb1fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f469511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f469511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f469511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560fb1faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/builtins-arm64.c (5013 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load ptr, ptr %b.addr, align 8
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @tp() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbitl(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.bitreverse.i64(i64) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbit64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @hints() #0 {
# | entry:
# |   call void @llvm.aarch64.hint(i32 0)
# |   call void @llvm.aarch64.hint(i32 1)
# |   call void @llvm.aarch64.hint(i32 2)
# |   call void @llvm.aarch64.hint(i32 3)
# |   call void @llvm.aarch64.hint(i32 4)
# |   call void @llvm.aarch64.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.aarch64.hint(i32) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @barriers() #0 {
# | entry:
# |   call void @llvm.aarch64.dmb(i32 1)
# |   call void @llvm.aarch64.dsb(i32 2)
# |   call void @llvm.aarch64.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dmb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dsb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.isb(i32) #5
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch_x() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @read_intent_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch.ir(ptr null)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @jcvt(double noundef %v) #7 {
# | entry:
# |   %v.addr = alloca double, align 8
# |   store double %v, ptr %v.addr, align 8
# |   %0 = load double, ptr %v.addr, align 8
# |   %1 = call i32 @llvm.aarch64.fjcvtzs(double %0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.fjcvtzs(double) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rsr() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = trunc i64 %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i64 @llvm.read_volatile_register.i64(metadata) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rsr64() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @rsrp() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = inttoptr i64 %0 to ptr
# |   ret ptr %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %1 = zext i32 %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nounwind
# | declare void @llvm.write_register.i64(metadata, i64) #8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr64(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   call void @llvm.write_register.i64(metadata !7, i64 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsrp(ptr noundef %v) #0 {
# | entry:
# |   %v.addr = alloca ptr, align 8
# |   store ptr %v, ptr %v.addr, align 8
# |   %0 = load ptr, ptr %v.addr, align 8
# |   %1 = ptrtoint ptr %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cls(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %cls = call i32 @llvm.aarch64.cls(i32 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsl(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls64(i64) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsll(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndr(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndr()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndr() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndrrs()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndrrs() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @trap() #0 {
# | entry:
# |   call void @llvm.aarch64.break(i32 42)
# |   ret void
# | }
# | 
# | ; Function Attrs: cold noreturn nounwind
# | declare void @llvm.aarch64.break(i32 immarg) #10
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca i64, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8
# |   %2 = load ptr, ptr %a.addr, align 8
# |   %3 = load i64, ptr %b.addr, a
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   243 |   __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint
# |       |   ^                                                            ~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type]
# |   305 |   __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type]
# |   306 |   __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type]
# |   307 |   __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH);
# |       |   ^                                                                ~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   308 |   return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5);
# |       |          ^                                                                ~
# | 5 warnings generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556183739eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556183736e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055618373a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561836cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561836cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561836b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556183363e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556183363b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556183363a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (5016 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f77e1cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f77e1cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f77e1d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7d7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f77e165bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f77e165a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f77e14a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f77ddf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f77ddf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7d74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f77ddf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (5017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsm
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562dbdf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562dbdeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562dbdf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90ad81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90ad8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90ad81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90ad803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562dbd87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562dbd87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562dbd6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562dba1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562dba1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90ad804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90ad8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90ad8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562dba1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (5018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573d25caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573d25c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573d25cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20cbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20cbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20cbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20cbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573d2560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573d2560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573d25458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573d21f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573d21f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20cbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20cbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20cbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573d21f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (5022 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/68065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568ce2eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568ce2ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568ce2ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa674305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa67435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa674305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6742ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568ce284bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568ce284a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568ce2698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568cdf18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568cdf18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6742eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6742ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6742ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568cdf18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (5024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f497c36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f497c33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f497c3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0503333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f050338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0503333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f050331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f497bccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f497bcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f497bb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f497860e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f497860b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f050331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f050331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f050331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f497860a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (5025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559737a97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559737a94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559737a9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4096b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4096b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4096b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4096b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559737a2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559737a2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559737a128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597376c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597376c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4096b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4096b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4096b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597376c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (5028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d75c575eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d75c572e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d75c57662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19c0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19c0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19c0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19c0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d75c50bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d75c50ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d75c4f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d75c19fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d75c19fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19c0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19c0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19c0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d75c19fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (5034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/69542) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442bfa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056442bf9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056442bfa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5782d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5782d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5782d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5782d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056442bf37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056442bf37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056442bf1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056442bbcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056442bbcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5782d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5782d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5782d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442bbcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (5039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e1a51beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e1a518e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e1a51c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0311933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f031198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0311933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f031191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e1a4b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e1a4b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e1a4968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e1a145e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e1a145b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f031191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f031191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f031191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e1a145a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (5040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff4353eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff4353be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff4353f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb76f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb76f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb76f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb76f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff434d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff434d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff434b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff43168e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff43168b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb76f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb76f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb76f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff43168a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (5042 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aeb3d9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aeb3d9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aeb3d9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6131c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6131ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6131c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6131c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aeb3d33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aeb3d33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aeb3d188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aeb39c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aeb39c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6131c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6131c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6131c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aeb39c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (5043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/170497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561add40feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561add40ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561add41062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d0b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d0b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d0b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d0b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561add3a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561add3a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561add38a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561add039e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561add039b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d0b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d0b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d0b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561add039a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (5045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636c0cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636c0ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636c0cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4a6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4a658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4a6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4a651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636c0c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636c0c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636c0c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636c08fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636c08fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4a651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4a651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4a651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636c08faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (5049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbbad3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbbad3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbbad3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8077849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80778a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8077849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8077831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbbacd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbbacd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbbacb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbba967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbba967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8077832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80778330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80778330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbba967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (5050 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/124036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c5583feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c5583ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c5584062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f777481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77748725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f777481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7774803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c557d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c557d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c557ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c55469e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c55469b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7774804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77748050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77748050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c55469a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (5051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e3ff21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e3ff1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e3ff2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4909733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f490978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4909733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f490971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e3feb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e3feb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e3fe9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e3fb4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e3fb4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f490971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f490971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f490971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e3fb4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (5058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e08da58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e08da55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e08da5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f627c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f627c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f627c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f627c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e08d9eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e08d9eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e08d9d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e08d682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e08d682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f627c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f627c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f627c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e08d682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (5060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565195c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565195bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565195c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6947e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6947e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6947e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6947e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556519556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556519556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055651953b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565191eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565191eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6947e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6947e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6947e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565191eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (5061 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2c4ea7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2c4ea4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2c4ea862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbacc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbacc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbacc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbacc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2c4e3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2c4e3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2c4e228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2c4ad1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2c4ad1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbacc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbacc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbacc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2c4ad1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (5067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e743f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e743ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e743f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f079c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f079c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f079c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f079c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e74386bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e74386a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e7436b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e7401ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e7401ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f079c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f079c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f079c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e7401aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (5076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2d44c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2d44c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2d44c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53e8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53e858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53e8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53e851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2d445cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2d445ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2d44418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2d40f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2d40f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53e851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53e851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53e851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2d40f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (5077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b0bd5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b0bd57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b0bd5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe869449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8694a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe869449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe869431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b0bcf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b0bcf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b0bcd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b0b984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b0b984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe869432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8694330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8694330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b0b984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (5080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e4a8c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e4a8c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e4a8ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8a1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8a158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8a1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8a151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e4a85fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e4a85fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e4a8448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e4a4f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e4a4f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8a151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8a151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8a151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e4a4f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (5081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116957) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055636feaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055636fea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055636fead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3432533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f343258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3432533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f343251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055636fe42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055636fe42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055636fe278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055636fad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055636fad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f343251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f343251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f343251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055636fad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (5082 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, a
# | ...
# `---data was truncated (10240/81515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056359fddbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056359fdd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056359fddc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfe4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfe4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfe4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfe4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056359fd71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056359fd71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056359fd568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056359fa05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056359fa05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfe4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfe4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfe4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056359fa05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (5085 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %v
# | ...
# `---data was truncated (10240/110062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0c6df3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0c6df0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0c6df462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f28049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f280a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f28049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f28031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0c6d89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0c6d89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0c6d6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0c6a1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0c6a1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f28032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f280330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f280330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0c6a1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (5086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579e5f55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579e5f52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579e5f5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cac71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e5eebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579e5eeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579e5ed08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579e5b7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579e5b7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cac71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e5b7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (5088 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557125ce2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557125cdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557125ce362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9531e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9531ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9531e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9531e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557125c78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557125c78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557125c5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055712590ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055712590cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9531e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9531e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9531e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055712590ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (5091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055955df2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055955df28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055955df2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055955dec1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055955dec1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055955dea68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055955db55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055955db55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055955db55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (5097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a70d9a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a70d9a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a70d9a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c7a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c7a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c7a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c7a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a70d939bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a70d939a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a70d91e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a70d5cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a70d5cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c7a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c7a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c7a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a70d5cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (5099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1b9689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1b9686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1b968a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc0ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc0ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc0ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc0ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1b961fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1b961fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1b96048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1b92b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1b92b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc0ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc0ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc0ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1b92b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (5102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/95437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ec3fd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ec3fcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ec3fd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7cca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7ccaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7cca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7cca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ec3f67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ec3f67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ec3f4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ec3bfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ec3bfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7cca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7cca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7cca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ec3bfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (5103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f226a82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f226a7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f226a8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f978481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97848725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f978481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9784803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f226a18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f226a18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2269fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2266ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2266acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9784804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97848050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97848050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2266aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (5105 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x
# | ...
# `---data was truncated (10240/101475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b3f23eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b3f23be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b3f23f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b47649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b476a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b47649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b47631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b3f1d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b3f1d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b3f1b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b3ee68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b3ee68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b47632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b476330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b476330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b3ee68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (5109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560704559eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560704556e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056070455a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7b4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7b48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7b4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7b4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607044efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607044efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607044d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560704183e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560704183b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7b4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7b48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7b48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560704183a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (5112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 
# | ...
# `---data was truncated (10240/97240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1e49eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1e49e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1e49eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a8d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a8d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a8d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a8d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1e4980bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1e4980a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1e49658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1e4614e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1e4614b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a8d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a8d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a8d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1e4614a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (5114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.
# | ...
# `---data was truncated (10240/78156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565311cddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565311cdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565311cde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7d521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7d52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7d521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7d5203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565311c73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565311c73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565311c588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565311907e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565311907b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7d5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7d52050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7d52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565311907a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (5120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e94937eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e94934e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e9493862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe42bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe42bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe42bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe42bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e948cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e948cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e948b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e94561e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e94561b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe42bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe42bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe42bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e94561a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (5126 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055970dc9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055970dc97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055970dc9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f43d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f43d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f43d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f43d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055970dc30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055970dc30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055970dc158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055970d8c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055970d8c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f43d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f43d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f43d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055970d8c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (5128 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cafba57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cafba54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cafba5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddb6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddb6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddb6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddb6a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cafb9edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cafb9eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cafb9d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cafb681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cafb681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddb6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddb6a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddb6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cafb681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (5130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx
# | ...
# `---data was truncated (10240/78682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d60ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d60eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d60ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15edf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15edf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15edf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15edf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d60e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d60e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d60e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d60ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d60ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15edf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15edf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15edf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d60ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (5131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e85bd24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e85bd21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e85bd2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b74c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b74ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b74c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b74c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e85bcbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e85bcbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e85bc9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e85b94ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e85b94eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b74c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b74c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b74c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e85b94ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (5132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdcabfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdcabfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdcabfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3c0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdcab93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdcab93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdcab788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdca827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdca827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3c00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdca827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (5136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eebda80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eebda7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eebda8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd406733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd40678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd406733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd40671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eebda16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eebda16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eebd9fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eebd6aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eebd6aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd40671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd40671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd40671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eebd6aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (5138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558baaa69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558baaa66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558baaa6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb31a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb31a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb31a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb31a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558baa9ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558baa9ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558baa9e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558baa693e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558baa693b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb31a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb31a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb31a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558baa693a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (5139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f129225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f129222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f12922662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaa0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaa00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaa0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaa0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1291bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1291bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1291a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f128e4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f128e4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaa0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaa00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaa00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f128e4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (5140 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579ce764eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579ce761e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579ce76562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28f3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28f3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28f3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28f3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579ce6fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579ce6faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579ce6df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579ce38ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579ce38eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28f3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28f3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28f3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579ce38ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (5141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff6d4deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff6d4dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff6d4df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29d0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff6d474bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff6d474a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff6d4598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff6d108e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff6d108b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff6d108a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (5143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568ce106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568ce103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568ce10762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecea231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568ce09cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568ce09ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568ce0818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568cdd30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568cdd30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecea2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568cdd30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (5146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfs
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c993f4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c993f4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c993f4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5437933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f543798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5437933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f543791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c993ee3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c993ee3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c993ec88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c993b77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c993b77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f543791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f543791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f543791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c993b77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (5150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f1bc8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f1bc8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f1bc9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4412133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f441218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4412133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f441211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f1bc25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f1bc25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f1bc0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f1b8b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f1b8b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f441211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f441211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f441211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f1b8b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (5153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8
# | ...
# `---data was truncated (10240/60809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b18cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b18ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b18cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8115649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81156a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8115649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8115631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b18c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b18c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b18c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b188fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b188fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8115632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81156330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81156330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b188faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (5159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be142c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be142c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be142c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e53933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e5398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e53933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e5391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be1425ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be1425ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be142438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be13ef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be13ef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e5391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e5391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e5391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be13ef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (5162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc9d631eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc9d62ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc9d63262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f9ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f9eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f9ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f9ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc9d5c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc9d5c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc9d5ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc9d25be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc9d25bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f9ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f9ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f9ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc9d25ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (5165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr =
# | ...
# `---data was truncated (10240/124514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555c3d5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555c3d57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555c3d5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f622d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f622d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f622d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f622d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555c3cf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555c3cf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555c3cd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555c3984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555c3984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f622d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f622d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f622d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555c3984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (5166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4534c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4534c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4534c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d73649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d73649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d73631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a45345ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a45345ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4534438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4530f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4530f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d73632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4530f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (5167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055963fa9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055963fa9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055963faa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4a6e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4a6e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4a6e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4a6e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055963fa35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055963fa35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055963fa1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055963f6c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055963f6c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4a6e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4a6e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4a6e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055963f6c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (5170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d6890beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d68908e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d6890c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe97801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9780725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe97801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe978003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d688a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d688a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d688868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d68535e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d68535b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe978004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9780050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9780050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d68535a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (5173 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5a910ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5a9109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5a910d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f561a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f561a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f561a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f561a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5a90a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5a90a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5a90878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5a8d36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5a8d36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f561a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f561a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f561a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5a8d36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (5179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570df36deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570df36ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570df36e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9801533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9801533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570df303bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570df303a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570df2e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570def97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570def97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f980151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570def97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (5182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d700abceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d700ab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d700abd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f9af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d700a52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d700a52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d700a378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7006e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7006e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7006e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (5183 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i
# | ...
# `---data was truncated (10240/120468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056123dfa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056123df9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056123dfa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c05249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c05249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c05231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056123df37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056123df37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056123df1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056123dbcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056123dbcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c05232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056123dbcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (5185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64
# | ...
# `---data was truncated (10240/97248) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1b1c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1b1c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1b1c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0752649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0752649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0752631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1b1c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1b1c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1b1bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1b18a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1b18a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0752632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07526330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1b18a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (5186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/78328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572cbbfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572cbbfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572cbbfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d1df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d1df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d1df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d1df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572cbb93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572cbb93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572cbb788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572cb827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572cb827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d1df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d1df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d1df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572cb827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (5188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c46148deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c46148ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c46148e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd43f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd43f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd43f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd43f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c461423bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c461423a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4614088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4610b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4610b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd43f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd43f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd43f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4610b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (5189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbdcfadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbdcfaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbdcfae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad0ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad0caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad0ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad0ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbdcf43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbdcf43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbdcf288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbdcbd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbdcbd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad0ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad0ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad0ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbdcbd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (5193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055600ddd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055600ddd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055600ddd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc13a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc13a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc13a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc13a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055600dd6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055600dd6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055600dd528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055600da01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055600da01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc13a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc13a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc13a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055600da01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (5195 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574210d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574210d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574210d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d24505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d2455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d24505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d244ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055742106bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055742106ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574210508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557420cffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557420cffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d244eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d244ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d244ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557420cffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (5201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055929c1f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055929c1f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055929c1f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5812249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58122a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5812249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5812231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055929c18bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055929c18ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055929c1708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055929be1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055929be1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5812232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58122330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58122330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055929be1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (5203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b82724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b82721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b8272562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d71f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d71f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d71f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d71f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b826babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b826baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b8269f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b8234ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b8234eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d71f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d71f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d71f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b8234ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (5205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/136489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcac168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcac165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcac16962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac31733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac3178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac31733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac3171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcac0febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcac0fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcac0e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcabd92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcabd92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac3171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac3171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac3171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcabd92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (5208 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a0f88beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a0f888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a0f88c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40d2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40d28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40d2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40d2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a0f821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a0f821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a0f8068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a0f4b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a0f4b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40d2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40d28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40d28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a0f4b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (5209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055796f898eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055796f895e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055796f89962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055796f82ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055796f82ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055796f8138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055796f4c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055796f4c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055796f4c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (5210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561044bbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561044bb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561044bbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3e1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3e10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3e1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3e1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561044b52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561044b52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561044b378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610447e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610447e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3e1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3e10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3e10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610447e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (5213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e7e666eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e7e663e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e7e66762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1987a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1987aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1987a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1987a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e7e5fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e7e5fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e7e5e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e7e290e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e7e290b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1987a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1987a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1987a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e7e290a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (5217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563689fd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563689fcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563689fd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7705c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7705ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7705c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7705c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563689f68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563689f68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563689f4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563689bfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563689bfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7705c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7705c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7705c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563689bfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (5219 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f605afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f605ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f605b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc5d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc5d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc5d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc5d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f60545bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f60545a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f6052a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f601d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f601d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc5d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc5d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc5d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f601d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (5223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f64a84deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f64a84ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f64a84e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f65a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f65aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f65a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f65a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f64a7e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f64a7e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f64a7c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f64a477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f64a477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f65a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f65a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f65a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f64a477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (5224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16
# | ...
# `---data was truncated (10240/62095) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604a0b4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604a0b47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604a0b4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f35c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f35ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f35c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f35c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604a0ae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604a0ae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604a0ac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604a0774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604a0774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f35c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f35c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f35c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604a0774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (5226 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.
# | ...
# `---data was truncated (10240/78690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627f92b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627f92b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627f92b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f319cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f319cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f319cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f319cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627f9249bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627f9249a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627f922e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627f8edde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627f8eddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f319cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f319cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f319cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627f8edda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (5227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d7f71feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d7f71ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d7f72062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9c4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9c46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9c4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9c4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d7f6b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d7f6b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d7f69a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d7f349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d7f349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9c4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9c46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9c46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d7f349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (5230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/135337) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563af70c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563af70bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563af70c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8942049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8942049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8942031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563af7057bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563af7057a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563af703c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563af6cebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563af6cebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8942032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563af6ceba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (5232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653ada14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653ada11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653ada1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad34933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad3498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad34933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad3491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653ad9aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653ad9aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653ad98f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653ad63ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653ad63eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad3491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad3491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad3491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653ad63ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (5234 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbc2f96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbc2f93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbc2f9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffad6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffad658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffad6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffad651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbc2f2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbc2f2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbc2f118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbc2bc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbc2bc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffad651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffad651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffad651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbc2bc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (5240 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ebab2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ebab2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ebab2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8baf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8baf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8baf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8baf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ebaac4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ebaac4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ebaaa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557eba758e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557eba758b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8baf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8baf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8baf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eba758a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (5243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea6cf45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea6cf42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea6cf4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2015649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20156a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2015649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2015631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea6cedbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea6cedba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea6cec08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea6cb6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea6cb6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2015632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20156330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20156330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea6cb6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (5244 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ac12eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ac12e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ac12ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ee6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ee6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ee6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ee6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ac1282bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ac1282a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ac12678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ac0f16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ac0f16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ee6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ee6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ee6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ac0f16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (5245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055663b42feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055663b42ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055663b43062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe42c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe42c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe42c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe42c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055663b3c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055663b3c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055663b3aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055663b059e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055663b059b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe42c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe42c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe42c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055663b059a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (5247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628e8664eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628e8661e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628e866562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f843ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f843ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f843ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f843ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628e85fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628e85faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628e85df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628e828ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628e828eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f843ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f843ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f843ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628e828ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (5249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>,
# | ...
# `---data was truncated (10240/16521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7bde7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7bde79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7bde7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c99305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c9935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c99305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c992ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7bde12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7bde12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7bddf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7bdaa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7bdaa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c992eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c992ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c992ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7bdaa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (5252 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = l
# | ...
# `---data was truncated (10240/23247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eccc77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558eccc74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558eccc7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb220105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb22015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb220105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2200ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eccc0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558eccc0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558eccbf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ecc8a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ecc8a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2200eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2200ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2200ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ecc8a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (5253 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.v
# | ...
# `---data was truncated (10240/58683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c29636aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c296367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c29636b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c296300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c296300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2962e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c295f94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c295f94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c295f94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (5254 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac2ab93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac2ab90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac2ab9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53b1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53b198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53b1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53b191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac2ab29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac2ab29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac2ab0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac2a7bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac2a7bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53b191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53b191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53b191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac2a7bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (5255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue
# | ...
# `---data was truncated (10240/81764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056063caedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056063caeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056063caee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcea0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcea00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcea0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcea0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056063ca83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056063ca83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056063ca688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056063c717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056063c717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcea0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcea00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcea00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056063c717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (5256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale
# | ...
# `---data was truncated (10240/79489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055854a756eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055854a753e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055854a75762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedadf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedadf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedadf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedadf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055854a6ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055854a6eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055854a6d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055854a380e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055854a380b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedadf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedadf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedadf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055854a380a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (5261 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056294e9f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056294e9f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056294e9f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f452a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f452a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f452a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f452a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056294e98cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056294e98ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056294e9718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056294e620e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056294e620b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f452a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f452a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f452a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056294e620a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (5267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559503836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559503833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055950383762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e38533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e3858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e38533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e3851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595037ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595037cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595037b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559503460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559503460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e3851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e3851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e3851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559503460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (5271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.add
# | ...
# `---data was truncated (10240/86739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f870dafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f870dace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f870db062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f415e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f415e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f415e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f415e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f870d45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f870d45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f870d2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8709d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8709d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f415e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f415e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f415e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8709d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (5274 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa07012eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa0700fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa0701362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdee7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdee7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdee7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdee7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa06fa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa06fa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa06f8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa06c3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa06c3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdee7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdee7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdee7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa06c3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (5275 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dba1a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dba19ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dba1a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5af2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5af298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5af2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5af291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dba137bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dba137a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dba11c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558db9dcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558db9dcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5af291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5af291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5af291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db9dcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (5276 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f3f842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f3f83fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f3f84362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effc5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effc52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effc5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effc5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f3f7d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f3f7d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f3f7bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f3f46ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f3f46cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effc5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effc52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effc52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f3f46ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (5279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646dc401eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646dc3fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646dc40262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54bac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54baca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54bac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54bac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646dc397bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646dc397a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646dc37c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646dc02be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646dc02bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54bac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54bac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54bac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646dc02ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (5281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f611628eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f611625e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f61162962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9be5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9be5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9be5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9be5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6115bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6115bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6115a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f611252e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f611252b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9be5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9be5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9be5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f611252a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (5285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564608e2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564608e2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564608e2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f224a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f224a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f224a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f224a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564608dc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564608dc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564608da98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564608a58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564608a58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f224a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f224a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f224a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564608a58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (5286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055741e790eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055741e78de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055741e79162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6282649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6282649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6282631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055741e726bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055741e726a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055741e70b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055741e3bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055741e3bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6282632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62826330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055741e3baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (5289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c8d170eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c8d16de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c8d17162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ea5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ea58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ea5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ea5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c8d106bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c8d106a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c8d0eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c8cd9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c8cd9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ea5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ea58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ea58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c8cd9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (5291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/88444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc9e70beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc9e708e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc9e70c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6571649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65716a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6571649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6571631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc9e6a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc9e6a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc9e6868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc9e335e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc9e335b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6571632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65716330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65716330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc9e335a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (5292 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0c13e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0c13e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0c13e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45bd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45bd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45bd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45bd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0c137bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0c137ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0c13608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0c100fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0c100fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45bd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45bd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45bd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0c100fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (5293 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd4eebfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd4eebce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd4eec062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd167333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd16738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd167333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd16731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd4ee55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd4ee55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd4ee3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd4eae9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd4eae9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd16731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd16731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd16731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd4eae9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (5295 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634187ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634187fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056341880062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f825c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f825c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f825c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f825c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563418795bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563418795a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056341877a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563418429e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563418429b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f825c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f825c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f825c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563418429a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (5298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616202eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616202e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616202ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe56c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe56c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe56c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe56c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561620282bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561620282a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616202678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056161ff16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056161ff16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe56c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe56c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe56c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056161ff16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (5301 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565455baaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565455ba7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565455bab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1170f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1170f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1170f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1170f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565455b40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565455b40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565455b258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654557d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654557d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1170f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1170f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1170f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654557d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (5302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056103f2c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056103f2c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056103f2c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c5d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c5d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c5d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c5d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056103f25cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056103f25ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056103f2418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056103eef0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056103eef0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c5d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c5d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c5d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056103eef0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (5303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   
# | ...
# `---data was truncated (10240/92362) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055906cc14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055906cc11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055906cc1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feefaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feefaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feefaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feefaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055906cbaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055906cbaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055906cb8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055906c83ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055906c83eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feefaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feefaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feefaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055906c83ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (5304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfm
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587fa2deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587fa2dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587fa2df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3eb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3eb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3eb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3eb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587fa274bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587fa274a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587fa2598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587f9f08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587f9f08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3eb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3eb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3eb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587f9f08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (5305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/63177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644720a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644720a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644720a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3374e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3374ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3374e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3374e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056447203cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056447203ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644720218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564471cd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564471cd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3374e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3374e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3374e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564471cd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (5306 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e1e60deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e1e60ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e1e60e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9be533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9be58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9be533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9be51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e1e5a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e1e5a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e1e5888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e1e237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e1e237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9be51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9be51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9be51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e1e237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (5308 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea2c28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea2c25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea2c2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c66533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c6658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c66533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c6651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea2bbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea2bbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea2ba38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea2852e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea2852b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c6651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c6651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c6651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea2852a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (5309 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6b9484eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6b9481e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6b948562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f054aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f054aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f054aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f054aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6b941abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6b941aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6b93ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6b90aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6b90aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f054aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f054aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f054aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6b90aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (5311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df8bb0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df8bb0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df8bb0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc42133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc4218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc42133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc4211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df8baa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df8baa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df8ba898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df8b738e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df8b738b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc4211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc4211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc4211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df8b738a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (5312 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c31b380eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c31b37de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c31b38162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0435c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0435ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0435c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0435c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c31b316bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c31b316a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c31b2fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c31afaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c31afaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0435c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0435c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0435c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c31afaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (5313 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563251969eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563251966e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056325196a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa640133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa64018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa640133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa64011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632518ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632518ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632518e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563251593e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563251593b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa64011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa64011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa64011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563251593a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (5317 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d496c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d496c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d496c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9fdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d496bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d496bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d496ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d496854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d496854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d496854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (5319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %o
# | ...
# `---data was truncated (10240/76627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e78c294eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e78c291e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e78c29562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ed6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ed6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ed6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ed6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e78c22abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e78c22aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e78c20f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e78bebee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e78bebeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ed6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ed6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ed6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e78bebea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (5320 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e664044eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e664041e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e66404562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79e3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79e3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79e3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79e3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e663fdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e663fdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e663fbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e663c6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e663c6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79e3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79e3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79e3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e663c6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (5321 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056092890eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056092890be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056092890f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe63bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe63bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe63bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe63bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609288a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609288a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609288898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560928538e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560928538b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe63bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe63bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe63bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560928538a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (5324 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# |  #0 0x000055680d26feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055680d26ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055680d27062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0573249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0573249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0573231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055680d205bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055680d205a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055680d1ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055680ce99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055680ce99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0573232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055680ce99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (5326 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563684848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563684845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056368484962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8da01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8da0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8da01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8da003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636847debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636847dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636847c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563684472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563684472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8da004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8da0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8da0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563684472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (5327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9978a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f99789fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9978a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce79f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce79f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce79f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce79f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f997838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f997838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f99781d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9974cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9974ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce79f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce79f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce79f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9974cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (5328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bf6210eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bf620de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bf621162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d99f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d99f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d99f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d99f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bf61a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bf61a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bf618b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bf5e3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bf5e3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d99f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d99f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d99f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bf5e3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (5330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/79671) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f70059eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f70056e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f7005a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9142e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9142e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9142e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9142e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6ffefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f6ffefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f6ffd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f6fc83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f6fc83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9142e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9142e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9142e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f6fc83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (5332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vr
# | ...
# `---data was truncated (10240/96265) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f90a8c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f90a8c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f90a8c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15f3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f90a859bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f90a859a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f90a83e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f90a4ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f90a4edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15f30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f90a4eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (5334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592d5a6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592d5a6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592d5a6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592d5a04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592d5a04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592d59e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592d5698e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592d5698b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592d5698a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (5336 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/51751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559934a37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559934a34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559934a3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aff31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599349cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599349cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599349b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559934661e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559934661b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0aff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aff31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559934661a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (5341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4f5254eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4f5251e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4f525562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bb4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bb4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bb4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bb4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4f51eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4f51eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4f51cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4f4e7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4f4e7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bb4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bb4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bb4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4f4e7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (5342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564affa1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564affa1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564affa1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4975533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4975533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aff9b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aff9b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aff9988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aff647e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aff647b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f497551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aff647a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (5343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608244c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608244c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608244c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcc5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcc54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcc5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcc5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056082445bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056082445ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608244408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608240efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608240efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcc5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcc54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcc54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608240efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (5345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eee7562eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eee755fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eee756362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8448933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f844898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8448933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f844891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eee74f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eee74f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eee74dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eee718ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eee718cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f844891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f844891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f844891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eee718ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (5349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcreate_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %2, <vscale x 4 x bfloat> %1, i64 4)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %4, <vscale x 4 x bfloat> %1, i64 4)
# |   %6 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %5, <vscale x 4 x bfloat> %2, i64 8)
# |   %7 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %6, <vscale x 4 x bfloat> %3, i64 12)
# |   ret <vscale x 16 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v4.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v5.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v6.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v7.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x bfloat> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x bfloat> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x bfloat> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x bfloat> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x bfloat>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x bfloat>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x bfloat>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x bfloat>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %9 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %8, <vscale x 4 x bfloat> %1, i64 4)
# |   %10 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %9, <vscale x 4 x bfloat> %2, i64 8)
# |   %11 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %10, <vscale x 4 x bfloat> %3, i64 12)
# |   %12 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %11, <vscale x 4 x bfloat> %4, i64 16)
# |   %13 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %12, <vscale x 4 x bfloat> %5, i64 20)
# |   %14 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %13, <vscale x 4 x bfloat> %6, i64 24)
# |   %15 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %14, <vscale x 4 x bfloat> %7, i64 28)
# |   ret <vscale x 32 x bfloat> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %2, <vscale x 8 x bfloat> %1, i64 8)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %4, <vscale x 8 x bfloat> %1, i64 8)
# |   %6 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %5, <vscale x 8 x bfloat> %2, i64 16)
# |   %7 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %6, <vscale x 8 x bfloat> %3, i64 24)
# |   ret <vscale x 32 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m4_bf16m8(<vscale x 16 x bfloat> %v0, <vscale x 16 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %2, <vscale x 16 x bfloat> %1, i64 16)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vcreate_v_bf16mf4x2(<vscale x 1 x bfloat> %v0, <vscale x 1 x bfloat> %v1) #0 {
# | entry:
# |   %v0.add
# | ...
# `---data was truncated (10240/71275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ae76c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ae76c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ae76c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe572333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe57238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe572333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe57231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ae765dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ae765da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ae76428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ae72f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ae72f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe57231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe57231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe57231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ae72f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (5350 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f01d403eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f01d400e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f01d40462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed80649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed80649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed80631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f01d399bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f01d399a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f01d37e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f01d02de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f01d02db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed80632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f01d02da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (5351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d87b81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d87b7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d87b8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe13db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe13db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe13db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe13db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d87b17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d87b17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d87afc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d877abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d877abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe13db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe13db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe13db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d877aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (5353 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i6
# | ...
# `---data was truncated (10240/67158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629df6dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629df6d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629df6dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a95e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a95ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a95e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a95e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629df672bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629df672a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629df6578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629df306e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629df306b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a95e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a95e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a95e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629df306a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (5354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557034f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557034f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557034f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f351261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35126725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f351261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3512603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555703489bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555703489a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055570346e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055570311de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055570311db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3512604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35126050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35126050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055570311da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (5355 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d018c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d018bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d018c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa189d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa189d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa189d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa189d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d01856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d01856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d0183b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d014eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d014eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa189d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa189d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa189d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d014eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (5358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <v
# | ...
# `---data was truncated (10240/65080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4e258eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4e258be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4e258f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51f871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4e2524bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4e2524a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4e25098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4e21b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4e21b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51f871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4e21b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (5361 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,10
# | ...
# `---data was truncated (10240/48393) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055878e1e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055878e1dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055878e1e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99b9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99b9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99b9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99b9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055878e176bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055878e176a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055878e15b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055878de0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055878de0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99b9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99b9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99b9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055878de0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (5364 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c26383eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c26380e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c2638462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc474249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4742a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc474249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc474231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c26319bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c26319a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c262fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c25fade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c25fadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc474232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4742330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4742330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c25fada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (5369 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2270b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2270afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2270b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b21049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b210a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b21049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b21031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e227048bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e227048a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e22702d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e226cdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e226cdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b21032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b210330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b210330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e226cdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (5372 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ec491beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ec4918e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ec491c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0799933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f079998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0799933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f079991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ec48b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ec48b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ec48968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ec4545e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ec4545b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f079991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f079991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f079991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ec4545a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (5373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f63662eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f63662be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f63662f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3390649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3390649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3390631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6365c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6365c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6365a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f636258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f636258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3390632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33906330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f636258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (5381 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637e4511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637e450ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637e451262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f586361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58636725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f586361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5863603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637e44a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637e44a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637e448c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637e413be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637e413bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5863604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58636050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58636050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637e413ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (5382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub
# | ...
# `---data was truncated (10240/84979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583ae667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583ae664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583ae66862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aa8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aa818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aa8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aa811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583ae5fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583ae5fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583ae5e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583ae291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583ae291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3aa811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aa811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aa811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583ae291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (5383 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556aee277eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556aee274e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556aee27862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd47d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd47d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd47d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd47d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556aee20dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556aee20da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556aee1f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556aedea1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556aedea1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd47d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd47d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd47d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556aedea1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (5387 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/100960) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aa7b28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557aa7b25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557aa7b2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1ca049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1ca0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1ca049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1ca031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aa7abebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557aa7abea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557aa7aa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557aa7752e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557aa7752b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1ca032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1ca0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1ca0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aa7752a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (5388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ad1c30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ad1c2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ad1c3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc790733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc79078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc790733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc79071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ad1bc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ad1bc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ad1bab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ad185ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ad185ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc79071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc79071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc79071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ad185aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (5391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcca9e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcca9e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcca9e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc41c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc41c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc41c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc41c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcca979bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcca979a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcca95e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcca60de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcca60db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc41c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc41c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc41c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcca60da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (5392 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/94157) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055add6b04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055add6b01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055add6b0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f177e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f177e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f177e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f177e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055add6a9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055add6a9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055add6a7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055add672ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055add672eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f177e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f177e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f177e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055add672ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (5394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/51193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a40fcbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a40fcbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a40fcbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a40fc54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a40fc54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a40fc398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a40f8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a40f8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a40f8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (5395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d518d17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d518d14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d518d1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39a7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39a7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39a7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39a7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d518cadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d518cada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d518c928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d518941e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d518941b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39a7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39a7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39a7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d518941a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (5396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c29431eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c2942ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c2943262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ace049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ace0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ace049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ace031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c293c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c293c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c293ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c2905be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c2905bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ace032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ace0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ace0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c2905ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (5397 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/81507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c55ed3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c55ed0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c55ed462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5316049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5316049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5316031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c55e69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c55e69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c55e4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c55afde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c55afdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5316032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c55afda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (5400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556abc113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556abc110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556abc11462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbde0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbde0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbde0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbde0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556abc0a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556abc0a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556abc08e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556abbd3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556abbd3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbde0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbde0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbde0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556abbd3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (5401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f550dddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f550ddae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f550dde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdb2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdb24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdb2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdb2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f550d73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f550d73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f550d588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f550a07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f550a07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdb2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdb24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdb24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f550a07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (5402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/97514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daf0ea8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daf0ea5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daf0ea962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42c1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42c1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42c1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42c1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daf0e3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daf0e3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daf0e238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daf0ad2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daf0ad2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42c1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42c1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42c1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daf0ad2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (5404 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d449da3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d449da0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d449da462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb84449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb84449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb84431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d449d39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d449d39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d449d1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4499cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4499cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb84432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4499cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (5408 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629cd629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629cd626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629cd62a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3bbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3bbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3bbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3bbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629cd5bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629cd5bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629cd5a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629cd253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629cd253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3bbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3bbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3bbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629cd253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (5410 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8dbdb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8dbdb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8dbdba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb72821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7282725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb72821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb728203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8dbd4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8dbd4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8dbd348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8db9e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8db9e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb728204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7282050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7282050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8db9e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (5411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/54480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b77103aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b771037e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b77103b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc38e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc38ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc38e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc38e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b770fd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b770fd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b770fb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b770c64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b770c64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc38e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc38e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc38e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b770c64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (5412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %b
# | ...
# `---data was truncated (10240/38307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630b4677eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630b4674e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630b467862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff77c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff77c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630b460dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630b460da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630b45f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630b42a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630b42a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff77c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630b42a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (5413 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/70979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a00249eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a00246e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a0024a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4036c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4036ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4036c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4036c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a001dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a001dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a001c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589ffe73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589ffe73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4036c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4036c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4036c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ffe73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (5415 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db09a62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db09a5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db09a6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0459133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f045918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0459133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f045911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db099f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db099f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db099dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db0968ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db0968cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f045911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f045911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f045911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db0968ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (5418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f132045eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f132042e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f13204662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb021933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb02198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb021933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb02191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f131fdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f131fdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f131fc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f131c6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f131c6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb02191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb02191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb02191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f131c6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (5419 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16
# | ...
# `---data was truncated (10240/93458) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ffc326eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ffc323e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ffc32762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc75f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc75f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc75f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc75f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ffc2bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ffc2bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ffc2a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ffbf50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ffbf50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc75f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc75f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc75f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ffbf50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (5421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfa
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601c8b47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601c8b44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601c8b4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb539133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb53918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb539133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb53911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601c8addbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601c8adda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601c8ac28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601c8771e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601c8771b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb53911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb53911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb53911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601c8771a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (5422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ba139feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ba139ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ba13a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0faf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0faf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0faf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0faf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ba1335bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ba1335a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ba131a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ba0fc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ba0fc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0faf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0faf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0faf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ba0fc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-neon-fma.c (5423 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf    -target-abi aapcs    -target-cpu cortex-a7    -mfloat-abi hard    -ffreestanding    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-none-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %accum.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %accum, ptr %accum.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %accum.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %accum.addr = alloca <4 x float>, align 8
# |   %lhs.addr = alloca <4 x float>, align 8
# |   %rhs.addr = alloca <4 x float>, align 8
# |   store <4 x float> %accum, ptr %accum.addr, align 8
# |   store <4 x float> %lhs, ptr %lhs.addr, align 8
# |   store <4 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x float>, ptr %accum.addr, align 8
# |   %1 = load <4 x float>, ptr %lhs.addr, align 8
# |   %2 = load <4 x float>, ptr %rhs.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store <4 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <2 x float>, align 8
# |   %__p1.addr.i.i = alloca <2 x float>, align 8
# |   %__p2.addr.i.i = alloca <2 x float>, align 8
# |   %__ret.i.i = alloca <2 x float>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <2 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <2 x float> %7, ptr %__p2.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %11 = bitcast <8 x i8> %8 to <2 x float>
# |   %12 = bitcast <8 x i8> %9 to <2 x float>
# |   %13 = bitcast <8 x i8> %10 to <2 x float>
# |   %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11)
# |   store <2 x float> %14, ptr %ref.tmp.i.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8
# |   store <2 x float> %15, ptr %__ret.i.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i.i, align 8
# |   store <2 x float> %16, ptr %__ret.i, align 8
# |   %17 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x float>, align 8
# |   %__p1.addr.i.i = alloca <4 x float>, align 8
# |   %__p2.addr.i.i = alloca <4 x float>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 8
# |   %ref.tmp.i.i = alloca <16 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 8
# |   %.compoundliteral.i = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <4 x float> %9, ptr %__p2.addr.i.i, align 8
# |   %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8
# |   %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8
# |   %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8
# |   %13 = bitcast <16 x i8> %10 to <4 x float>
# |   %14 = bitcast <16 x i8> %11 to <4 x float>
# |   %15 = bitcast <16 x i8> %12 to <4 x float>
# |   %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13)
# |   store <4 x float> %16, ptr %ref.tmp.i.i, align 8
# |   %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8
# |   store <4 x float> %17, ptr %__ret.i.i, align 8
# |   %18 = load <4 x float>, ptr %__ret.i.i, align 8
# |   store <4 x float> %18, ptr %__ret.i, align 8
# |   %19 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %19
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564975ce3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564975ce0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564975ce462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4f0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4f0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4f0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4f0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564975c79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564975c79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564975c5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056497590de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056497590db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4f0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4f0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4f0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056497590da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (5427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align
# | ...
# `---data was truncated (10240/102872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5d1200eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5d11fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5d120162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb87e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb87e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb87e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb87e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5d1196bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5d1196a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5d117b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5d0e2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5d0e2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb87e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb87e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb87e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5d0e2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (5429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdb7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cdb7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cdb7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf79649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf796a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf79649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf79631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdb791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cdb791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cdb7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cdb425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cdb425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf79632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf796330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf796330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdb425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (5430 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558089431eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055808942ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055808943262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f242881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24288725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f242881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2428803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580893c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580893c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580893ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055808905be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055808905bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2428804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24288050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24288050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055808905ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (5431 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0322b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0322b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0322ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f623e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f623e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f623e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f623e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d03224fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d03224fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0322348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d031ee3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d031ee3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f623e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f623e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f623e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d031ee3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (5434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056231aa1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056231aa19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056231aa1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f988dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f988dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f988dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f988dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056231a9b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056231a9b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056231a9978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056231a646e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056231a646b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f988dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f988dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f988dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056231a646a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (5437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648d4655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648d4652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648d465662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1fbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648d45ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648d45eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648d45d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648d427fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648d427fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1fbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648d427fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (5438 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   st
# | ...
# `---data was truncated (10240/110292) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0ac2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b0ac2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0ac2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e4c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e4c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e4c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e4c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0abc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b0abc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b0aba88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b0a857e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b0a857b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e4c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e4c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e4c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0a857a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (5439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/83080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e39bfcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e39bfc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e39bfcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae1021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae102725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae1021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae10203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e39bf61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e39bf61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e39bf468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e39bbf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e39bbf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae10204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae102050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae102050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e39bbf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (5441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl
# | ...
# `---data was truncated (10240/78896) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cab0d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cab0d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cab0d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f250bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f250bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f250bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f250bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cab06abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cab06aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cab04f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563caacfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563caacfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f250bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f250bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f250bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563caacfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (5442 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8e489aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8e4897e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8e489b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89b611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8e4830bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8e4830a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8e48158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8e44c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8e44c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89b611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8e44c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (5447 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaa
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efe9ca8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efe9ca5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efe9ca962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f1b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f1b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f1b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f1b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efe9c3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efe9c3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efe9c238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efe98d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efe98d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f1b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f1b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f1b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efe98d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (5449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed00131eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed0012ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed0013262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8e1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8e12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8e1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8e1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed000c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed000c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed000ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecffd5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecffd5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8e1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8e12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8e12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecffd5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (5452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c05067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c05064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c0506862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0860649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0860649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0860631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c04ffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c04ffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c04fe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c04c91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c04c91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0860632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08606330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c04c91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (5453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632a31b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632a31b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632a31b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e33933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e3398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e33933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e3391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632a314dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632a314da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632a31328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632a2de1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632a2de1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e3391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e3391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e3391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632a2de1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (5454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621cf07deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621cf07ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621cf07e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa355d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa355d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa355d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa355ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621cf013bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621cf013a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621ceff88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621ceca7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621ceca7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa355ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa355cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa355cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621ceca7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (5456 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/79853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb29f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb29f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb29f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f542e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f542e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f542e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f542e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb29f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb29f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb29f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb29bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb29bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f542e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f542e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f542e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb29bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (5457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e1ca22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e1ca1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e1ca2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d0e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d0e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d0e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d0e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e1c9b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e1c9b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e1c99d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e1c64ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e1c64cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6d0e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d0e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d0e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e1c64ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (5459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x 
# | ...
# `---data was truncated (10240/70013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ffe9b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ffe9b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ffe9b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa40b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa40b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa40b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa40b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ffe94bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ffe94ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ffe9308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ffe5dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ffe5dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa40b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa40b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa40b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ffe5dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (5466 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30710aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c307107e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c30710b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8dda933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8dda98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8dda933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8dda91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3070a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3070a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3070858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c306d34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c306d34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8dda91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8dda91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8dda91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c306d34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (5468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1dc9b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1dc9ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1dc9b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28aa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28aa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28aa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28aa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1dc946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1dc946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1dc92b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1dc5dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1dc5dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28aa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28aa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28aa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1dc5daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (5469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fd2d1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fd2d1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fd2d1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa9f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa9f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa9f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa9f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fd2cb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fd2cb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fd2c998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fd2948e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fd2948b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa9f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa9f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa9f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fd2948a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (5470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c5a48aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c5a487e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c5a48b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90af031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c5a420bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c5a420a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c5a4058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c5a0b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c5a0b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90af0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c5a0b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (5473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nx
# | ...
# `---data was truncated (10240/83629) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f9f977eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f9f974e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f9f97862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f555b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f555b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f555b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f555b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9f90dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f9f90da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f9f8f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f9f5a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f9f5a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f555b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f555b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f555b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9f5a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (5476 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = al
# | ...
# `---data was truncated (10240/41670) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b097546eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b097543e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b09754762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a78933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a78933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0974dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0974dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0974c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b097170e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b097170b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a7891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b097170a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (5477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ee1f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ee1f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ee1f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f435441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43544725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f435441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4354403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ee1ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ee1ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ee1ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ee1b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ee1b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4354404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43544050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43544050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ee1b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (5478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562d0251eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562d024ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562d025262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24a7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24a715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24a7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24a70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d01e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562d01e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562d01cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562cfe7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562cfe7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24a70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24a70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24a70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562cfe7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (5479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625d8a70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625d8a6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625d8a7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd87a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd87aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd87a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd87a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d8a06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625d8a06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625d89eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625d869ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625d869ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd87a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd87a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd87a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d869aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (5481 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055563254eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055563254be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055563254f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6264849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6264849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6264831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556324e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556324e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556324c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555632178e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555632178b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6264832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62648330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555632178a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (5485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c314180eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c31417de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c31418162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe12bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe12bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe12bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe12bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c314116bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c314116a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3140fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c313daae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c313daab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe12bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe12bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe12bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c313daaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (5488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac1546ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac15469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac1546d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ce0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ce0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ce0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ce0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac15402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac15402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac153e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac15096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac15096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ce0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ce0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ce0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac15096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (5489 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c84fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560c84f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560c84fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a4f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a4f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c8491bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560c8491a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560c84768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560c8125e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560c8125b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a4f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560c8125a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (5491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a66a25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a66a22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a66a2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb959105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb95915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb959105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9590ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a669bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a669bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a669a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a6664fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a6664fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9590eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9590ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9590ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a6664fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (5492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cd4602eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cd45ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cd460362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc771d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc771d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc771d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc771ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cd4598bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cd4598a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cd457d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cd422ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cd422cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc771ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc771cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc771cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cd422ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (5493 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559be05bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559be05b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559be05bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26d891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559be0552bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559be0552a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559be05378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559be01e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559be01e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26d891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559be01e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (5495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x flo
# | ...
# `---data was truncated (10240/78024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596d7fbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d7fbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d7fc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff502733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff50278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff502733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff50271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d7f55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d7f55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d7f3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d7be9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d7be9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff50271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff50271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff50271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d7be9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (5497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i6
# | ...
# `---data was truncated (10240/56171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaf6ed8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaf6ed5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaf6ed962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40baf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40baf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40baf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40baf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaf6e6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaf6e6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaf6e538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaf6b02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaf6b02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40baf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40baf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40baf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaf6b02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (5503 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i)
# |   store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i)
# |   store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i)
# |   store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i)
# |   store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i)
# |   store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i)
# |   store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i)
# |   store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i)
# |   store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i)
# |   store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i)
# |   store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i)
# |   store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i)
# |   st
# | ...
# `---data was truncated (10240/16770) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564248e97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564248e94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564248e9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564248e2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564248e2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564248e128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564248ac1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564248ac1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564248ac1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (5504 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e0f02beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e0f028e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e0f02c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9356133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f935618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9356133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f935611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e0efc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e0efc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e0efa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e0ec55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e0ec55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f935611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f935611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f935611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e0ec55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (5505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557662f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557662f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557662f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb143a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb143a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb143a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb143a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557662ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557662ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557662ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557662b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557662b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb143a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb143a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb143a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557662b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (5506 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4787eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4787ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4787ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb939649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9396a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb939649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb939631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b478784bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b478784a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4787698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b478418e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b478418b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb939632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9396330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9396330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b478418a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (5507 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605918f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605918f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605918f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83cf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83cf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83cf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83cf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056059188dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056059188da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605918728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560591521e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560591521b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83cf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83cf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83cf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560591521a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (5510 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df29167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df29164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df2916862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f315a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f315a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f315a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f315a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df290fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df290fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df290e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df28d91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df28d91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f315a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f315a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f315a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df28d91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (5511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7656e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7656dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7656e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9df649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9df6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9df649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9df631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a765676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a765676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a76565b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a76530ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a76530ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9df632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9df6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9df6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a76530aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (5512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/95445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0955b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0955b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0955b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69f3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69f398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69f3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69f391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c09554abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c09554aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c09552f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0951dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0951deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69f391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69f391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69f391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0951dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (5513 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650f98c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650f98c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650f98c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f875ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f875ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650f9859bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650f9859a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650f983e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650f94ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650f94edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f875ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650f94eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (5515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ad86b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ad86b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ad86b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8b7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8b74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8b7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8b7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ad864bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ad864ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ad86308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ad82dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ad82dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8b7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8b74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8b74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ad82dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (5516 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e05fabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e05fa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e05fac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc9b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc9b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc9b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc9b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e05f41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e05f41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e05f268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e05bd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e05bd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc9b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc9b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc9b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e05bd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (5517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0d12a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0d12a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0d12a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a73b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a73b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a73b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a73b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0d123cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0d123ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0d12218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0d0ed0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0d0ed0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a73b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a73b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a73b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0d0ed0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (5518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a74102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a740ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a7410362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8387649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83876a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8387649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8387631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a74098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a74098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a7407d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a73d2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a73d2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8387632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83876330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83876330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a73d2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (5521 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i)
# |   %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8>
# |   store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i)
# |   %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i)
# |   %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8>
# |   store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i)
# |   %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b10be06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b10be03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b10be0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5896a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5896aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5896a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5896a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b10bd9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b10bd9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b10bd818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b10ba30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b10ba30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5896a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5896a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5896a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b10ba30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (5524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba4c73beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba4c738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba4c73c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f600b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f600b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f600b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f600b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba4c6d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba4c6d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba4c6b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba4c365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba4c365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f600b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f600b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f600b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba4c365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (5525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/51759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce78b07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce78b04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce78b0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7446333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f744638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7446333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f744631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce78a9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce78a9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce78a828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce78731e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce78731b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f744631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f744631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f744631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce78731a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (5526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd4854feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd4854ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd4855062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b56d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b56d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b56d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b56d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd484e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd484e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd484ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd48179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd48179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b56d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b56d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b56d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd48179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (5527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a77ce1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a77cdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a77ce262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21ecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21ecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21ecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21ecc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a77c77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a77c77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a77c5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a7790be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a7790bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21ecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21ecc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21ecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a7790ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (5528 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, a
# | ...
# `---data was truncated (10240/98149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb46276eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb46273e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb4627762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d22249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d222a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d22249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d22231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb4620cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb4620ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb461f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb45ea0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb45ea0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d22232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d222330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d222330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb45ea0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (5530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055925f254eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055925f251e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055925f25562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc54f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc54f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc54f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc54f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055925f1eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055925f1eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055925f1cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055925ee7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055925ee7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc54f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc54f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc54f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055925ee7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (5531 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/70971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc76908eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc76905e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc7690962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6b9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6b9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6b9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6b9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc7689ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc7689ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc768838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc76532e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc76532b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6b9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6b9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6b9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc76532a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (5533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a80f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645a80efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645a80f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f381ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f381eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f381ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f381ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a8088bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645a8088a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645a806d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645a7d1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645a7d1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f381ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f381ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f381ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a7d1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (5535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650f4ca0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650f4c9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650f4ca162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84a6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84a6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84a6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84a6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650f4c36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650f4c36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650f4c1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650f48cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650f48cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84a6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84a6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84a6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650f48caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (5536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f56af80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f56af7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f56af8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ed1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ed10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ed1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ed1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f56af16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f56af16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f56aefb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f56abaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f56abaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ed1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ed10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ed10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f56abaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (5537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f15655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f15652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f1565662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd20649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd206a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd20649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd20631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f155ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f155eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f155d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f1527fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f1527fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd20632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd206330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd206330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f1527fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (5539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/64341) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc0852deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc0852ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc0852e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12a771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc084c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc084c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc084a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc08157e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc08157b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12a771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc08157a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (5541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555769e97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555769e94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555769e9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f9c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f9c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f9c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f9c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555769e2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555769e2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555769e128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555769ac1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555769ac1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f9c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f9c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f9c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555769ac1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (5542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ada791eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ada78ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ada79262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aac831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ada727bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ada727a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ada70c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ada3bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ada3bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3aac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aac8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ada3bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (5543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe82096eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe82093e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe8209762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31c2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31c278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31c2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31c271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe8202cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe8202ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe820118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe81cc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe81cc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31c271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31c271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31c271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe81cc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (5545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f25a313eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f25a310e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f25a31462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1cfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f25a2a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f25a2a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f25a28e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f259f3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f259f3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f259f3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (5546 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a7afb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a7afb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a7afb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe985733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe98578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe985733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe98571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a7af4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a7af4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a7af308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a7abdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a7abdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe98571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe98571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe98571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a7abdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (5547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c1604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9c1601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9c160562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cd2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cd2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cd2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cd2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c159abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9c159aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9c157f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9c122ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9c122eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cd2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cd2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cd2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9c122ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (5550 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f207daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f207d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f207db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a99333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a9938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a99333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a9931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f20770bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f20770a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f207558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f20404e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f20404b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a9931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a9931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a9931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f20404a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (5551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a9c7abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a9c7a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a9c7ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d5ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d5ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d5ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d5ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a9c741bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a9c741a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a9c7268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a9c3d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a9c3d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d5ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d5ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d5ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a9c3d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (5552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056064e334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056064e331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056064e33562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47ca71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056064e2cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056064e2caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056064e2af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056064df5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056064df5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056064df5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (5554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556de9221eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556de921ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556de922262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e6c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e6c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e6c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e6c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556de91b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556de91b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556de919c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556de8e4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556de8e4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e6c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e6c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e6c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556de8e4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (5557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4eda6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4eda6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4eda6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a41c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a41ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a41c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a41c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4eda04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4eda04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4ed9e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4ed698e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4ed698b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a41c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a41c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a41c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ed698a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (5558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f92b68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f92b65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f92b6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d71249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d71249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d71231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f92afebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f92afea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f92ae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f92792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f92792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d71232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d712330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f92792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (5561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3c9c16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3c9c13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3c9c1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd110733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd11078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd110733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd11071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3c9bacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3c9baca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3c9b918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3c9840e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3c9840b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd11071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd11071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd11071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3c9840a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (5562 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a606146eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a606143e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a60614762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feea7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feea778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feea7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feea771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6060dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6060dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6060c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a605d70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a605d70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feea771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feea771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feea771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a605d70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (5564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd4b94ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd4b949e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd4b94d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1826933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f182698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1826933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f182691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd4b8e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd4b8e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd4b8c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd4b576e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd4b576b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f182691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f182691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f182691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd4b576a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (5566 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c8b88feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c8b88ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c8b89062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3adbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3adbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3adbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3adbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c8b825bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c8b825a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c8b80a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c8b4b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c8b4b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3adbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3adbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3adbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c8b4b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (5568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e523408eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e523405e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e52340962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f782be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f782bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f782be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f782be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e52339ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e52339ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5233838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e523032e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e523032b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f782be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f782be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f782be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e523032a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (5571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<
# | ...
# `---data was truncated (10240/119297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7dc088eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7dc085e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7dc08962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ca9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ca9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ca9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ca9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7dc01ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7dc01ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7dc0038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7dbcb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7dbcb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ca9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ca9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ca9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7dbcb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (5572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>
# | ...
# `---data was truncated (10240/51185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580c5e4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580c5e4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580c5e4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa144e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa144ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa144e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa144e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580c5de3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580c5de3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580c5dc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580c5a77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580c5a77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa144e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa144e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa144e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580c5a77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (5575 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566238b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566238b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566238b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd82b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd82b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd82b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd82b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662384dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055662384da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566238328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566234e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566234e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd82b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd82b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd82b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566234e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (5582 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, pt
# | ...
# `---data was truncated (10240/79679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0c193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da0c190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0c19462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4d3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4d358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4d3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4d351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da0c129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da0c129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da0c10e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da0bdbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da0bdbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4d351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4d351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4d351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0bdbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (5584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/134744) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056346e989eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056346e986e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056346e98a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf8fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf8faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf8fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf8fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056346e91fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056346e91fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056346e9048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056346e5b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056346e5b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf8fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf8fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf8fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056346e5b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (5590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fbf7f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fbf7f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fbf7f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd996105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd99615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd996105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9960ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fbf78ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fbf78ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fbf7738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fbf422e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fbf422b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9960eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9960ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9960ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fbf422a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (5593 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80)
# |   %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64)
# |   %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4)
# |   %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1
# |   store <2 x i64> %6, ptr %0, align 8
# |   %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a886dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a886d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a886dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3aec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3aeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3aec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3aec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a88672bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a88672a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a886578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a88306e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a88306b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3aec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3aec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3aec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a88306a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (5594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f181d71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f181d6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f181d7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc894849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8948a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc894849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc894831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f181d07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f181d07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f181cec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f18199be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f18199bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc894832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8948330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8948330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f18199ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (5595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ff3a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ff3a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ff3a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6726733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f672678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6726733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f672671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ff3a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ff3a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ff39f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ff36a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ff36a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f672671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f672671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f672671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ff36a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (5598 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e3ca01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e3c9fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e3ca0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9228f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9228f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9228f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9228eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e3c997bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e3c997a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e3c97c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e3c62be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e3c62bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9228eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9228eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9228eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e3c62ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (5599 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fb0434eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fb0431e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fb043562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44dbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44dbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44dbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44dbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fb03cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fb03caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fb03af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fb005ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fb005eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44dbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44dbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44dbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fb005ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (5603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c85365aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c853657e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c85365b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe148d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe148d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe148d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe148d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8535f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8535f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8535d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c853284e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c853284b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe148d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe148d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe148d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c853284a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (5605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4db28feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4db28ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4db29062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f328a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f328a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f328a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f328a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4db225bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4db225a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4db20a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4daeb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4daeb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f328a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f328a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f328a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4daeb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (5608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2dcff3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2dcff0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2dcff462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b9f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b9f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b9f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b9f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2dcf89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2dcf89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2dcf6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2dcc1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2dcc1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b9f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b9f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b9f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2dcc1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (5609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/66322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a63b53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a63b50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a63b5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01f3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a63ae9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a63ae9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a63ace8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a6377de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a6377db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01f30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a6377da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (5610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba5890eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ba588de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ba589162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a05249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a05249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a05231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba5826bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ba5826a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ba580b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ba54bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ba54bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a05232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba54baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-poly-add.c (5614 of 27910)
******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi    -target-feature +neon    -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   store <8 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <4 x i16>
# |   store <4 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <1 x i64>
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   store <16 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <16 x i8>, ptr %ref.tmp.i, align 8
# |   store <16 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <16 x i8>, ptr %__ret.i, align 8
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <8 x i16>
# |   store <8 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 8
# |   store <8 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i16>, ptr %__ret.i, align 8
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 8
# |   %__p1.addr.i = alloca <2 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = load <2 x i64>, ptr %b.addr, align 8
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   store <2 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i64>, ptr %ref.tmp.i, align 8
# |   store <2 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i64>, ptr %__ret.i, align 8
# |   ret <2 x i64> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560720b7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560720b77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560720b7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d5dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560720b10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560720b10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560720af58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607207a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607207a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607207a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (5615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583fe978eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583fe975e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583fe97962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6024733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f602478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6024733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f602471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583fe90ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583fe90ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583fe8f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583fe5a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583fe5a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f602471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f602471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f602471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583fe5a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (5616 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055654018aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556540187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055654018b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b3dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b3dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b3dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b3dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556540120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556540120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565401058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055653fdb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055653fdb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b3dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b3dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b3dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055653fdb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (5617 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562d8b39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562d8b36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562d8b3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3667333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f366738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3667333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f366731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d8acfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562d8acfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562d8ab48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562d8763e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562d8763b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f366731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f366731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f366731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562d8763a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (5618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, al
# | ...
# `---data was truncated (10240/92370) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648d6c5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648d6c59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648d6c5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f210af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f210af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f210af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f210af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648d6bf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648d6bf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648d6bd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648d6886e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648d6886b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f210af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f210af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f210af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648d6886a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (5621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055876be8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055876be8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055876be8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d3961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d396725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d3961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d39603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055876be23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055876be23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055876be088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055876bab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055876bab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d39604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d396050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d396050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055876bab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (5624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602108d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602108cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602108d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4ddb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560210868bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560210868a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056021084d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602104fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602104fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602104fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (5625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055952f3b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055952f3b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055952f3b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa366e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa366ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa366e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa366e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055952f34dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055952f34da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055952f3328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055952efe1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055952efe1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa366e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa366e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa366e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055952efe1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (5628 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec3e6d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec3e6d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec3e6d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75bb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75bb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75bb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75bb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec3e669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec3e669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec3e64e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec3e2fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec3e2fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75bb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75bb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75bb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec3e2fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (5629 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/72135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b1af33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b1af30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b1af3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb089449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0894a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb089449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb089431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b1aec9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b1aec9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b1aeae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b1ab5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b1ab5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb089432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0894330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0894330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b1ab5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (5631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz
# | ...
# `---data was truncated (10240/58675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2f9fe3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2f9fe0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2f9fe462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5922933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f592298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5922933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f592291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f9f79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2f9f79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2f9f5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2f9c0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2f9c0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f592291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f592291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f592291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f9c0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (5632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613f8d1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613f8d18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613f8d1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10b2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10b2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10b2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10b2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f8cb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613f8cb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613f8c968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613f8945e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613f8945b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10b2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10b2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10b2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f8945a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (5633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560350ae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560350ae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560350ae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc89ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc89aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc89ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc89ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560350a79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560350a79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560350a5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056035070de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056035070db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc89ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc89ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc89ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056035070da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (5637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %v
# | ...
# `---data was truncated (10240/86747) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d28d297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d28d294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d28d29862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1580133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f158018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1580133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f158011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d28d22dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d28d22da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d28d2128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d28cec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d28cec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f158011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f158011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f158011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d28cec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (5638 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale
# | ...
# `---data was truncated (10240/70021) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7cbba1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7cbb9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7cbba262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe34dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe34dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe34dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe34dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7cbb37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7cbb37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7cbb1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7cb7cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7cb7cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe34dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe34dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe34dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7cb7cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (5639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055955308deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055955308ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055955308e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a4461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a446725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a4461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a44603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559553023bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559553023a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595530088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559552cb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559552cb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a44604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a446050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a446050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559552cb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (5640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/40883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babfe28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055babfe25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055babfe2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f226d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f226d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f226d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f226d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babfdbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055babfdbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055babfda38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055babfa52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055babfa52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f226d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f226d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f226d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babfa52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (5643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd6bb82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd6bb7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd6bb8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96f7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96f7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96f7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96f7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd6bb18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd6bb18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd6bafd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd6b7ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd6b7acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96f7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96f7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96f7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd6b7aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (5644 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 nou
# | ...
# `---data was truncated (10240/78890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607508a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607508a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607508a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc370649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc370649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc370631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560750839bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560750839a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056075081e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607504cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607504cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc370632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3706330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607504cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (5646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557779e78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557779e75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557779e7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc669533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc66958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc669533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc66951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557779e0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557779e0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557779df38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557779aa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557779aa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc66951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc66951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc66951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557779aa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (5651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsc
# | ...
# `---data was truncated (10240/65905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f86c5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f86c5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f86c5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f86bf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f86bf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f86bd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f86887e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f86887b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f86887a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (5652 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648ba395eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648ba392e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648ba39662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8baf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8baf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8baf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8baf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648ba32bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648ba32ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648ba3108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648b9fbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648b9fbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8baf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8baf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8baf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648b9fbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (5653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561102c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561102c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561102c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5643449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56434a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5643449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5643431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561102bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561102bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561102bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056110285de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056110285db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5643432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56434330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56434330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056110285da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (5654 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x h
# | ...
# `---data was truncated (10240/69487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619adc7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619adc7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619adc7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa679d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa679d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa679d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa679d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619adc13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619adc13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619adbf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619ad8a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619ad8a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa679d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa679d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa679d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619ad8a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (5657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5e805deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5e805ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5e805e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5398f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5398f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5398f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5398f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5e7ff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5e7ff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5e7fd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5e7c87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5e7c87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5398f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5398f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5398f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5e7c87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (5659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb54478eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb54475e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb5447962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ce6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ce6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ce6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ce6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb5440ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb5440ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb543f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb540a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb540a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ce6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ce6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ce6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb540a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (5662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b849d3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b849d37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b849d3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0033049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00330a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0033049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0033031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b849cd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b849cd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b849cb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b849964e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b849964b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0033032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00330330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00330330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b849964a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (5667 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d97b4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d97b49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d97b4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe64f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe64f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe64f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe64f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d97ae2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d97ae2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d97ac78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d97776e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d97776b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe64f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe64f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe64f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d97776a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (5668 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2
# | ...
# `---data was truncated (10240/94673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba05e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba05e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba05e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0755e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0755ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0755e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0755e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba05df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba05df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba05ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba05a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba05a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0755e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0755e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0755e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba05a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (5670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c459c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c459c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c459c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f215bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f215bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f215bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f215bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c45959bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c45959a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c4593e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c455ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c455edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f215bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f215bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f215bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c455eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (5676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4c8562eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4c855fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4c856362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea73a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4c84f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4c84f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4c84dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4c818ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4c818cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea73a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4c818ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (5679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   
# | ...
# `---data was truncated (10240/23061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c85162eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c8515fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c8516362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f38f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c850f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c850f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c850dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c84d8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c84d8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c84d8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (5680 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = loa
# | ...
# `---data was truncated (10240/23447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560097e6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560097e67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560097e6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f300bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f300bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f300bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f300bced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560097e00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560097e00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560097de58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560097a94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560097a94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f300bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f300bcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f300bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560097a94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (5685 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llv
# | ...
# `---data was truncated (10240/59779) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f50500eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f504fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f5050162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6898f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6898f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6898f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6898f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f50496bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f50496a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f5047b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f5012ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f5012ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6898f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6898f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6898f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f5012aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (5686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstrid
# | ...
# `---data was truncated (10240/17118) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c05711eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c0570ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c0571262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7356b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7356b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7356b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7356b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c056a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c056a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c0568c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c0533be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c0533bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7356b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7356b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7356b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c0533ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (5687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589755e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589755e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589755e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbdc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbdc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbdc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbdc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055897557ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055897557ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589755638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558975212e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558975212b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbdc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbdc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbdc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558975212a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (5692 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055def7e5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055def7e5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055def7e6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7cd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7cd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7cd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7cd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055def7df5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055def7df5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055def7dda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055def7a89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055def7a89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7cd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7cd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7cd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055def7a89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (5695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4b5ea7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4b5ea4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4b5ea862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1932a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1932a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1932a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1932a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4b5e3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4b5e3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4b5e228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4b5ad1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4b5ad1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1932a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1932a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1932a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4b5ad1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (5697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557972b00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557972afde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557972b0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01f6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01f68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01f6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01f6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557972a96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557972a96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557972a7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055797272ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055797272ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01f6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01f68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01f68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055797272aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (5700 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563840861eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056384085ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056384086262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c2cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c2cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c2cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c2cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638407f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638407f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638407dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056384048be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056384048bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c2cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c2cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c2cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056384048ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (5704 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f13fc9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f13fc99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f13fc9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f654ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f654ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f654ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f654ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f13fc32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f13fc32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f13fc178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f13f8c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f13f8c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f654ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f654ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f654ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f13f8c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (5707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d26e512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d26e50fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d26e51362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f003d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f003d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f003d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f003d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d26e4a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d26e4a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d26e48d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d26e13ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d26e13cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f003d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f003d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f003d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d26e13ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (5709 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c535cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c535cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c535ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4130649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4130649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4130631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c53563bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c53563a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c535488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c531f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c531f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4130632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41306330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c531f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (5710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b13466beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b134668e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b13466c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dad01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dad0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dad01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dad003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b134601bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b134601a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1345e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b134295e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b134295b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dad004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dad0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dad0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b134295a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (5711 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be5dc70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be5dc6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be5dc7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb214933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb21498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb214933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb21491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be5dc06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be5dc06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be5dbeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be5d89ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be5d89ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb21491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb21491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb21491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be5d89aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (5712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/48385) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdcc5efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdcc5ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdcc5f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec87733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec8778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec87733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec8771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdcc585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdcc585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdcc56a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdcc219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdcc219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec8771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec8771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec8771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdcc219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (5715 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff2021eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ff201ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ff202262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33be849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33be8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33be849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33be831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff1fb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ff1fb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ff1f9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ff1c4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ff1c4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33be832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33be8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33be8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff1c4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (5719 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cf06c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cf06c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cf06c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b78133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b7818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b78133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b7811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cf065bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cf065ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cf06408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cf02efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cf02efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b7811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b7811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b7811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cf02efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (5720 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9e629aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9e6297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9e629b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3a8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3a898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3a8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3a891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9e6230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9e6230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9e62158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9e5ec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9e5ec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3a891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3a891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3a891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9e5ec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (5722 of 27910)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.srshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nos
# | ...
# `---data was truncated (10240/11578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa15fc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa15fc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa15fc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c4e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c4e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c4e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c4e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa15f5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa15f5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa15f408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa15befe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa15befb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c4e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c4e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c4e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa15befa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (5723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vsc
# | ...
# `---data was truncated (10240/41579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adb2c94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adb2c91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adb2c9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79c3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79c395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79c3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79c38ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adb2c2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adb2c2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adb2c0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adb28bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adb28beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79c38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79c38ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79c38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adb28bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (5724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b4b480eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b4b47de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b4b48162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb797d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb797d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb797d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb797d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b4b416bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b4b416a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b4b3fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b4b0aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b4b0aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb797d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb797d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb797d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b4b0aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (5725 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560550414eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560550411e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056055041562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c5f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c5f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c5f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c5f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605503aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605503aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056055038f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056055003ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056055003eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c5f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c5f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c5f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056055003ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (5727 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/121927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c53b154eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c53b151e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c53b15562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ebde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ebdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ebde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ebde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c53b0eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c53b0eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c53b0cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c53ad7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c53ad7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ebde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ebde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ebde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c53ad7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (5728 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @l
# | ...
# `---data was truncated (10240/62760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e295edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e295eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e295ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a29d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a29d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a29d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a29d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e29583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e29583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e295688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e29217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e29217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a29d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a29d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a29d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e29217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (5729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b05243deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b05243ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b05243e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2096049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20960a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2096049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2096031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0523d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0523d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0523b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b052067e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b052067b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2096032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20960330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20960330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b052067a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (5731 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559620a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559620a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559620a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5442a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5442aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5442a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5442a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055962099ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055962099ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596209838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559620632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559620632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5442a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5442a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5442a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559620632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (5732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd15a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfd159de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfd15a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a29b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a29b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a29b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a29b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd1536bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfd1536a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfd151b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfd11cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfd11cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a29b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a29b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a29b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd11caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (5733 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9f97f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9f97ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9f97f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5bd61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5bd6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5bd61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5bd603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f9786bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9f9786a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9f976b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9f941ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9f941ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5bd604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5bd6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5bd6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f941aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (5735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/112825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055905dd3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055905dd3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055905dd3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4b1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055905dcd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055905dcd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055905dcb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055905d967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055905d967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055905d967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (5737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba60bd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba60bd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba60bd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba60b6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba60b6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba60b538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba60802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba60802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56f2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba60802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (5738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587cb4daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587cb4d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587cb4db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a89b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a89b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a89b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a89b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587cb470bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587cb470a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587cb4558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587cb104e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587cb104b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a89b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a89b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a89b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587cb104a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (5739 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b912779eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b912776e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b91277a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf56733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf5678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf56733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf5671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b91270fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b91270fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9126f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9123a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9123a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf5671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf5671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf5671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9123a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (5740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv
# | ...
# `---data was truncated (10240/53548) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baaaaaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baaaaabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baaaaaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e00f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e00f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e00f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e00f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baaaa44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baaaa44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baaaa298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baaa6d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baaa6d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e00f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e00f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e00f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baaa6d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (5743 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f19c8bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f19c8bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f19c8c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f62449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f62449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f62431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f19c855bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f19c855a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f19c83a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f19c4e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f19c4e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f62432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f624330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f19c4e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (5744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cba80a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cba80a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cba80a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bea431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cba803bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cba803ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cba80208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cba7ccfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cba7ccfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bea4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cba7ccfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (5747 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b937297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b937294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b93729862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb93a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb93a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb93a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb93a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b93722dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b93722da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9372128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b936ec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b936ec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb93a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb93a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb93a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b936ec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (5750 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1b4782eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1b477fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1b478362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce5c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce5c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce5c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce5c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1b4718bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1b4718a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1b46fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1b43ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1b43acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce5c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce5c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce5c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1b43aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (5755 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570798dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570798d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570798dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2af6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2af6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2af6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2af6c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557079871bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557079871a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570798568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557079505e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557079505b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2af6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2af6c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2af6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557079505a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (5757 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8928bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8928b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8928bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f22e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f22e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f22e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f22e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c892852bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c892852a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8928378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8924e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8924e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f22e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f22e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f22e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8924e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (5760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638d30cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638d30cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638d30ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed7f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed7f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed7f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed7f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638d3063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638d3063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638d30488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638d2cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638d2cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed7f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed7f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed7f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638d2cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (5763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/67006) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8941ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8941fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d89420062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f740d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f740d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f740d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f740d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d894195bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d894195a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d89417a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d893e29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d893e29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f740d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f740d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f740d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d893e29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (5765 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c12c0abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c12c0a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c12c0ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84ce61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84ce6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84ce61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84ce603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c12c041bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c12c041a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c12c0268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c12bcd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c12bcd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84ce604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84ce6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84ce6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c12bcd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (5768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555618117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555618114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055561811862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fc4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fc498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fc4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fc491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556180adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556180ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556180928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555617d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555617d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fc491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fc491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fc491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555617d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (5770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store
# | ...
# `---data was truncated (10240/79497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564376dbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564376db7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564376dbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b04333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b0438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b04333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b0431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564376d50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564376d50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564376d358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643769e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643769e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b0431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b0431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b0431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643769e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (5771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055695e27feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055695e27ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055695e28062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbec4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbec40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbec4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbec4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055695e215bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055695e215a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055695e1fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055695dea9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055695dea9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbec4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbec40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbec40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055695dea9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (5772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e456021eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e45601ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e45602262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4b2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4b2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4b2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4b2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e455fb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e455fb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e455f9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e455c4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e455c4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4b2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4b2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4b2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e455c4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (5775 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055899bebeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055899bebbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055899bebf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f211e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f211e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f211e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f211e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055899be54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055899be54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055899be398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055899bae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055899bae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f211e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f211e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f211e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055899bae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (5776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bb4ab2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bb4aafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bb4ab362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aea91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bb4a48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bb4a48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bb4a2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bb46dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bb46dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5aea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aea91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bb46dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (5777 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/72493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622085deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622085dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622085df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67ea705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67ea75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67ea705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67ea6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562208574bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562208574a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622085598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562208208e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562208208b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67ea6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67ea6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67ea6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562208208a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (5779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c03ec28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c03ec25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c03ec2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc285f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc285f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc285f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc285f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c03ebbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c03ebbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c03eba38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c03e852e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c03e852b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc285f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc285f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc285f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c03e852a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (5788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbabb41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbabb3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbabb4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32b0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbabad7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbabad7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbababc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbab76be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbab76bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbab76ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (5789 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/58334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b2f7d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b2f7cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b2f7d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b0aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b0aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b0aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b0aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b2f767bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b2f767a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b2f74c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b2f3fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b2f3fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b0aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b0aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b0aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b2f3fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (5790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056011a6adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056011a6aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056011a6ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83cad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056011a643bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056011a643a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056011a6288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056011a2d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056011a2d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056011a2d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (5792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582279eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582279ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582279ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1333933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f133398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1333933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f133391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558227984bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558227984a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582279698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558227618e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558227618b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f133391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f133391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f133391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558227618a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (5794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/63169) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f235a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f235a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f235a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f8fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f8fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f8fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f8fc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f235a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f235a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f235a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2356b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2356b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f8fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f8fc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f8fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2356b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (5800 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4ad4e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4ad4e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4ad4e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cc0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cc038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cc0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cc031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4ad47ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4ad47ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4ad4638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4ad112e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4ad112b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cc031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cc031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cc031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ad112a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (5801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0502eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da0502be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0502f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ea3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ea3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ea3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ea3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da04fc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da04fc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da04fa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da04c58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da04c58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ea3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ea3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ea3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da04c58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (5806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642ab490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642ab48de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642ab49162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5a4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5a44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5a4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5a4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642ab426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642ab426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642ab40b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642ab0bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642ab0bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5a4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5a44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5a44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642ab0baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (5807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe4de8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe4de88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe4de8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc356d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc356d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc356d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc356d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe4de21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe4de21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe4de068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe4dab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe4dab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc356d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc356d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc356d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe4dab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (5809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6855bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6855bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6855be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfdaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfdaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfdaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfdaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a685553bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a685553a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6855388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6851e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6851e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfdaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfdaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfdaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6851e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (5810 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c7ea0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c7ea08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c7ea0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02ec431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c7e9a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c7e9a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c7e9868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c7e635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c7e635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02ec4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c7e635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (5818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8002a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a80029fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8002a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc79c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc79c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc79c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc79c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a800238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a800238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a80021d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7ffecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7ffeccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc79c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc79c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc79c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7ffecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (5823 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2cae5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2cae58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2cae5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff65c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff65c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2cadf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2cadf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2cadd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2caa85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2caa85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff65c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2caa85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (5825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601420c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601420c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601420c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b0d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b0d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b0d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b0d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560142059bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560142059a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056014203e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560141cede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560141cedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b0d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b0d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b0d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560141ceda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (5827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056492ca69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056492ca66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056492ca6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff98249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff982a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff98249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff98231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056492c9ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056492c9ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056492c9e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056492c693e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056492c693b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff98232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff982330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff982330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056492c693a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (5828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e24680beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e246808e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e24680c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5942d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5942d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5942d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5942d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2467a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2467a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2467868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e246435e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e246435b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5942d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5942d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5942d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e246435a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (5829 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ab0f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ab0f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ab0f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf2f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf2f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf2f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf2f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ab0ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ab0ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ab0ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ab0b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ab0b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf2f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf2f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf2f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ab0b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (5830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e723fc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e723fc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e723fc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77fc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77fc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77fc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77fc4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e723f5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e723f5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e723f428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e723bf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e723bf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77fc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77fc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77fc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e723bf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (5835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5b8be9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5b8be6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5b8bea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0af449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0af4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0af449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0af431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5b8b7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5b8b7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5b8b648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5b8813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5b8813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0af432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0af4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0af4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5b8813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (5836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055956d6b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055956d6b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055956d6b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd74f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd74f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd74f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd74f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055956d64bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055956d64ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055956d6308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055956d2dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055956d2dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd74f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd74f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd74f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055956d2dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (5842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %
# | ...
# `---data was truncated (10240/47698) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e9417ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e94179e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e9417d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d70c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d70ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d70c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d70c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e94112bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e94112a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e940f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e93da6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e93da6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d70c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d70c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d70c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e93da6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (5843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056233046eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056233046be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056233046f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59df133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59df18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59df133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59df11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562330404bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562330404a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623303e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562330098e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562330098b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59df11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59df11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59df11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562330098a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (5844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056533cbd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056533cbd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056533cbd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbbbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbbbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbbbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbbbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056533cb69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056533cb69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056533cb4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056533c7fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056533c7fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbbbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbbbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbbbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056533c7fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (5845 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb523e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb523dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb523e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2cb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2cb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2cb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2cb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb52378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb52378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb5235d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb5200ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb5200cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2cb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2cb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2cb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb5200ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (5847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb48fa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb48f9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb48fa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbac533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbac58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbac533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbac51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb48f37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb48f37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb48f1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb48bcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb48bcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbac51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbac51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbac51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb48bcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (5848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056395e7e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056395e7e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056395e7e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e35f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e35f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e35f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e35f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056395e77bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056395e77ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056395e7608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056395e40fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056395e40fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e35f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e35f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e35f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056395e40fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (5850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3a740feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3a740ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3a741062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c5db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c5db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c5db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c5db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3a73a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3a73a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3a738a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3a7039e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3a7039b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c5db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c5db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c5db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3a7039a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (5854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccf657aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccf6577e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccf657b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f949f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f949f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f949f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f949f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccf6510bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccf6510a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccf64f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccf61a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccf61a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f949f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f949f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f949f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccf61a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (5855 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f6051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590f604ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590f605262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f5fe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590f5fe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590f5fcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590f5c7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590f5c7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5de231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f5c7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (5857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqr
# | ...
# `---data was truncated (10240/28170) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e00bb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e00bade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e00bb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7a0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7a018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7a0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7a011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e00b46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e00b46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e00b2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e007dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e007dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7a011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7a011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7a011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e007daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (5858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae963e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae963dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae963e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f270ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f270aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f270ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f270ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae96378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae96378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae9635d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae9600ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae9600cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f270ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f270ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f270ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae9600ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (5859 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635418c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635418c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635418c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f801c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f801c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056354185cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056354185ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635418418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635414f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635414f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635414f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (5861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd7b168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd7b165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd7b16962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbe7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbe738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbe7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbe731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd7b0febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd7b0fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd7b0e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd7ad92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd7ad92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbe731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbe731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbe731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd7ad92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (5862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055790b966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055790b963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055790b96762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7689a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7689aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7689a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7689a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055790b8fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055790b8fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055790b8e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055790b590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055790b590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7689a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7689a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7689a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055790b590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (5863 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cddb1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cddb19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cddb1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0357933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f035798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0357933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f035791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cddab2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cddab2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cdda978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cdd746e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cdd746b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f035791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f035791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f035791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cdd746a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (5866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x
# | ...
# `---data was truncated (10240/58661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd14030eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd1402de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd1403162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd874b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd874b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd874b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd874b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd13fc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd13fc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd13fab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd13c5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd13c5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd874b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd874b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd874b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd13c5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (5867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/53678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055845f776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055845f773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055845f77762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb92ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb92baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb92ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb92ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055845f70cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055845f70ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055845f6f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055845f3a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055845f3a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb92ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb92ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb92ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055845f3a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (5869 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e1dfe8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e1dfe5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e1dfe962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0d331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e1df7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e1df7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e1df638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e1dc12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e1dc12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0d331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e1dc12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (5871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bc8781eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bc877ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bc878262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b70e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b70ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b70e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b70e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bc8717bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bc8717a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bc86fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bc83abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bc83abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b70e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b70e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b70e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bc83aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (5874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d070b72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d070b6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d070b7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faac4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faac415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faac4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faac40ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d070b08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d070b08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d070aed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d07079ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d07079cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faac40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faac40ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faac40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d07079ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (5875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f6807eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f6807be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f6807f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb55d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb55d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb55d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb55d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f68014bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f68014a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f67ff98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f67ca8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f67ca8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb55d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb55d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb55d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f67ca8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (5876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5d4751eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5d474ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5d475262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6251933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f625198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6251933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f625191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5d46e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5d46e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5d46cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5d437be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5d437bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f625191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f625191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f625191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5d437ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (5878 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562627bbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562627bbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562627bbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8da8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8da898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8da8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8da891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562627b53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562627b53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562627b388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626277e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626277e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8da891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8da891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8da891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626277e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (5883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4294e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4294e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4294e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5599249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5599249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5599231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e42947bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e42947ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4294608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e42910fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e42910fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5599232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55992330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e42910fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (5885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb703d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb703d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb703d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1316049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1316049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1316031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb70369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb70369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb7034e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb6fffde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb6fffdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1316032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb6fffda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (5891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dabbbe1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dabbbdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dabbbe262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1775c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1775ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1775c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1775c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dabbb77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dabbb77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dabbb5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dabb80be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dabb80bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1775c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1775c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1775c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dabb80ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (5898 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <v
# | ...
# `---data was truncated (10240/22290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fec660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fec65de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fec66162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4866333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4866333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fec5f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fec5f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fec5db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fec28ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fec28ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f486631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fec28aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (5899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055603a097eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055603a094e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055603a09862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b69449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b694a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b69449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b69431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603a02dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603a02da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055603a0128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556039cc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556039cc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b69432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b694330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b694330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556039cc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (5904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b84dc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b84dbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b84dc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9da7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9da76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9da7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9da7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b84d58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b84d58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b84d3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b849ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b849ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9da7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9da76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9da76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b849eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (5905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8f7f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8f7f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8f7f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2072d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2072d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2072d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2072d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8f7f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8f7f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8f7f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8f7bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8f7bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2072d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2072d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2072d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8f7bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (5907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055681d2d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055681d2cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055681d2d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb92f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb92f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb92f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb92f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055681d266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055681d266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055681d24b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055681cefae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055681cefab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb92f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb92f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb92f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055681cefaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (5908 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c8f262eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c8f25fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c8f26362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1567133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f156718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1567133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f156711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c8f1f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c8f1f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c8f1dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c8ee8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c8ee8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f156711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f156711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f156711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c8ee8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (5909 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 
# | ...
# `---data was truncated (10240/47772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560270627eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560270624e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056027062862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c9da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c9daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c9da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c9da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602705bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602705bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602705a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560270251e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560270251b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c9da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c9da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c9da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560270251a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (5911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634f2d1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634f2d1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634f2d2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb119f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb119f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb119f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb119eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634f2cb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634f2cb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634f2c9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634f2949e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634f2949b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb119eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb119eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb119eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634f2949a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (5913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e34b7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e34b77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e34b7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f759b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f759b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f759b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f759b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e34b10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e34b10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e34af58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e347a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e347a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f759b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f759b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f759b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e347a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (5914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x
# | ...
# `---data was truncated (10240/93466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8e2910eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8e290de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8e291162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eff049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eff0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eff049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eff031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8e28a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8e28a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8e288b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8e253ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8e253ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3eff032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eff0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eff0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8e253aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (5915 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfaa12beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfaa128e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfaa12c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc21d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc21d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc21d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc21d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfaa0c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfaa0c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfaa0a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfa9d55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfa9d55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc21d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc21d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc21d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa9d55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (5918 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636a37d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636a37d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636a37d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f528dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f528dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f528dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f528dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636a376abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636a376aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636a374f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636a33fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636a33feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f528dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f528dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f528dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636a33fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (5919 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aaf604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aaf601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aaf60562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e32849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e32849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e32831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aaf59abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aaf59aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aaf57f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aaf22ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aaf22eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e32832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e328330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aaf22ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (5920 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/71955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c45e058eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c45e055e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c45e05962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c1661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c166725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c1661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c16603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c45dfeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c45dfeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c45dfd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c45dc82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c45dc82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c16604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c166050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c166050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c45dc82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (5921 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b4034eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b4034be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b4034f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77bdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b402e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b402e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b402c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b3ff78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b3ff78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b3ff78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (5923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0b5238eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0b5235e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0b523962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc531733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc53178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc531733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc53171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0b51cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0b51cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0b51b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0b4e62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0b4e62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc53171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc53171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc53171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0b4e62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (5927 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a59362eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a5935fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a5936362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cd1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cd118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cd1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cd111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a592f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a592f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a592dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a58f8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a58f8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cd111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cd111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cd111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a58f8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (5930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4cfae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4cfae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4cfaea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff28b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff28b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff28b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff28b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4cfa7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4cfa7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4cfa648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4cf713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4cf713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff28b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff28b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff28b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4cf713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (5934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056094ff1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056094ff19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056094ff1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb200305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb20035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb200305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2002ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056094feb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056094feb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056094fe978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056094fb46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056094fb46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2002eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2002ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2002ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056094fb46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (5935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562616c11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562616c0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562616c1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc758f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc758f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc758f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc758f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562616ba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562616ba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562616b8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056261683be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056261683bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc758f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc758f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc758f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056261683ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (5937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055667400beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556674008e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055667400c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ff4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ff418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ff4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ff411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556673fa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556673fa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556673f868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556673c35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556673c35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ff411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ff411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ff411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556673c35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (5938 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x ha
# | ...
# `---data was truncated (10240/58653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cc5400eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cc53fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cc540162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4665649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46656a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4665649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4665631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cc5396bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cc5396a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cc537b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cc502ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cc502ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4665632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46656330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46656330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cc502aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (5942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b4b217eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b4b214e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b4b21862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafd1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafd198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafd1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafd191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b4b1adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b4b1ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b4b1928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b4ae41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b4ae41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafd191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafd191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafd191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b4ae41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (5943 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620659eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620659e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620659ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f541a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f541a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f541a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f541a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562065982bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562065982a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620659678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562065616e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562065616b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f541a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f541a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f541a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562065616a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (5946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d093e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d093e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d093e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f37f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f37f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f37f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f37f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d0937ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d0937ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d093638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d09012e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d09012b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f37f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f37f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f37f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d09012a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (5947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0b6643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0b6640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0b664462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6521449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6521449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6521431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0b65d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0b65d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0b65be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0b626de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0b626db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6521432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65214330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0b626da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (5948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556af5a42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556af5a3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556af5a4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ba0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ba015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ba0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ba00ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556af59d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556af59d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556af59bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556af566ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556af566cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ba00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ba00ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ba00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556af566ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (5950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055613cbe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055613cbe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055613cbe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70ae533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70ae58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70ae533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70ae51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055613cb7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055613cb7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055613cb618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055613c810e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055613c810b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70ae51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70ae51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70ae51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055613c810a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (5951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdb46f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdb46f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdb46f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8700249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87002a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8700249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8700231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdb468abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdb468aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdb466f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdb431ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdb431eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8700232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87002330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87002330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdb431ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (5953 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc5155aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc51557e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc5155b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feac1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feac18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feac1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feac1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc514f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc514f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc514d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc51184e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc51184b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feac1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feac18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feac18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc51184a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (5954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b44bd0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b44bd0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b44bd1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe27601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2760725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe27601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe276003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b44bca5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b44bca5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b44bc8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b44b939e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b44b939b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe276004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2760050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2760050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b44b939a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (5955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/80648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a03a5eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a03a5ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a03a5ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5cb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5cb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5cb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5cb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a03a584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a03a584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a03a5698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a03a218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a03a218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5cb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5cb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5cb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a03a218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (5956 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1758cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1758c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1758cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f175861bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f175861a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1758468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1754f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1754f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1754f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (5958 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555eec31feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555eec31ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555eec32062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2431c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2431ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2431c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2431c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555eec2b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555eec2b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555eec29a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555eebf49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555eebf49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2431c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2431c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2431c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555eebf49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (5965 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8ce7bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8ce7bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8ce7be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5e2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5e2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5e2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5e2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8ce753bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8ce753a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8ce7388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8ce3e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8ce3e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5e2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5e2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5e2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8ce3e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (5966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea5935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea5932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea593662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d78133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d7818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d78133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d7811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea58cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea58cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea58b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea555fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea555fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d7811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d7811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d7811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea555fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (5967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563339b00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563339afde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563339b0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc649105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc64915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc649105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6490ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563339a96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563339a96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563339a7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056333972ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056333972ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6490eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6490ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6490ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056333972aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (5968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562318558eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562318555e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056231855962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd68f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd68f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd68f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd68f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623184eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623184eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623184d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562318182e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562318182b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd68f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd68f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd68f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562318182a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (5969 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558885bfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558885bf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558885bfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2297d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2297d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2297d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2297d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558885b90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558885b90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558885b758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558885824e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558885824b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2297d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2297d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2297d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558885824a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (5971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vs
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055760d8f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055760d8efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055760d8f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02b8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02b8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02b8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02b8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055760d888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055760d888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055760d86d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055760d51ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055760d51cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02b8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02b8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02b8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055760d51ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (5973 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579e88e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579e88dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579e88e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0673649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0673649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0673631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e8876bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579e8876a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579e885b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579e850ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579e850ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0673632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e850aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (5975 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056083d208eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056083d205e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056083d20962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56bb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56bb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56bb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56bb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056083d19ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056083d19ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056083d1838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056083ce32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056083ce32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56bb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56bb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56bb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056083ce32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (5976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota
# | ...
# `---data was truncated (10240/94681) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f11b912eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f11b90fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f11b91362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff58dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff58dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff58dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff58dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f11b8a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f11b8a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f11b88d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f11b53ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f11b53cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff58dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff58dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff58dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f11b53ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (5977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630047b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630047b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630047b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77b0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77b08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77b0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77b0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056300474bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056300474ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630047308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630043dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630043dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77b0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77b08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77b08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630043dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (5979 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608ce67deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608ce67ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608ce67e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ff6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ff66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ff6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ff6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608ce613bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608ce613a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608ce5f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608ce2a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608ce2a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ff6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ff66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ff66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608ce2a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (5981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.v
# | ...
# `---data was truncated (10240/53192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056119a081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056119a07ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056119a08262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef28305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef2835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef28305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef282ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056119a017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056119a017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561199ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561199cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561199cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef282eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef282ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef282ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561199caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (5982 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056461c92aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056461c927e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056461c92b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f906cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f906cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f906cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f906caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056461c8c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056461c8c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056461c8a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056461c554e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056461c554b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f906caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f906caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f906caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056461c554a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (5984 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d59d93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d59d90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d59d9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7dcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7dcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7dcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7dcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d59d29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d59d29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d59d0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d599bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d599bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7dcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7dcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7dcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d599bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (5985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639b9865eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639b9862e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639b986662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c4d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c4d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c4d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c4d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639b97fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639b97fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639b97e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639b948fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639b948fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c4d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c4d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c4d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639b948fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (5988 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f0c491eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f0c48ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f0c49262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb342649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb342649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb342631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f0c427bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f0c427a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f0c40c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f0c0bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f0c0bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb342632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3426330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f0c0bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (5990 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/65072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b15d29deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b15d29ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b15d29e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d2b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d2b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d2b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d2b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b15d233bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b15d233a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b15d2188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b15cec7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b15cec7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d2b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d2b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d2b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b15cec7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (5991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557970f51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557970f4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557970f5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe87c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe87c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe87c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe87c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557970ee7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557970ee7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557970ecc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557970b7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557970b7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe87c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe87c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe87c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557970b7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (5992 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cc6671eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cc666ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cc667262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe38f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe38f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe38f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe38f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cc6607bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cc6607a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cc65ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cc629be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cc629bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe38f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe38f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe38f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cc629ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (5993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) 
# | ...
# `---data was truncated (10240/68437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055834ac50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055834ac4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055834ac5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f549b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f549b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f549b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f549b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055834abe6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055834abe6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055834abcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055834a87ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055834a87ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f549b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f549b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f549b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055834a87aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (5996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056374ca36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056374ca33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056374ca3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cc3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cc3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cc3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cc3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056374c9ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056374c9cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056374c9b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056374c660e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056374c660b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cc3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cc3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cc3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056374c660a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (5997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a92d0c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a92d0c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a92d0c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef57f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef57f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef57f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef57f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a92d05ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a92d05ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a92d0438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a92ccf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a92ccf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef57f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef57f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef57f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a92ccf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (5999 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddb91cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddb91c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddb91cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f859f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f859f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f859f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f859f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddb9161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddb9161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddb91468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddb8df5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddb8df5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f859f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f859f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f859f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddb8df5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (6006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056098da66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056098da63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056098da6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feacdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feacdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feacdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feacdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056098d9fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056098d9fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056098d9e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056098d690e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056098d690b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feacdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feacdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feacdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056098d690a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (6009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642f834eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f834be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f834f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f563b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f563b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f563b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f563b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f82e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f82e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f82c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f7f78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f7f78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f563b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f563b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f563b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f7f78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (6010 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv
# | ...
# `---data was truncated (10240/75133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ecaca3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ecaca0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ecaca462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d93333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d9338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d93333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d9331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ecac39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ecac39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ecac1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eca8cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eca8cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d9331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d9331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d9331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eca8cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (6014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/33198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4bf3b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4bf3afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4bf3b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a86333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a8638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a86333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a8631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4bf348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4bf348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4bf32d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4befdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4befdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a8631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a8631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a8631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4befdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (6015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568ad01eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568ad01be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568ad01f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f903fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f903fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f903fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f903fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568acfb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568acfb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568acf998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568acc48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568acc48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f903fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f903fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f903fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568acc48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (6017 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, pt
# | ...
# `---data was truncated (10240/73955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abdd987eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abdd984e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abdd98862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdf1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdf1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdf1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdf1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abdd91dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abdd91da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abdd9028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abdd5b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abdd5b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdf1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdf1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdf1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abdd5b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (6018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643f4ceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643f4cebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643f4cef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d46249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d462a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d46249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d46231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643f4c84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643f4c84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643f4c698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643f4918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643f4918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d46232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d462330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d462330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643f4918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (6020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562eb3406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562eb3403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562eb340762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1090133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f109018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1090133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f109011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562eb339cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562eb339ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562eb33818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562eb3030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562eb3030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f109011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f109011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f109011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562eb3030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (6021 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e839aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e839a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e839ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bbbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bbbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bbbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bbbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e83940bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e83940a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e839258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e835d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e835d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bbbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bbbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bbbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e835d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (6023 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559702c50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559702c4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559702c5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05db21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05db2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05db21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05db203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559702be6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559702be6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559702bcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055970287ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055970287ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05db204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05db2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05db2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055970287aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (6025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/62752) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056536b874eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056536b871e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056536b87562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5636a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5636aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5636a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5636a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056536b80abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056536b80aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056536b7ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056536b49ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056536b49eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5636a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5636a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5636a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056536b49ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (6026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055690a736eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055690a733e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055690a73762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76a0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76a0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76a0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76a0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055690a6ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055690a6cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055690a6b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055690a360e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055690a360b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76a0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76a0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76a0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055690a360a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (6028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bf26abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bf26a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bf26ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb278133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb27818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb278133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb27811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bf2641bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bf2641a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bf26268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bf22d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bf22d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb27811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb27811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb27811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bf22d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (6030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv
# | ...
# `---data was truncated (10240/83637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055690087ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556900879e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055690087d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0ade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0adea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0ade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0ade31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556900812bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556900812a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569007f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569004a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569004a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0ade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0ade330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0ade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569004a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (6031 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree n
# | ...
# `---data was truncated (10240/15237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d55d95beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d55d958e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d55d95c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bdcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bdcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bdcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bdcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d55d8f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d55d8f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d55d8d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d55d585e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d55d585b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bdcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bdcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bdcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d55d585a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (6032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca7cc6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca7cc6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca7cc6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb160705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb16075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb160705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1606ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca7cc04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca7cc04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca7cbe98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca7c898e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca7c898b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1606eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1606ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1606ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca7c898a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (6033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/68247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648f4be4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648f4be1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648f4be562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c6921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c692725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c6921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c69203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648f4b7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648f4b7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648f4b5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648f480ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648f480eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c69204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c692050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c692050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648f480ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (6034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624659ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624659fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562465a0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ca9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ca9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ca9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ca9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562465995bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562465995a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056246597a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562465629e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562465629b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ca9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ca9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ca9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562465629a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (6035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a7b5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589a7b59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589a7b5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f138a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f138a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f138a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f138a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a7af2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589a7af2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589a7ad78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589a7786e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589a7786b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f138a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f138a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f138a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a7786a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (6037 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg)
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d239f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d239f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d239f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedcaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedcaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedcaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedcaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d23989bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d23989a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d2396e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d2361de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d2361db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedcaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedcaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedcaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d2361da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (6039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056174ab0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056174ab09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056174ab0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e05e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e05ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e05e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e05e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056174aaa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056174aaa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056174aa878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056174a736e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056174a736b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e05e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e05e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e05e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056174a736a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (6040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055892f7e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055892f7e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055892f7e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62fd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62fd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62fd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62fd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055892f779bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055892f779a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055892f75e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055892f40de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055892f40db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62fd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62fd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62fd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055892f40da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (6041 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3b5bd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3b5bcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3b5bd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33c4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3b5b67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3b5b67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3b5b4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3b57fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3b57fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33c4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3b57fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (6043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adad0c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adad0c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adad0c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4888b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4888b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4888b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4888b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adad05abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adad05aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adad03f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adacceee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adacceeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4888b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4888b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4888b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adacceea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (6044 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564d0c1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564d0c1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564d0c2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef4f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef4f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef4f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef4f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564d0bb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564d0bb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564d0b9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564d0849e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564d0849b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef4f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef4f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef4f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564d0849a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (6045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e14795ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e147959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e14795d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b24f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b24f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b24f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b24f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1478f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1478f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1478d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e147586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e147586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b24f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b24f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b24f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e147586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (6046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc40cfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc40cf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc40cfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9367649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9367649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9367631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc40c90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc40c90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc40c758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc40924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc40924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9367632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc40924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (6047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/77054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056477d149eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056477d146e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056477d14a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07cdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07cdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07cdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07cdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056477d0dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056477d0dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056477d0c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056477cd73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056477cd73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07cdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07cdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07cdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056477cd73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (6049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c926329eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c926326e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c92632a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe979449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9794a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe979449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe979431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9262bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9262bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9262a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c925f53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c925f53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe979432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9794330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9794330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c925f53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (6050 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/87191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4689adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4689aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4689ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc003533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc00358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc003533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc00351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c468943bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c468943a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4689288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4685d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4685d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc00351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc00351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc00351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4685d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (6051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597e2107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597e2104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597e210862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa63f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa63f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa63f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa63f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597e209dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597e209da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597e20828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597e1d31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597e1d31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa63f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa63f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa63f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597e1d31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (6053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/58326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565e99c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565e99bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565e99c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd610b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd610b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd610b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd610aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565e9956bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565e9956a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565e993b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565e95eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565e95eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd610aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd610aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd610aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565e95eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (6056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055889e654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055889e651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055889e65562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ea2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ea2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ea2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ea2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055889e5eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055889e5eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055889e5cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055889e27ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055889e27eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ea2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ea2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ea2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889e27ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (6057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <v
# | ...
# `---data was truncated (10240/50890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aff908eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557aff905e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557aff90962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff3de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff3de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff3de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff3de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aff89ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557aff89ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557aff8838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557aff532e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557aff532b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff3de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff3de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff3de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aff532a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (6062 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7482e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7482e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7482e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5eb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5eb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5eb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5eb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e74827ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e74827ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7482638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e747f12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e747f12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5eb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5eb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5eb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e747f12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (6063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/62956) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d13a8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d13a8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d13a8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4e2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4e295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4e2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4e28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d13a23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d13a23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d13a088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d136b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d136b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4e28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4e28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4e28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d136b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (6064 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32> %maske
# | ...
# `---data was truncated (10240/75397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71eb50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a71eb4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a71eb5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71eae6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a71eae6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a71eacb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a71e77ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a71e77ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a71e77aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (6065 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0379e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0379e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0379e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0714f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0714f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0714f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0714f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e03797dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e03797da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0379628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e037611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e037611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0714f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0714f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0714f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e037611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (6068 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055593cbe3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055593cbe0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055593cbe462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa588449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5884a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa588449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa588431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055593cb79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055593cb79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055593cb5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055593c80de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055593c80db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa588432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5884330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5884330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055593c80da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (6069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567b4b8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567b4b8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567b4b9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03eda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03edaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03eda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03eda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567b4b25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567b4b25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567b4b0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567b47b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567b47b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03eda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03eda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03eda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567b47b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (6070 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c832f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c832f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c832f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3138c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3138c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3138c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3138c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c83289bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c83289a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c8326e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c82f1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c82f1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3138c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3138c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3138c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c82f1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (6071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4dcbd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4dcbcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4dcbd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24c2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24c2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24c2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24c2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4dcb67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4dcb67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4dcb4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4dc7fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4dc7fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24c2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24c2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24c2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4dc7fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (6072 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf3e173eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf3e170e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf3e17462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2007649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20076a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2007649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2007631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf3e109bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf3e109a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf3e0ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf3dd9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf3dd9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2007632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20076330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20076330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf3dd9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (6077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_viota_m_u16m4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_viota_m_u16m8(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/40411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623d436feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623d436ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623d437062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4fa105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4fa15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4fa105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4fa0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623d4305bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623d4305a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623d42ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623d3f99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623d3f99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4fa0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4fa0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4fa0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623d3f99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (6078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c7e993eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c7e990e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c7e99462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd127049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd127049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd127031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c7e929bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c7e929a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c7e90e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c7e5bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c7e5bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd127032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c7e5bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (6079 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i
# | ...
# `---data was truncated (10240/40929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2e8778eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2e8775e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2e877962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f610dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f610dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f610dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f610dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2e870ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2e870ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2e86f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2e83a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2e83a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f610dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f610dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f610dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2e83a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (6080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed55ddaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed55dd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed55ddb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa276249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa276249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa276231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed55d70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed55d70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed55d558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed55a04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed55a04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa276232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2762330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed55a04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (6081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, a
# | ...
# `---data was truncated (10240/71115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eeb842feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eeb842ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eeb843062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb48b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb48b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb48b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb48b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eeb83c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eeb83c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eeb83aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eeb8059e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eeb8059b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb48b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb48b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb48b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eeb8059a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (6083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da6f8caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da6f8c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da6f8cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6b6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6b6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6b6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6b6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da6f860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da6f860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da6f8458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da6f4f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da6f4f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6b6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6b6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6b6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da6f4f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (6084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %
# | ...
# `---data was truncated (10240/66087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3f34c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3f34c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3f34c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7773249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7773249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7773231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3f345abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3f345aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3f343f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3f30eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3f30eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7773232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3f30eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (6086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bfac8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bfac87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bfac8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9021c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9021c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9021c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9021c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bfac20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bfac20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bfac058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bfa8b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bfa8b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9021c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9021c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9021c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bfa8b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (6089 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbe4846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbe4843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbe484762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7d971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbe47dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbe47dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbe47c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbe4470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbe4470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7d971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbe4470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (6091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560681ab4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560681ab1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560681ab562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd411133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd41118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd411133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd41111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560681a4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560681a4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560681a2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606816dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606816deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd41111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd41111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd41111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606816dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (6093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2f413eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e2f410e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2f41462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9793933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f979398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9793933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f979391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2f3a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e2f3a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e2f38e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e2f03de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e2f03db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f979391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f979391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f979391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e2f03da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (6094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d484450eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d48444de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d48445162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f446e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f446e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f446e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f446e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4843e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4843e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4843cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d48407ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d48407ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f446e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f446e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f446e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d48407aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (6095 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564b37a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564b37a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564b37a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd98c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd98c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd98c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd98c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564b373abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564b373aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564b371f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564b33cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564b33ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd98c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd98c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd98c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564b33cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (6096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aaeb2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aaeb29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aaeb2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aaeac2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aaeac2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aaeaa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aae756e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aae756b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aae756a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (6097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e832637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e832634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e83263862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d55649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d55649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d55631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8325cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8325cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8325b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e832261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e832261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d55632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d556330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e832261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (6100 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637d22fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637d22f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637d22fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5fd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5fd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5fd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5fd2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637d2292bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637d2292a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637d22778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637d1f26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637d1f26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5fd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5fd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5fd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637d1f26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (6101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |  
# | ...
# `---data was truncated (10240/43478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b0193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615b0190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615b019462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d57831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b0129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615b0129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615b010e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615afdbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615afdbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615afdbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (6103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg
# | ...
# `---data was truncated (10240/20531) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055603dcadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055603dcaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055603dcae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9762a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9762aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9762a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9762a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603dc43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603dc43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055603dc288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055603d8d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055603d8d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9762a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9762a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9762a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055603d8d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (6104 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3a8f07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3a8f04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3a8f0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc632649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6326a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc632649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc632631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a8e9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3a8e9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3a8e828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3a8b31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3a8b31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc632632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6326330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6326330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a8b31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (6106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562d2397eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562d2394e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562d239862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2245b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2245b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2245b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2245aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d232dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562d232da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562d23128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562d1fc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562d1fc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2245aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2245aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2245aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562d1fc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (6108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/41659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558effe3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558effe3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558effe3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbea849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbea8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbea849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbea831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558effdd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558effdd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558effdb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558effa68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558effa68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbea832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbea8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbea8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558effa68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (6110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d25b63deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d25b63ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d25b63e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d25b5d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d25b5d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d25b5b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d25b267e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d25b267b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d25b267a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (6111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac86b1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac86b18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac86b1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac86ab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac86ab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac86a968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac86745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac86745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac86745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (6112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056307cf1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056307cf1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056307cf1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6687333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f668738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6687333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f668731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307ceb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056307ceb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056307ce998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056307cb48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056307cb48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f668731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f668731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f668731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056307cb48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (6114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055908dadceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055908dad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055908dadd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9d6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9d60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9d6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9d6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055908da72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055908da72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055908da578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055908d706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055908d706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9d6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9d60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9d60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055908d706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (6117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611d1cb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611d1cb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611d1cb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5524649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5524649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5524631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611d1c4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611d1c4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611d1c318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611d18e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611d18e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5524632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55246330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611d18e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (6118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ...
# `---data was truncated (10240/14904) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f297411eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f29740ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f29741262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96ead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2973a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2973a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f29738c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f29703be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f29703bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f29703ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (6121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613d93dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613d93d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613d93dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7f921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7f92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7f921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7f9203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613d9371bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613d9371a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613d93568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613d9005e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613d9005b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7f9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7f92050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7f92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613d9005a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (6123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055826934beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558269348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055826934c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd91fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd91fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd91fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd91fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582692e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582692e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582692c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558268f75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558268f75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd91fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd91fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd91fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558268f75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (6124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/68429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561997d5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561997d5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561997d5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d6a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d6a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d6a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d6a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561997cf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561997cf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561997cd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561997987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561997987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d6a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d6a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d6a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561997987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (6126 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aee7cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557aee7cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557aee7d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14ddf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14ddf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14ddf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14ddf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aee765bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557aee765a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557aee74a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557aee3f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557aee3f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14ddf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14ddf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14ddf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aee3f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (6127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600cdc19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600cdc16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600cdc1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb86bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb86bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb86bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb86bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600cdbafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600cdbafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600cdb948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600cd843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600cd843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb86bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb86bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb86bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600cd843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (6130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e88650eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e8864de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e8865162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1d7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e885e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e885e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e885cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e8827ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e8827ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1d78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e8827aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (6132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d4c260eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d4c25de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d4c26162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff538849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5388a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff538849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff538831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d4c1f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d4c1f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d4c1db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d4be8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d4be8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff538832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5388330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5388330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d4be8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (6133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/65723) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608cf2e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608cf2e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608cf2ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f280d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f280d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608cf27fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608cf27fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608cf2648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608cef13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608cef13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f280d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608cef13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (6134 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_
# | ...
# `---data was truncated (10240/10440) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbfdb4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbfdb4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbfdb4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd379849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3798a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd379849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd379831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbfdae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbfdae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbfdac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbfd778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbfd778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd379832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3798330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3798330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbfd778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (6135 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0,
# | ...
# `---data was truncated (10240/29451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604230eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604230e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604230eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efec6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efec68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efec6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efec6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560423080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560423080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604230658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560422d14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560422d14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efec6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efec68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efec68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560422d14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (6136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618fc2eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618fc2e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618fc2ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f186c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f186c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f186c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f186c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618fc282bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618fc282a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618fc2678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618fbf16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618fbf16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f186c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f186c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f186c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618fbf16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (6137 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056367f8efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056367f8ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056367f8f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4588733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4588733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056367f885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056367f885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056367f86a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056367f519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056367f519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f458871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056367f519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (6139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056496f9c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056496f9c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056496f9ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa83f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa83f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa83f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056496f95fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056496f95fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056496f9448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056496f5f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056496f5f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa83f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa83f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa83f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056496f5f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (6141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a1fd63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a1fd60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a1fd6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb81401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8140725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb81401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb814003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a1fcf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a1fcf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a1fcde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a1f98de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a1f98db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb814004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8140050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8140050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a1f98da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (6142 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x 
# | ...
# `---data was truncated (10240/59787) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cda048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cda045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cda04962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd949a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd949a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd949a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd949a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cd9fdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cd9fdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cd9fc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cd9c72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cd9c72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd949a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd949a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd949a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cd9c72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (6145 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0, i64 %2)
# | ...
# `---data was truncated (10240/69831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565105681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056510567ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056510568262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e22133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e2218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e22133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e2211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565105617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565105617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651055fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651052abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651052abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e2211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e2211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e2211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651052aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (6146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bb453eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bb453be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bb453f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5687533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f568758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5687533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f568751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bb44d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bb44d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bb44b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bb4168e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bb4168b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f568751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f568751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f568751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bb4168a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (6147 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/68255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558de78afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558de78ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558de78b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5da21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5da2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5da21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5da203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558de7845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558de7845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558de782a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558de74d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558de74d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5da204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5da2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5da2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558de74d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (6148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind 
# | ...
# `---data was truncated (10240/77062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b053debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b053de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b053dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee12e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee12e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee12e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee12e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b053d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b053d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b053d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b053a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b053a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee12e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee12e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee12e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b053a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (6149 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055604c4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055604c4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055604c4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eb8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eb898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eb8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eb891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055604c46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055604c46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055604c4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055604c102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055604c102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1eb891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eb891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eb891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055604c102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (6150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1b6521eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1b651ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1b652262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae0c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae0c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae0c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae0c6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1b64b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1b64b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1b649c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1b614be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1b614bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae0c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae0c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae0c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1b614ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (6151 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/60817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff650eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ff650be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ff650f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb74ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb74aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb74ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb74ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff64a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ff64a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ff64898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ff6138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ff6138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb74ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb74ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb74ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff6138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (6152 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vundefined_f16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vundefined_f16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vundefined_f16m1() #0 {
# | entry:
# |   ret <vscale x 4 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vundefined_f16m2() #0 {
# | entry:
# |   ret <vscale x 8 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vundefined_f16m4() #0 {
# | entry:
# |   ret <vscale x 16 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vundefined_f16m8() #0 {
# | entry:
# |   ret <vscale x 32 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vundefined_f32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vundefined_f32m1() #0 {
# | entry:
# |   ret <vscale x 2 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vundefined_f32m2() #0 {
# | entry:
# |   ret <vscale x 4 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vundefined_f32m4() #0 {
# | entry:
# |   ret <vscale x 8 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vundefined_f32m8() #0 {
# | entry:
# |   ret <vscale x 16 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vundefined_f64m1() #0 {
# | entry:
# |   ret <vscale x 1 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vundefined_f64m2() #0 {
# | entry:
# |   ret <vscale x 2 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vundefined_f64m4() #0 {
# | entry:
# |   ret <vscale x 4 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vundefined_f64m8() #0 {
# | entry:
# |   ret <vscale x 8 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_i8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_i8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_i8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_i8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_i8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_i8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_i8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_i16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_i16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_i16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_i16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_i16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_i16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_i32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_i32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_i32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_i32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_i32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_i64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_i64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_i64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_i64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_u8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_u8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_u8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_u8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_u8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_u8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_u8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_u16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_u16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_u16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_u16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_u16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_u16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_u32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_u32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_u32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_u32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_u32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_u64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_u64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_u64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_u64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/63140) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c846ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c846e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c846ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba2f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba2f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba2f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba2f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c846e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c846e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c846e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c846acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c846acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba2f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba2f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba2f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c846acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (6154 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 im
# | ...
# `---data was truncated (10240/78242) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a91906eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a91906be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a91906f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc43141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4314725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc43141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc431403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a919004bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a919004a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a918fe98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a918c98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a918c98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc431404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4314050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4314050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a918c98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (6155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebc699eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebc699be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebc699f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05f6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05f6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05f6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05f6c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebc6934bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebc6934a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebc69198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebc65c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebc65c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05f6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05f6c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05f6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebc65c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (6156 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055714b267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055714b264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055714b26862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055714b1fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055714b1fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055714b1e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055714ae91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055714ae91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fe831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055714ae91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (6158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a78c66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a78c63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a78c6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d23733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d2378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d23733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d2371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a78bfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a78bfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a78be18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a78890e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a78890b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d2371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d2371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d2371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a78890a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (6161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056263b883eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056263b880e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056263b88462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f544621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54462725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f544621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5446203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056263b819bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056263b819a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056263b7fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056263b4ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056263b4adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5446204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54462050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54462050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056263b4ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (6162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de651aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de651a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de651ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47f051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de65142bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de65142a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de651278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de64dd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de64dd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47f051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de64dd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (6165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8438e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8438dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8438e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57cfd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57cfd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57cfd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57cfced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e843878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e843878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e84385d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e84350ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e84350cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57cfceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57cfcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57cfcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e84350ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (6166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d0e24eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d0e24be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d0e24f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d50d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d0e1e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d0e1e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d0e1c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d0de78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d0de78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d0de78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (6168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5329dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5329d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5329dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f366501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36650725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f366501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3665003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c532972bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c532972a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5329578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c532606e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c532606b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3665004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36650050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36650050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c532606a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (6170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560045605eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560045602e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004560662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b4bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b4bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b4bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b4bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056004559bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056004559ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600455808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056004522fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056004522fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b4bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b4bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b4bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056004522fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (6171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c288e26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c288e23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c288e2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0667a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0667a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0667a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0667a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c288dbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c288dbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c288da18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c288a50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c288a50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0667a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0667a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0667a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c288a50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (6174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560342f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560342f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560342f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f94533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f9458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f94533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f9451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603428bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603428ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560342708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556033f1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556033f1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f9451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f9451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f9451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556033f1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (6175 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562ba4c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562ba4bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562ba4c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb10141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1014725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb10141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb101403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562ba456bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562ba456a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562ba43b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562ba0eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562ba0eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb101404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1014050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1014050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562ba0eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (6180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = ca
# | ...
# `---data was truncated (10240/67474) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad8d56ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad8d569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad8d56d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2702249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27022a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2702249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2702231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad8d502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad8d502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad8d4e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad8d196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad8d196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2702232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27022330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27022330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad8d196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (6182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1(<vscale x 8 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1(<vscale x 16 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1(<vscale x 32 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale
# | ...
# `---data was truncated (10240/40902) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a62fafceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a62faf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a62fafd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c22a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c22aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c22a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c22a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a62fa92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a62fa92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a62fa778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a62f726e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a62f726b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c22a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c22a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c22a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a62f726a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (6184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/12439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c500168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c500165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c50016962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25da133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25da18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25da133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25da11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5000febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5000fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5000e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4ffd92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4ffd92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25da11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25da11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25da11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4ffd92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (6185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de752ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560de7529e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560de752d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8886b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8886b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8886b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8886b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de74c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560de74c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560de74a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560de7156e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560de7156b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8886b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8886b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8886b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de7156a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (6186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e126e3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e126e38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e126e3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3648733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3648733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e126dd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e126dd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e126db68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e126a65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e126a65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f364871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e126a65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (6187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de8423feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de8423ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de8424062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6317933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f631798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6317933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f631791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de841d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de841d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de841ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de83e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de83e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f631791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f631791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f631791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de83e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (6188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c5664ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c56649e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c5664d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e7c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e7c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e7c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e7c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c565e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c565e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c565c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c56276e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c56276b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e7c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e7c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e7c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c56276a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (6189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591688f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591688f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591688f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055916888ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055916888ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591688738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559168522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559168522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559168522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (6190 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558359242eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055835923fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055835924362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf22f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf22f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf22f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf22f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583591d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583591d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583591bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558358e6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558358e6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf22f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf22f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf22f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558358e6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (6192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2d20feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2d20fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2d20ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc30a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc30a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc30a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc30a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2d2094bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2d2094a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2d20798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2d1d28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2d1d28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc30a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc30a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc30a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2d1d28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (6196 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b99911feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b99911ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b99912062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dc2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dc20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dc2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dc2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9990b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9990b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b99909a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b998d49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b998d49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dc2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dc20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dc20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b998d49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (6197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d3fd67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d3fd64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d3fd6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a53733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a5378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a53733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a5371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d3fcfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d3fcfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d3fce28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d3f991e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d3f991b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a5371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a5371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a5371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d3f991a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (6198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7db3b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7db3aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7db3b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ada305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ada35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ada305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ada2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7db347bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7db347a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7db32c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7dafdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7dafdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ada2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ada2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ada2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7dafdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (6203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba53cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba53cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba53cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e49305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e4935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e49305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e492ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba53c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba53c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba53c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba53926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba53926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e492eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e492ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e492ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba53926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (6204 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601a9b45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601a9b42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601a9b4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dce105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dce15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dce105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dce0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601a9adbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601a9adba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601a9ac08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601a976fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601a976fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dce0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dce0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dce0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601a976fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (6206 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 nou
# | ...
# `---data was truncated (10240/27442) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055575231beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555752318e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055575231c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ad6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ad6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ad6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ad6c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557522b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557522b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557522968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555751f45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555751f45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ad6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ad6c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ad6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555751f45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (6210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570234cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570234c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570234cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557023461bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557023461a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570234468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570230f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570230f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570230f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (6211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564519caceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564519ca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564519cad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cf9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cf915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cf9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cf90ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564519c42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564519c42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564519c278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645198d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645198d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cf90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cf90ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cf90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645198d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (6212 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c380a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c380a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c380a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e2761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e276725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e2761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e27603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c38039bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c38039a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c3801e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c37ccde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c37ccdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e27604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e276050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e276050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c37ccda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (6213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5d60dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5d60d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5d60dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d69649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d69649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d69631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5d6071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5d6071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5d60568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5d5d05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5d5d05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d69632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d696330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5d5d05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (6215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f758fcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f758fcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f758fd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a72733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a7278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a72733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a7271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f758f65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f758f65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f758f4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f758bf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f758bf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a7271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a7271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a7271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f758bf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (6216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055587a2f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055587a2f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055587a2f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4273849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4273849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4273831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055587a28ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055587a28ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055587a2738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555879f22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555879f22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4273832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42738330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555879f22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (6218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdc512feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdc512ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdc513062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f0e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f0e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f0e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f0e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdc50c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdc50c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdc50aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdc4d59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdc4d59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f0e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f0e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f0e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdc4d59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (6223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr 
# | ...
# `---data was truncated (10240/18895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055760ec77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055760ec74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055760ec7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a6a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a6a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a6a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a6a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055760ec0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055760ec0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055760ebf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055760e8a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055760e8a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a6a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a6a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a6a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055760e8a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (6225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641347cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641347c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641347cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5372f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5372f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5372f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5372f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564134762bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564134762a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641347478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641343f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641343f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5372f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5372f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5372f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641343f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (6226 of 27910)
******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | %struct.S = type { ptr, ptr }
# | %struct.T = type { [2 x ptr] }
# | %struct.SS = type { ptr }
# | 
# | @__hip_cuid_ = addrspace(1) global i8 0
# | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4
# |   %1 = load i32, ptr %0, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 {
# | entry:
# |   %x.addr = alloca ptr addrspace(2), align 8, addrspace(5)
# |   %y.addr = alloca ptr addrspace(1), align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr
# |   store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8
# |   store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8
# |   %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0
# |   %1 = load i32, ptr addrspace(2) %arrayidx, align 4
# |   %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8
# |   %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0
# |   store i32 %1, ptr addrspace(1) %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind
# | define dso_local void @_Z4funcPi(ptr noundef %x) #1 {
# | entry:
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr %x, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 {
# | entry:
# |   %s = alloca %struct.S, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %s.ascast = addrspacecast ptr addrspace(5) %s to ptr
# |   %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1
# |   %3 = load ptr, ptr %y, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %4, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 {
# | entry:
# |   %s = alloca ptr, align 8, addrspace(5)
# |   %s.addr = alloca ptr, align 8, addrspace(5)
# |   %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr
# |   store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8
# |   %s1 = load ptr, ptr addrspace(5) %s, align 8
# |   store ptr %s1, ptr %s.addr.ascast, align 8
# |   %0 = load ptr, ptr %s.addr.ascast, align 8
# |   %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %3 = load ptr, ptr %s.addr.ascast, align 8
# |   %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1
# |   %4 = load ptr, ptr %y, align 8
# |   %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0
# |   %5 = load float, ptr %arrayidx2, align 4
# |   %add = fadd contract float %5, 1.000000e+00
# |   store float %add, ptr %arrayidx2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 {
# | entry:
# |   %t = alloca %struct.T, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %t.ascast = addrspacecast ptr addrspace(5) %t to ptr
# |   %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0
# |   %1 = load ptr, ptr %arrayidx, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0
# |   %2 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %2, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1
# |   %3 = load ptr, ptr %arrayidx3, align 8
# |   %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx4, align 4
# |   %add5 = fadd contract float %4, 2.000000e+00
# |   store float %add5, ptr %arrayidx4, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 {
# | entry:
# |   %a = alloca %struct.SS, align 8, addrspace(5)
# |   %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0
# |   store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8
# |   %a.ascast = addrspacecast ptr addrspace(5) %a to ptr
# |   %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0
# |   %0 = load ptr, ptr %x, align 8
# |   %1 = load float, ptr %0, align 4
# |   %add = fadd contract float %1, 3.000000e+00
# |   store float %add, ptr %0, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !2 = !{!"clang version 24.0.0"}
# | !3 = !{}
# | !4 = !{i64 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x000055da9aa10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da9aa0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da9aa1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bf5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bf5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bf5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bf5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da9a9a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da9a9a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da9a98b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da9a63ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da9a63ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bf5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bf5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bf5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da9a63aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (6227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/41651) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a3333feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a3333ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a3334062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ff1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ff18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ff1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ff1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a332d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a332d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a332ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a32f69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a32f69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ff1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ff18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ff18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a32f69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (6228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/47706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e74275eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e74272e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e7427662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0232705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f023275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0232705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02326ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e7420bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e7420ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e741f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e73e9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e73e9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02326eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02326ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02326ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e73e9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (6229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c0ddf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c0ddf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c0ddf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff45b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff45b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff45b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff45b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c0dd89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c0dd89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c0dd6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c0da1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c0da1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff45b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff45b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff45b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c0da1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (6232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561852734eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561852731e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056185273562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b78733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b7878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b78733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b7871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618526cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618526caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618526af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056185235ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056185235eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b7871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b7871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b7871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056185235ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (6233 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056204fe37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056204fe34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056204fe3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf1c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf1c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf1c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf1c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056204fdcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056204fdcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056204fdb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056204fa61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056204fa61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf1c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf1c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf1c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056204fa61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (6236 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056069b72ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056069b729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056069b72d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1f5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1f5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1f5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1f5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056069b6c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056069b6c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056069b6a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056069b356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056069b356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1f5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1f5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1f5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056069b356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (6237 of 27910)
******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s0, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 
# | ...
# `---data was truncated (10240/18482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005632fdceaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632fdce7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632fdceb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa536a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa536aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa536a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa536a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632fdc80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632fdc80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632fdc658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632fd914e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632fd914b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa536a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa536a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa536a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632fd914a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (6239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646c795deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646c795ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646c795e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f1b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f1b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f1b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f1b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646c78f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646c78f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646c78d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646c7587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646c7587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f1b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f1b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f1b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646c7587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (6241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff94522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff9451fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff9452362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd73b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd73b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd73b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd73b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff944b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff944b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff9449d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff9414ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff9414cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd73b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd73b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd73b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff9414ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (6243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b676591eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b67658ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b67659262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51bc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51bc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51bc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51bc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b676527bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b676527a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b67650c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6761bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6761bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51bc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51bc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51bc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6761bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (6245 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055844b9eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055844b9ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055844b9ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdab7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdab7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdab7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdab7e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055844b984bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055844b984a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055844b9698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055844b618e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055844b618b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdab7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdab7e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdab7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055844b618a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (6247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1c5ec4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1c5ec1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1c5ec562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3e1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3e198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3e1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3e191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1c5e5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1c5e5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1c5e3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1c5aeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1c5aeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3e191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3e191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3e191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1c5aeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/arm-neon-vget.c (6253 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -target-abi apcs-gnu    -target-cpu cortex-a8    -mfloat-abi soft    -target-feature +soft-float-abi    -ffreestanding    -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x float> @low_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr
# | ...
# `---data was truncated (10240/15571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab5eba3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab5eba0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab5eba462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc35fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc35fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc35fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc35fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab5eb39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab5eb39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab5eb1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab5e7cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab5e7cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc35fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc35fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc35fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab5e7cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (6255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9bc643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9bc640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9bc64462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9525a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9525aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9525a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9525a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9bc5d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9bc5d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9bc5be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9bc26de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9bc26db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9525a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9525a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9525a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9bc26da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (6256 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577fb337eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577fb334e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577fb33862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e3b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e3b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e3b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e3b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577fb2cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577fb2cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577fb2b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577faf61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577faf61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e3b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e3b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e3b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577faf61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (6257 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056410ce38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056410ce35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056410ce3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1155c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1155ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1155c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1155c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056410cdcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056410cdcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056410cdb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056410ca62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056410ca62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1155c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1155c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1155c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056410ca62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (6258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5e0dd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5e0dd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5e0dd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f563b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f563b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f563b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f563b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5e0d6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5e0d6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5e0d508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5e09ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5e09ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f563b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f563b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f563b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5e09ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (6263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4d877ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4d8779e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4d877d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff178333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff17838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff178333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff17831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4d8712bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4d8712a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4d86f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4d83a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4d83a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff17831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff17831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff17831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4d83a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (6266 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 
# | ...
# `---data was truncated (10240/66065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4444d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4444d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4444d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa214449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa214449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa214431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e44446bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e44446ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4444508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4440ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4440ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa214432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2144330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4440ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (6269 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/67482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffc90fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffc90f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffc90fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4360133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f436018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4360133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f436011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffc9091bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffc9091a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffc90768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffc8d25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffc8d25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f436011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f436011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f436011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffc8d25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (6270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6a7e64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6a7e61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6a7e6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0a1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6a7dfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6a7dfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6a7ddf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6a7a8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6a7a8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6a7a8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (6271 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600fc27deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600fc27ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600fc27e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8746c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8746ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8746c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8746c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600fc213bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600fc213a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600fc1f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600fbea7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600fbea7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8746c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8746c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8746c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600fbea7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (6272 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564139e7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564139e7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564139e7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f776e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f776e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f776e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f776e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564139e14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564139e14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564139df98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564139aa8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564139aa8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f776e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f776e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f776e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564139aa8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (6274 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e1a5eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e1a5e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e1a5ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa66ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa66ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa66ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa66eced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e1a582bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e1a582a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e1a5678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e1a216e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e1a216b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa66eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa66ecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa66ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e1a216a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (6275 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f2b8c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f2b8bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f2b8c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe55ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe55ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe55ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe55ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f2b856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f2b856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f2b83b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f2b4eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f2b4eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe55ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe55ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe55ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f2b4eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (6276 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604d553aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604d5537e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604d553b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bce249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bce2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bce249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bce231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604d54d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604d54d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604d54b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604d5164e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604d5164b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bce232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bce2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bce2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604d5164a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (6280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e40328eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e40325e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e4032962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66b3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e402bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e402bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e402a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e3ff52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e3ff52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e3ff52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (6281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>
# | ...
# `---data was truncated (10240/43625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfeadeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfeade9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfeaded62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d30049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d30049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d30031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfead82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfead82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfead678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfeaa16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfeaa16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d30032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfeaa16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (6282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <
# | ...
# `---data was truncated (10240/66998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a5b9beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a5b9bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a5b9bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6883249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68832a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6883249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6883231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a5b954bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a5b954a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a5b9398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a5b5e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a5b5e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6883232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68832330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68832330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a5b5e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (6286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cbc2afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cbc2ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cbc2b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f02849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f02849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f02831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cbc245bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cbc245a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cbc22a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cbbed9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cbbed9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f02832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f028330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cbbed9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (6289 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.a
# | ...
# `---data was truncated (10240/63518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632ac77ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632ac779e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632ac77d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff28c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff28c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff28c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff28c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632ac712bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632ac712a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632ac6f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632ac3a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632ac3a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff28c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff28c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff28c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632ac3a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (6292 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567e436aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567e4367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567e436b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3700e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3700e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3700e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3700e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567e4300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567e4300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567e42e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567e3f94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567e3f94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3700e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3700e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3700e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567e3f94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (6293 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055900c2e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055900c2e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055900c2e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe16c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe16c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe16c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe16c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055900c27cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055900c27ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055900c2618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055900bf10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055900bf10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe16c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe16c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe16c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055900bf10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (6297 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555e0305eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555e0302e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555e030662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb526049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5260a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb526049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb526031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555e029bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555e029ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555e02808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555dff2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555dff2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb526032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5260330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5260330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555dff2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (6299 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66314) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a7783deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a7783ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a7783e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12ae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12ae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12ae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12ae31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a777d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a777d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a777b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a77467e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a77467b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12ae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12ae31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12ae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a77467a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (6300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %v
# | ...
# `---data was truncated (10240/43948) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcac45beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcac458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcac45c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc059933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc059933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc05991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcac3f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcac3f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcac3d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcac085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcac085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc05991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc05991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc05991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcac085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (6302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   
# | ...
# `---data was truncated (10240/12381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f320d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f320cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f320d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec0eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec0eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec0eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec0eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f32067bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f32067a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f3204c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f31cfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f31cfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec0eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec0eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec0eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f31cfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (6305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bdcf0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bdcf0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bdcf1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f925c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f925c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f925c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f925c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bdcea5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bdcea5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bdce8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bdcb39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bdcb39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f925c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f925c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f925c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bdcb39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (6313 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ccf3aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ccf3a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ccf3ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb16f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb16f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb16f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb16f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ccf340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ccf340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ccf3258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ccefd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ccefd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb16f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb16f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb16f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ccefd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (6314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556771278eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556771275e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055677127962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc92b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055677120ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055677120ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567711f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556770ea2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556770ea2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556770ea2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (6315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vas
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d1f887eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d1f884e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d1f88862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8adee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8adeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8adee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8adee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d1f81dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d1f81da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d1f8028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d1f4b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d1f4b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8adee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8adee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8adee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d1f4b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (6316 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd23c56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd23c53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd23c5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69ead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd23becbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd23beca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd23bd18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd23880e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd23880b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd23880a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (6317 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558e56dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558e56d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558e56dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558e5672bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558e5672a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558e56578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558e5306e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558e5306b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e5ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558e5306a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (6319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f27d3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f27d39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f27d3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f494dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f494dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f494dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f494dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f27cd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f27cd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f27cb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f27966e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f27966b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f494dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f494dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f494dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f27966a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (6322 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c04710aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c047107e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c04710b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facce249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facce2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facce249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facce231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0470a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0470a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0470858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c046d34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c046d34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facce232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facce2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facce2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c046d34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (6326 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.a
# | ...
# `---data was truncated (10240/41678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563293db4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563293db1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563293db562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa734333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa73438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa734333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa73431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563293d4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563293d4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563293d2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632939dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632939deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa73431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa73431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa73431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632939dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (6327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align
# | ...
# `---data was truncated (10240/14145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563808e71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563808e6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563808e7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fbf705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fbf75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fbf705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fbf6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563808e07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563808e07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563808dec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563808a9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563808a9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fbf6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fbf6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fbf6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563808a9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (6328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584e8b5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584e8b5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584e8b6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab4361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab436725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab4361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab43603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584e8af5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584e8af5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584e8ada8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584e8789e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584e8789b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab43604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab436050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab436050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584e8789a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (6329 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm
# | ...
# `---data was truncated (10240/53200) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b80fb5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b80fb5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b80fb5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3dad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b80faf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b80faf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b80fad98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b80f788e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b80f788b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b80f788a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (6330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d33b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d33b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d33b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cf7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cf7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cf7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cf7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d33ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d33ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d33ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d33768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d33768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cf7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cf7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cf7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d33768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (6332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580b4e66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580b4e63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580b4e6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7293b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7293b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7293b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7293b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580b4dfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580b4dfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580b4de18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580b4a90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580b4a90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7293b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7293b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7293b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580b4a90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (6333 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c689867eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c689864e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c68986862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6897fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6897fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6897e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c689491e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c689491b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fe251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c689491a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (6335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcffe51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fcffe4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fcffe5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1db4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1db40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1db4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1db4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcffde7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fcffde7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fcffdcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fcffa7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fcffa7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1db4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1db40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1db40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcffa7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (6336 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de6773eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564de6770e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564de677462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff53761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5376725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff53761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff537603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de6709bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564de6709a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564de66ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564de639de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564de639db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff537604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5376050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5376050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de639da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/arm-neon-dot-product.c (6340 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 8
# |   %__s0_827 = alloca <4 x i32>, align 8
# |   %__s1_827 = alloca <16 x i8>, align 8
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x i32>, align 8
# |   %tmp2 = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0_827, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %1, ptr %__s1_827, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 8
# |   %4 = load <16 x i8>, ptr %__s1_827, align 8
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1,
# | ...
# `---data was truncated (10240/18322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x0000563724149eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563724146e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056372414a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f601c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f601c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f601c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f601c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637240dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637240dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637240c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563723d73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563723d73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f601c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f601c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f601c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563723d73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (6342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align
# | ...
# `---data was truncated (10240/29111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5e0f9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5e0f9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5e0f9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8151133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f815118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8151133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f815111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5e0f33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5e0f33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5e0f188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5e0bc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5e0bc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f815111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f815111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f815111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5e0bc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (6343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/18303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e870a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e870a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e870a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa87c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa87c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa87c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa87c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e8703bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e8703ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e870208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e86ccfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e86ccfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa87c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa87c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa87c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e86ccfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (6344 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = all
# | ...
# `---data was truncated (10240/41587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dc438beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dc4388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dc438c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dc4321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dc4321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dc43068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dc3fb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dc3fb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dc3fb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (6345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloc
# | ...
# `---data was truncated (10240/71123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056427c351eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056427c34ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056427c35262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb46733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb4678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb46733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb4671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056427c2e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056427c2e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056427c2cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056427bf7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056427bf7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb4671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb4671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb4671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056427bf7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (6346 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcc2c1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcc2c19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcc2c1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbabac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbabac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbabac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbabac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcc2bb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcc2bb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcc2b978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcc2846e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcc2846b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbabac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbabac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbabac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcc2846a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (6349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc22c7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc22c7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc22c8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd003905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd00395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd003905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0038ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc22c15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc22c15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc22bfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc228a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc228a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0038eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0038ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0038ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc228a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (6352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621d553aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621d5537e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621d553b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd28933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd2898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd28933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd2891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621d54d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621d54d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621d54b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621d5164e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621d5164b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd2891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd2891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd2891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621d5164a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (6353 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c759c3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c759c37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c759c3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f978cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f978cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f978cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f978cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c759bd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c759bd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c759bb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c759864e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c759864b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f978cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f978cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f978cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c759864a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (6354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559738a89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559738a86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559738a8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56a9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56a9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56a9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56a9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559738a1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559738a1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559738a048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597386b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597386b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56a9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56a9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56a9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597386b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (6355 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4d3f32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4d3f2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4d3f3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc67ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc67eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc67ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc67ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4d3ec8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4d3ec8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4d3ead8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4d3b5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4d3b5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc67ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc67ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc67ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4d3b5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (6356 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/43515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b019d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b019d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b019d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f60249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f602a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f60249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f60231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b0196dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b0196da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b019528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b01601e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b01601b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f60232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f602330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f602330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b01601a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (6357 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056304a3d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056304a3cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056304a3d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feac9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feac9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feac9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feac9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056304a367bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056304a367a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056304a34c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563049ffbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563049ffbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feac9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feac9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feac9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563049ffba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (6358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056175d2a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056175d29de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056175d2a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effeaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effeaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effeaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effeaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056175d236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056175d236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056175d21b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056175cecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056175cecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effeaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effeaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effeaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056175cecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (6359 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/32709) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056200198aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562001987e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056200198b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb25d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb25d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb25d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb25d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562001920bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562001920a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620019058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620015b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620015b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb25d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb25d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb25d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620015b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (6360 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b749e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b749e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b749e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0aca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0aca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0aca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0aca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b749daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b749daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b749d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b749a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b749a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0aca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0aca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0aca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b749a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (6362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055928f876eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055928f873e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055928f87762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6af8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6af88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6af8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6af8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055928f80cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055928f80ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055928f7f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055928f4a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055928f4a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6af8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6af88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6af88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055928f4a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (6363 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/31868) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589af82feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589af82ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589af83062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67bf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67bf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67bf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67bf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589af7c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589af7c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589af7aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589af459e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589af459b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67bf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67bf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67bf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589af459a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (6364 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613db95beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613db958e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613db95c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e98e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e98e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e98e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e98e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613db8f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613db8f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613db8d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613db585e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613db585b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e98e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e98e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e98e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613db585a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (6366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056193c601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056193c5fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056193c60262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8702c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8702ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8702c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8702c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056193c597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056193c597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056193c57c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056193c22be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056193c22bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8702c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8702c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8702c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056193c22ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (6371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da84badeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da84baae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da84bae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fe3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fe315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fe3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fe30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da84b43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da84b43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da84b288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da847d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da847d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fe30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fe30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fe30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da847d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (6374 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a92a6aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a92a6a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a92a6ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f929c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f929c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f929c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f929c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a92a640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a92a640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a92a6258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a92a2d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a92a2d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f929c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f929c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f929c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a92a2d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (6376 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/68133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de33fb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de33fb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de33fb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd081649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0816a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd081649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd081631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de33f4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de33f4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de33f318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de33be0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de33be0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd081632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0816330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0816330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de33be0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (6378 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d77ea60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d77ea5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d77ea6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa684f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa684f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa684f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa684f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d77e9f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d77e9f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d77e9db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d77e68ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d77e68ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa684f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa684f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa684f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d77e68aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (6380 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/18353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3ad697eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3ad694e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3ad69862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9653849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96538a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9653849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9653831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3ad62dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3ad62da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3ad6128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3ad2c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3ad2c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9653832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96538330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96538330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3ad2c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (6382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/68073) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a129dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a129dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a129dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d64449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d64449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d64431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a129d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a129d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a129d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1299f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1299f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d64432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d644330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1299f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (6384 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615bcd4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615bcd4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615bcd4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd22533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd2258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd22533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd2251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615bcce3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615bcce3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615bccc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615bc977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615bc977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd2251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd2251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd2251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615bc977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (6385 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 
# | ...
# `---data was truncated (10240/43617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc12ce4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc12ce1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc12ce562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86e0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86e015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86e0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86e00ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc12c7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc12c7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc12c5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc1290ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc1290eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86e00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86e00ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86e00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc1290ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (6387 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac05685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac05682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac0568662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc44d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc44d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc44d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc44d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0561bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac0561ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac056008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac052afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac052afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc44d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc44d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc44d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac052afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (6388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3,
# | ...
# `---data was truncated (10240/29443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056097c5ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056097c5fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056097c60062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60e181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60e18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60e181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60e1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056097c595bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056097c595a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056097c57a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056097c229e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056097c229b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60e1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60e18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60e18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056097c229a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (6390 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c100331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c10032ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c10033262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f6951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1002c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1002c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1002ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0fff5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0fff5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f6951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0fff5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (6391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b044fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b044f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b044fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfeda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfedaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfeda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfeda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b044f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b044f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b044f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b044bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b044bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfeda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfeda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfeda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b044bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (6392 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d39b73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d39b70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d39b7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46e4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46e4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46e4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46e4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d39b09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d39b09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d39aee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d3979de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d3979db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46e4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46e4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46e4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d3979da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (6393 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563194444eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563194441e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056319444562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9185d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9185d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9185d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9185d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631943dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631943daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631943bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056319406ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056319406eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9185d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9185d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9185d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056319406ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (6395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de34403eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de34400e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de3440462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae43733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae4378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae43733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae4371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de34399bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de34399a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de3437e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de3402de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de3402db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae4371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae4371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae4371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de3402da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (6396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582d8b0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582d8b0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582d8b0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7403f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7403f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7403f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7403eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582d8aa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582d8aa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582d8a898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582d8738e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582d8738b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7403eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7403eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7403eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582d8738a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (6398 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eac4875eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eac4872e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eac487662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eac480bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eac480ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eac47f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eac449fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eac449fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eac449fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (6399 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056182bf52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056182bf4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056182bf5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7bcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7bcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7bcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7bcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056182bee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056182bee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056182becd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056182bb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056182bb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7bcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7bcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7bcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056182bb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (6400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf29008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf29005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf2900962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7efc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7efc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7efc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7efc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf28f9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf28f9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf28f838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf28c32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf28c32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7efc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7efc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7efc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf28c32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (6401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #
# | ...
# `---data was truncated (10240/26584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f8bc71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f8bc6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f8bc7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9d5d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9d5d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9d5d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9d5ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f8bc07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f8bc07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f8bbec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f8b89be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f8b89bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9d5ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9d5cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9d5cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f8b89ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (6402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580a38fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580a38f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580a38fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0134a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0134aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0134a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0134a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580a3892bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580a3892a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580a38778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580a3526e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580a3526b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0134a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0134a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0134a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580a3526a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (6404 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/58460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632a32a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632a329ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632a32a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3265333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f326538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3265333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f326531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632a3237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632a3237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632a321c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632a2ecbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632a2ecbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f326531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f326531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f326531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632a2ecba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (6407 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/62964) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f40ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622f40dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622f40de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9340c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9340ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9340c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9340c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f4073bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622f4073a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622f40588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622f3d07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622f3d07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9340c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9340c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9340c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f3d07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (6409 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c156daaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c156da7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c156dab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e13d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e13d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e13d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e13d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c156d40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c156d40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c156d258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1569d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1569d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e13d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e13d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e13d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1569d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (6411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.
# | ...
# `---data was truncated (10240/14900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d0cc12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d0cc0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d0cc1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f17733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f1778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f17733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f1771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d0cba8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d0cba8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d0cb8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d0c83ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d0c83cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f1771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f1771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f1771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d0c83ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (6412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aafc1e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aafc1e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aafc1e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e0f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e0f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e0f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e0f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aafc17abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aafc17aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aafc15f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aafbe0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aafbe0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e0f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e0f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e0f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aafbe0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (6413 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %bas
# | ...
# `---data was truncated (10240/60209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562792467eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562792464e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056279246862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb462e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb462ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb462e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb462e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627923fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627923fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627923e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562792091e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562792091b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb462e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb462e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb462e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562792091a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (6414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vsc
# | ...
# `---data was truncated (10240/41425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ef7fbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ef7fbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ef7fbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9a3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9a3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9a3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9a3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ef7f54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ef7f54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ef7f398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ef7be8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ef7be8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9a3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9a3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9a3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ef7be8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (6418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b41ed47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b41ed44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b41ed4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2ccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2ccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2ccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2ccb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b41ecddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b41ecdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b41ecc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b41e971e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b41e971b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2ccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2ccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2ccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b41e971a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (6420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f617a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f617a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f617a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b08449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b084a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b08449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b08431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f6173abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f6173aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f6171f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f613cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f613ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b08432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b084330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b084330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f613cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (6421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.r
# | ...
# `---data was truncated (10240/33423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056159623eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056159623be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056159623f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0461a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0461aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0461a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0461a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615961d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615961d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615961b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561595e68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561595e68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0461a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0461a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0461a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561595e68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (6422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fbd2fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fbd2fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fbd2fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93d7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93d7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93d7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93d7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbd293bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fbd293a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fbd2788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fbcf27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fbcf27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93d7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93d7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93d7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fbcf27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (6425 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b9708ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b97089e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b9708d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8100f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8100f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8100f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8100f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b97022bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b97022a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b970078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b96cb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b96cb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8100f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8100f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8100f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b96cb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (6427 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, 
# | ...
# `---data was truncated (10240/60217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f0fc23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f0fc20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f0fc2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd05e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd05e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd05e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd05e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f0fbb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f0fbb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f0fb9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f0f84de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f0f84db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd05e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd05e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd05e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f0f84da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (6429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vs
# | ...
# `---data was truncated (10240/32206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b03750deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b03750ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b03750e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f658b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f658b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f658b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f658b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0374a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0374a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0374888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b037137e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b037137b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f658b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f658b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f658b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b037137a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (6433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cef78eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cef78be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cef78f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faebf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faebf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faebf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faebf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cef724bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cef724a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cef7098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cef3b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cef3b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faebf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faebf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faebf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cef3b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (6434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.
# | ...
# `---data was truncated (10240/28427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d77374eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d77371e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d7737562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fcc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fcc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fcc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fcc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d7730abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d7730aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d772ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d76f9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d76f9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fcc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fcc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fcc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d76f9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (6437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   s
# | ...
# `---data was truncated (10240/69534) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d797c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d797bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d797c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0eabf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0eabf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0eabf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0eabf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d79756bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d79756a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d7973b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d793eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d793eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0eabf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0eabf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0eabf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d793eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (6438 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b254c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b254bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b254c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f218bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f218bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f218bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f218bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b25458bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b25458a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b2543d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b250ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b250ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f218bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f218bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f218bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b250eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (6439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559752513eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559752510e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055975251462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dc3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dc398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dc3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dc391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597524a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597524a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055975248e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055975213de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055975213db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dc391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dc391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dc391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055975213da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (6440 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/26748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a10f53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a10f50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a10f5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62fc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a10ee9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a10ee9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a10ece8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a10b7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a10b7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62fc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a10b7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (6441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610fc577eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610fc574e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610fc57862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610fc50dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610fc50da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610fc4f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610fc1a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610fc1a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5c0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610fc1a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (6443 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2de60feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2de60ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2de61062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d3a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d3a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d3a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d3a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2de5a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2de5a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2de58a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2de239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2de239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d3a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d3a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d3a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2de239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (6444 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i
# | ...
# `---data was truncated (10240/51295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f35af48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f35af45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f35af4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d62649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d626a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d62649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d62631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f35aedebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f35aedea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f35aec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f35ab72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f35ab72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d62632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d626330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d626330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f35ab72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (6445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac93506eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac93503e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac9350762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f552b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f552b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f552b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f552b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac9349cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac9349ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac934818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac93130e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac93130b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f552b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f552b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f552b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac93130a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (6446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.
# | ...
# `---data was truncated (10240/16654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558a0d64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558a0d61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558a0d6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f799f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f799f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f799f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f799f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558a0cfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558a0cfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558a0cdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558a098ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558a098eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f799f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f799f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f799f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558a098ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (6452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa837c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa837c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa837c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe402a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe402aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe402a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe402a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8375dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa8375da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa837428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa833f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa833f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe402a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe402a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe402a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa833f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/arm-neon-shifts.c (6454 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -disable-O0-optnone    -target-cpu cortex-a8    -ffreestanding    -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"apcs-gnu"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579898b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579898b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579898b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e34b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e34b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e34b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e34b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055798984ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055798984ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579898338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579894e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579894e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e34b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e34b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e34b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579894e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (6456 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557993debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557993de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557993dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb0f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557993d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557993d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557993d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557993a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557993a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb0f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557993a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (6457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5646b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5646b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5646b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc5d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc5d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc5d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc5d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c56464bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c56464ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5646308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5642dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5642dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc5d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc5d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc5d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5642dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (6459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %
# | ...
# `---data was truncated (10240/13308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561763474eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561763471e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056176347562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f234f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f234f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f234f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f234f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056176340abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056176340aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617633ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056176309ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056176309eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f234f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f234f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f234f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056176309ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (6462 of 27910)
******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc    -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | $__profc__Z6helperi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6helperi = comdat any
# | 
# | $__profc__Z6kernelPi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6kernelPi = comdat any
# | 
# | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0
# | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8
# | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8
# | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1
# | @__start___llvm_prf_names = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_names = external hidden addrspace(1) global i8
# | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__start___llvm_prf_data = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_data = external hidden addrspace(1) global i8
# | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__llvm_profile_raw_version = external addrspace(1) constant i64
# | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version }
# | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %x.addr = alloca i32, align 4, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store i32 %x, ptr %x.addr.ascast, align 4
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load i32, ptr %x.addr.ascast, align 4
# |   %add = add nsw i32 %1, 1
# |   ret i32 %add
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
# | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %p = alloca ptr, align 8, addrspace(5)
# |   %p.addr = alloca ptr, align 8, addrspace(5)
# |   %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr
# |   store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8
# |   %p1 = load ptr, ptr addrspace(5) %p, align 8
# |   store ptr %p1, ptr %p.addr.ascast, align 8
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load ptr, ptr %p.addr.ascast, align 8
# |   %2 = load i32, ptr %1, align 4
# |   %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4
# |   %3 = load ptr, ptr %p.addr.ascast, align 8
# |   store i32 %call, ptr %3, align 4
# |   ret void
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | declare i32 @__llvm_profile_sampling_gpu(i32)
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3
# | 
# | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64)
# | 
# | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { nounwind }
# | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #4 = { convergent nounwind "uniform-work-group-size" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 2, !"EnableValueProfiling", i32 0}
# | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# |  #0 0x0000557663458eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557663455e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055766345962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6df505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6df55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6df505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6df4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576633eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576633eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576633d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557663082e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557663082b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6df4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6df4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6df4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557663082a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (6463 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056516f012eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056516f00fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056516f01362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f867a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f867a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f867a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f867a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056516efa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056516efa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056516ef8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056516ec3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056516ec3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f867a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f867a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f867a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056516ec3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (6464 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e316b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e316b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e316b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3f7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3f76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3f7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3f7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e3164cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e3164ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e316318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e312e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e312e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3f7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3f76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3f76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e312e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (6465 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loca
# | ...
# `---data was truncated (10240/18587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b5f4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615b5f4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615b5f4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20f691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b5ee4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615b5ee4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615b5ec98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615b5b78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615b5b78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20f691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615b5b78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (6466 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 =
# | ...
# `---data was truncated (10240/39218) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cd0d9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cd0d98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cd0d9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f676381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67638725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f676381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6763803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cd0d31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cd0d31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cd0d168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cd09c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cd09c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6763804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67638050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67638050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cd09c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (6468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c74be3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c74be0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c74be462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56ea133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56ea18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56ea133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56ea11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c74b79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c74b79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c74b5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c7480de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c7480db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56ea11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56ea11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56ea11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c7480da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (6469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564a721feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564a721ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564a722062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f660ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f660ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f660ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f660ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564a71b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564a71b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564a719a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564a6e49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564a6e49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f660ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f660ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f660ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564a6e49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (6470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587d9814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587d9811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587d981562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3243449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32434a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3243449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3243431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587d97aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587d97aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587d978f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587d943ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587d943eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3243432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32434330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32434330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587d943ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (6473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632e1c7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632e1c7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632e1c8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4827049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4827049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4827031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632e1c15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632e1c15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632e1bfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632e18a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632e18a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4827032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632e18a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (6474 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591dc673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591dc670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591dc67462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40fbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591dc609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591dc609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591dc5ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591dc29de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591dc29db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40fbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591dc29da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (6475 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> poison, i64 %0)
# |   ret <vscale x 1 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> poison, i64 %0)
# |   ret <vscale x 2 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> poison, i64 %0)
# |   ret <vscale x 4 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> poison, i64 %0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> poison, i64 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> poison, i64 %0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> poison, i64 %0)
# |   ret <vscale x 64 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> poison, i64 %0)
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> poison, i64 %0)
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> poison, i64 %0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> poison, i64 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> poison, i64 %0)
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> poison, i64 %0)
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> poison, i64 %0)
# |   ret <vscale x 1 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vid_v_u32m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> poison, i64 %0)
# |   ret <vscale x 2 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vid_v_u32m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> poison, i64 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vid_v_u32m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> poison, i64 %0)
# |   ret <vscale x 8 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vid_v_u32m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> poison, i64 %0)
# |   ret <vscale x 16 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vid_v_u64m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/30303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e9c5b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e9c5aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e9c5b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cf3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cf335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cf3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cf32ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e9c547bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e9c547a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e9c52c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e9c1dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e9c1dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cf32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cf32ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cf32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e9c1dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (6476 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c247efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c247ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c247f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b8a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b8a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b8a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b8a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c24785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c24785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c2476a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c24419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c24419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b8a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b8a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b8a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c24419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (6477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e06aa4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e06aa1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e06aa562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc77ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc77ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc77ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc77ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e06a3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e06a3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e06a1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e066cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e066ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc77ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc77ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc77ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e066cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (6478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.n
# | ...
# `---data was truncated (10240/33624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625db19deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625db19ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625db19e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa95de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa95de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa95de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa95de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625db133bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625db133a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625db1188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625dadc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625dadc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa95de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa95de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa95de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625dadc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/arm-neon-vcadd.c (6479 of 27910)
******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic  -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.3a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i)
# |   %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i)
# |   %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i)
# |   %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %result = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i)
# |   %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i)
# |   %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i)
# |   %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i)
# |   %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 
# | ...
# `---data was truncated (10240/13572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# |  #0 0x0000555c156cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c156c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c156cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5df3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5df398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5df3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5df391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c15662bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c15662a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c156478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c152f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c152f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5df391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5df391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5df391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c152f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (6481 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567e560feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567e560ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567e561062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1357733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f135778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1357733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f135771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567e55a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567e55a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567e558a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567e5239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567e5239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f135771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f135771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f135771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567e5239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (6482 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/32701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557586dd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557586dd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557586dd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f220ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f220ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f220ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f220ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557586d6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557586d6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557586d528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557586a01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557586a01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f220ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f220ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f220ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557586a01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (6485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da2c7adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da2c7aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da2c7ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ce2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ce2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ce2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ce2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da2c743bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da2c743a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da2c7288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da2c3d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da2c3d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ce2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ce2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ce2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da2c3d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (6490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.
# | ...
# `---data was truncated (10240/24951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056127053eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056127053be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056127053f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb2fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb2fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb2fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb2faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612704d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612704d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612704b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561270168e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561270168b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb2faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb2faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb2faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561270168a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (6491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609440f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609440f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609440f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe65ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe65ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056094408abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056094408aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056094406f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560943d1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560943d1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe65ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560943d1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (6492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x
# | ...
# `---data was truncated (10240/29379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f81cf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f81cf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f81cf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bdf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bdf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bdf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bdf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f81c8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f81c8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f81c728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f81921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f81921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bdf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bdf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bdf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f81921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (6493 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ba382beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ba3828e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ba382c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25b5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ba37c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ba37c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ba37a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ba3455e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ba3455b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ba3455a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (6494 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/15718) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056494d4edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056494d4eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056494d4ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb77c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb77c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb77c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb77c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056494d483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056494d483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056494d4688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056494d117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056494d117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb77c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb77c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb77c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056494d117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (6497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2dbb41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2dbb3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2dbb4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c18249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c18249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c18231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2dbad7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2dbad7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2dbabc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2db76be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2db76bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c18232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c182330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2db76ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (6498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/12389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055727428beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557274288e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055727428c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4809305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f480935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4809305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48092ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557274221bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557274221a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572742068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557273eb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557273eb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48092eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48092ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48092ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557273eb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (6499 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3614f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3614f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3614f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b36148abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b36148aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b36146f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b36111ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b36111eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11f3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b36111ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (6502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563322e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563322e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563322ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbaae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbaae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbaae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbaae231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055633227fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055633227fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563322648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556331f13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556331f13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbaae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbaae2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbaae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556331f13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (6503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/68067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3285e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3285e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3285e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9322333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f932238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9322333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f932231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e32857abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e32857aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e32855f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e32820ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e32820eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f932231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f932231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f932231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32820ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (6504 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.a
# | ...
# `---data was truncated (10240/32394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560009d54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560009d51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560009d5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe244449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe244449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe244431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560009ceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560009ceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560009ccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056000997ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056000997eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe244432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2444330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056000997ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (6505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f4d41beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f4d418e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f4d41c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33dde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33ddea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33dde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33dde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f4d3b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f4d3b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f4d3968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f4d045e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f4d045b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33dde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33dde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33dde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f4d045a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (6508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a59ec1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a59ebee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a59ec262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4a071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a59e57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a59e57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a59e3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a59aebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a59aebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4a071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a59aeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (6511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b54e5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b54e57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b54e5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa526a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa526aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa526a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa526a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b54df0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b54df0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b54dd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b54a84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b54a84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa526a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa526a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa526a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b54a84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (6512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i
# | ...
# `---data was truncated (10240/51303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559083689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559083686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055908368a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9188849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91888a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9188849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9188831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055908361fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055908361fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590836048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590832b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590832b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9188832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91888330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91888330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590832b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (6517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb696eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb696ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb696ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c2eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c2eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c2eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c2eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb69684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb69684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb696698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb69318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb69318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c2eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c2eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c2eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb69318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (6518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605b06c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605b06c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605b06c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fbe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fbe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fbe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fbe91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605b065dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605b065da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605b06428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605b02f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605b02f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fbe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fbe91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fbe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605b02f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (6519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583d226aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583d2267e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583d226b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e78d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e78d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e78d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e78d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583d2200bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583d2200a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583d21e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583d1e94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583d1e94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e78d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e78d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e78d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583d1e94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (6522 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564071114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564071111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056407111562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9b9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9b92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9b9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9b9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640710aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640710aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056407108f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564070d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564070d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9b9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9b92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9b92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564070d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (6523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628e5b49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628e5b46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628e5b4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36e0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36e0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36e0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36e0c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628e5adfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628e5adfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628e5ac48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628e5773e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628e5773b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36e0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36e0c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36e0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628e5773a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (6524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32
# | ...
# `---data was truncated (10240/75405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596d24bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d24b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d24bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0805905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f080595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0805905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08058ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d2452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d2452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d24378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d20e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d20e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08058eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08058ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08058ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d20e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (6526 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605736bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605736bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605736c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f481e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f481e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f481e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f481e4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560573655bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560573655a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056057363a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605732e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605732e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f481e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f481e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f481e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605732e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (6527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a2d0f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a2d0f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a2d0f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07c5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07c56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07c5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07c5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a2d08cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a2d08ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a2d0718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a2cd20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a2cd20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07c5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07c56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07c56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a2cd20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (6528 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca targe
# | ...
# `---data was truncated (10240/53556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4b4cb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4b4cb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4b4cb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8431f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8431f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8431f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8431f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4b4c49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4b4c49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4b4c2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4b48dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4b48ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8431f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8431f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8431f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4b48dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (6529 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ab95f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ab95f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ab95f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe62af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe62af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe62af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe62af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ab958dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ab958da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ab95728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ab9221e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ab9221b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe62af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe62af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe62af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ab9221a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (6530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> po
# | ...
# `---data was truncated (10240/50898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee40f7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee40f7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee40f7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ad1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ad1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ad1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ad1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee40f14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee40f14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee40ef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee40ba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee40ba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ad1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ad1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ad1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee40ba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (6532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a094d86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a094d83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a094d8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff94ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff94ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff94ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff94ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a094d1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a094d1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a094d018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0949b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0949b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff94ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff94ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff94ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0949b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (6533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f639a58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f639a55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f639a5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a47f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a47f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a47f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a47eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6399eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6399eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6399d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f639682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f639682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a47eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a47eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a47eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f639682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (6535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c70fa54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c70fa51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c70fa5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8bbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8bbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8bbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8bbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c70f9eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c70f9eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c70f9cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c70f67ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c70f67eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8bbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8bbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8bbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c70f67ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (6537 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3b7d23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3b7d20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3b7d2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6813b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6813b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6813b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6813b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3b7cb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3b7cb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3b7c9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3b794de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3b794db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6813b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6813b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6813b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3b794da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (6538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d28cd91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d28cd8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d28cd9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb9d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb9d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb9d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb9d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d28cd27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d28cd27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d28cd0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d28c9bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d28c9bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb9d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb9d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb9d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d28c9bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (6541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bee3f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bee3f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bee3f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1879f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1879f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1879f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1879f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bee38ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bee38ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bee3738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bee022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bee022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1879f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1879f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1879f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bee022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (6542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5fc650eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5fc64de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5fc65162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c35733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c3578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c35733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c3571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5fc5e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5fc5e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5fc5cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5fc27ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5fc27ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c3571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c3571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c3571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5fc27aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (6543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056214c85feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056214c85ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056214c86062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76b4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76b48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76b4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76b4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056214c7f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056214c7f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056214c7da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056214c489e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056214c489b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76b4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76b48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76b48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056214c489a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (6544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c5c995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c5c992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c5c99662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd03d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd03d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd03d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd03d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c5c92bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c5c92ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c5c9108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c5c5bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c5c5bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd03d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd03d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd03d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c5c5bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (6545 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056323862eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056323862be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056323862f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f836b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f836b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f836b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f836b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632385c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632385c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632385a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563238258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563238258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f836b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f836b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f836b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563238258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (6546 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 
# | ...
# `---data was truncated (10240/26572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572a4bc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572a4bc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572a4bc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0af2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0af2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0af2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0af2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572a4b5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572a4b5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572a4b438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572a47f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572a47f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0af2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0af2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0af2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572a47f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (6547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 
# | ...
# `---data was truncated (10240/14429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a662c2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a662c2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a662c3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb2721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb272725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb2721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb27203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a662bc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a662bc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a662baa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a662859e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a662859b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb27204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb272050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb272050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a662859a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (6548 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b7bc30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b7bc2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b7bc3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18d1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18d16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18d1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18d1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b7bbc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b7bbc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b7bbab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b7b85ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b7b85ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18d1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18d16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18d16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b7b85aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (6549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff2f942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff2f93fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff2f94362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faec6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faec6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faec6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faec6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff2f8d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff2f8d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff2f8bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff2f56ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff2f56cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faec6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faec6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faec6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff2f56ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (6550 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613fad5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613fad5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613fad6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f27e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f27e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f27e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f27e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613facf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613facf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613facda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613fa989e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613fa989b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f27e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f27e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f27e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613fa989a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (6551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/71947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571bac6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571bac6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571bac7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26f8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26f898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26f8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26f891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571bac05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571bac05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571babea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571ba899e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571ba899b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26f891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26f891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26f891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571ba899a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (6552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056490bb81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056490bb7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056490bb8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e71533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e7158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e71533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e7151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056490bb17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056490bb17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056490bafc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056490b7abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056490b7abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e7151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e7151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e7151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056490b7aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (6553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/68141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608d1ca8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608d1ca5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608d1ca962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fba01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fba0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fba01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fba003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d1c3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608d1c3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608d1c238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608d18d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608d18d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fba004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fba0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fba0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d18d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (6554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c626593eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c626590e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c62659462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f356af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f356af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f356af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f356af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c626529bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c626529a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c62650e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6261bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6261bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f356af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f356af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f356af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6261bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (6555 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %
# | ...
# `---data was truncated (10240/21774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557ec27ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557ec279e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557ec27d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b4d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b4d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557ec212bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557ec212a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557ec1f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557ebea6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557ebea6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b4d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557ebea6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (6558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae4f956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae4f953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae4f95762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff19fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff19fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff19fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff19fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae4f8ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae4f8eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae4f8d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae4f580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae4f580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff19fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff19fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff19fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae4f580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (6561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16
# | ...
# `---data was truncated (10240/15367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcbb2f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcbb2f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcbb2f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1a1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1a1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1a1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1a1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcbb28ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcbb28ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcbb2738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcbaf22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcbaf22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1a1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1a1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1a1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcbaf22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (6563 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605765beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605765bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605765bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a02849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a02849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a02831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560576554bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560576554a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605765398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605761e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605761e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a02832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a028330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605761e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (6564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, bflo
# | ...
# `---data was truncated (10240/43940) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e3d692eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e3d68fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e3d69362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c2f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c2f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c2f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c2f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e3d628bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e3d628a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e3d60d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e3d2bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e3d2bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c2f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c2f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c2f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e3d2bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (6568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c58a39beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c58a398e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c58a39c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7197f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7197f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7197f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7197f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c58a331bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c58a331a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c58a3168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c589fc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c589fc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7197f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7197f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7197f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c589fc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (6569 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558991f37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558991f34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558991f3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdeb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdeb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdeb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdeb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558991ecdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558991ecda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558991eb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558991b61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558991b61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdeb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdeb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdeb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558991b61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (6570 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e67870eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e6786de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e6787162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f888c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f888c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f888c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f888c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e67806bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e67806a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e677eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e6749ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e6749ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f888c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f888c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f888c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e6749aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (6572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 64 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, al
# | ...
# `---data was truncated (10240/30013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056301db85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056301db82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056301db8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f7b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f7b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f7b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f7b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301db1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056301db1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056301db008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056301d7afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056301d7afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f7b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f7b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f7b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301d7afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (6575 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/64349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb51a94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb51a91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb51a9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f129f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f129f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f129f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f129f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb51a2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb51a2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb51a0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb516bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb516beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f129f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f129f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f129f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb516bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (6576 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c99a76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c99a73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c99a7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24d9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24d995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24d9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24d98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c99a0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c99a0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c999f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c996a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c996a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24d98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24d98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24d98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c996a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (6577 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | 
# | ...
# `---data was truncated (10240/12652) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfb1e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfb1e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfb1e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c77705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c7775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c77705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c776ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfb1dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfb1dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfb1da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfb1a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfb1a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c776eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c776ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c776ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfb1a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (6578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a30a19eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a30a19be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a30a19f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2639933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2639933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a30a134bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a30a134a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a30a1198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a309dc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a309dc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f263991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a309dc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (6580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/25279) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635e3c60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635e3c5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635e3c6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f197de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f197dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f197de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f197de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635e3bf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635e3bf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635e3bdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635e388ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635e388ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f197de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f197de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f197de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635e388aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (6581 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c363f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c363eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c363f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2da2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2da2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2da2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2da2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c36387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c36387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c3636c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c3601be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c3601bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2da2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2da2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2da2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c3601ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (6584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/41102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056160ba6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056160ba6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056160ba6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc516e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc516ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc516e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc516e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056160ba04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056160ba04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056160b9e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056160b698e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056160b698b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc516e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc516e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc516e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056160b698a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (6587 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/29371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cffbf89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cffbf86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cffbf8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cffbf1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cffbf1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cffbf048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cffbbb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cffbbb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff1bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cffbbb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (6588 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/12656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c23f4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c23f4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c23f4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f607c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f607c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f607c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f607c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c23ee3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c23ee3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c23ec88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c23b77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c23b77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f607c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f607c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f607c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c23b77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (6589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f6c598eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f6c595e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f6c59962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44d611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6c52ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f6c52ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f6c5138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f6c1c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f6c1c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44d611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f6c1c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (6590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |  
# | ...
# `---data was truncated (10240/30268) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624888afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624888ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624888b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f803d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f803d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f803d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f803d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562488845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562488845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056248882a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624884d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624884d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f803d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f803d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f803d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624884d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (6591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b563a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b5639fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b563a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1464f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1464f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1464f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1464f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b56338bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b56338a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b5631d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b55fcce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b55fccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1464f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1464f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1464f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b55fcca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (6592 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstrid
# | ...
# `---data was truncated (10240/28111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8de759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8de756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8de75a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dee41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dee4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dee41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dee403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8de6efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8de6efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8de6d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8de383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8de383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dee404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dee4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dee4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8de383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (6593 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620317faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620317f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620317fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff543c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff543ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff543c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff543c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562031790bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562031790a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620317758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562031424e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562031424b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff543c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff543c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff543c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562031424a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (6594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedo
# | ...
# `---data was truncated (10240/30751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640588e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640588e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640588e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f105ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f105ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f105ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f105ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056405887cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056405887ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640588618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564058510e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564058510b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f105ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f105ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f105ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564058510a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (6596 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055920c7eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055920c7e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055920c7eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f238b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f238b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f238b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f238b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055920c780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055920c780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055920c7658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055920c414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055920c414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f238b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f238b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f238b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055920c414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (6597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb17fc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb17fc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb17fc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33bcd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33bcd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33bcd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33bcced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb17f5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb17f5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb17f418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb17bf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb17bf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33bcceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33bccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33bccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb17bf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (6599 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055856bc95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055856bc92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055856bc9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f001a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f001a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f001a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f001a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055856bc2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055856bc2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055856bc108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055856b8bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055856b8bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f001a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f001a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f001a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055856b8bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (6603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559314682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055931467fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055931468362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2c1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2c1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2c1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2c1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559314618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559314618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593145fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593142ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593142acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2c1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2c1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2c1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593142aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (6605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560886f81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560886f7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560886f8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc510449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5104a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc510449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc510431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560886f17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560886f17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560886efc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560886babe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560886babb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc510432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5104330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5104330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560886baba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (6607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d62802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d627ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d6280362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e05133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e0518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e05133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e0511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d62798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d62798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d6277d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d6242ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d6242cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e0511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e0511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e0511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d6242ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (6609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee2da4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ee2da1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ee2da562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09f9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09f9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09f9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09f9e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee2d3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ee2d3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ee2d1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ee29cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ee29ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09f9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09f9e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09f9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee29cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (6610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612efe25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612efe22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612efe2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a04533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a0458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a04533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a0451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612efdbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612efdbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612efda08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612efa4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612efa4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a0451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a0451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a0451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612efa4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (6611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5c1867eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5c1864e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5c186862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ffa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ffa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ffa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ffa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5c17fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5c17fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5c17e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5c1491e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5c1491b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ffa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ffa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ffa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5c1491a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (6612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d5a824eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d5a821e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d5a82562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30fc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30fc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30fc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30fc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d5a7babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d5a7baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d5a79f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d5a44ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d5a44eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30fc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30fc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30fc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d5a44ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (6614 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a34aa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a34aa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a34aa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15d6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15d64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15d6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15d6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a34a3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a34a3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a34a218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a346d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a346d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15d6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15d64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15d64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a346d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (6615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9af4b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9af4b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9af4b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2426c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2426ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2426c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2426c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9af44dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9af44da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9af4328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9af0e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9af0e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2426c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2426c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2426c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9af0e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (6617 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10878) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055deaf42beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055deaf428e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055deaf42c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa40e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa40e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa40e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa40e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055deaf3c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055deaf3c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055deaf3a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055deaf055e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055deaf055b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa40e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa40e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa40e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055deaf055a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (6620 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634946afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634946ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634946b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff246333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff24638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff246333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff24631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563494645bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563494645a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056349462a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634942d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634942d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff24631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff24631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff24631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634942d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (6621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565541fabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565541fa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565541fac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4abf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4abf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4abf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4abf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565541f41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565541f41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565541f268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565541bd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565541bd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4abf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4abf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4abf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565541bd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (6622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c29283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c29280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c2928462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2770e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2770ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2770e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2770e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c29219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c29219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c291fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c28eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c28eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2770e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2770e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2770e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c28eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (6623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609d346feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609d346ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609d347062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3d7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3d718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3d7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3d711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609d3405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609d3405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609d33ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609d3099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609d3099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3d711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3d711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3d711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609d3099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (6624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <v
# | ...
# `---data was truncated (10240/28691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619f6e93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619f6e90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619f6e9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd34af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd34af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd34af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd34af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619f6e29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619f6e29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619f6e0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619f6abde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619f6abdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd34af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd34af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd34af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619f6abda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (6625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f07969deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f07969ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f07969e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc3da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc3daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc3da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc3da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f079633bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f079633a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0796188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0792c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0792c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc3da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc3da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc3da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0792c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (6626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d700d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d700d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d700d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e9fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e9fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e9fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e9fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d70069bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d70069a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d7004e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d6fcfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d6fcfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e9fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e9fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e9fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d6fcfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (6629 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf8efd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf8efd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf8efd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcbc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcbc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcbc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcbc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf8ef6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf8ef6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf8ef508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf8ebffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf8ebffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcbc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcbc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcbc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf8ebffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (6631 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559840025eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559840022e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055984002662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5827d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5827d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5827d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5827d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055983ffbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055983ffbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055983ffa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055983fc4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055983fc4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5827d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5827d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5827d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055983fc4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (6632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5f811beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5f8118e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5f811c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7499533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f749958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7499533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f749951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5f80b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5f80b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5f80968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5f7d45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5f7d45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f749951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f749951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f749951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5f7d45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (6634 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558126a9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558126a99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558126a9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8103249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81032a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8103249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8103231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558126a32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558126a32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558126a178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581266c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581266c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8103232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81032330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81032330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581266c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (6635 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1f5bf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1f5befe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1f5bf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f5fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f5faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f5fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f5fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1f5b88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1f5b88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1f5b6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1f581ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1f581cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f5fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f5fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f5fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1f581ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (6637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622b8d65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622b8d62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622b8d6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5310533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f531058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5310533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f531051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622b8cfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622b8cfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622b8ce08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622b898fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622b898fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f531051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f531051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f531051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622b898fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (6638 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | 
# | ...
# `---data was truncated (10240/34641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab9eca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab9eca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab9eca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa430049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa430049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa430031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab9ec3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab9ec3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab9ec208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab9e8cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab9e8cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa430032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab9e8cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (6641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f143a11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f143a0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f143a1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1439a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1439a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f14398c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f14363be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f14363bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f14363ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (6642 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d8ebf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d8ebf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d8ebfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c88e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c88ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c88e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c88e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d8eb8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d8eb8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d8eb748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d8e823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d8e823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c88e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c88e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c88e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d8e823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (6644 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a34fafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a34face85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a34fb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f810b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f810b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f810b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f810b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a34f45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a34f45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a34f2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a34bd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a34bd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f810b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f810b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f810b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a34bd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (6645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558c6f81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558c6f7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558c6f8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86ff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86ff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86ff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86ff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558c6f17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558c6f17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558c6efc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558c6babe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558c6babb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86ff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86ff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86ff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558c6baba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (6646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/83088) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055568250feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055568250ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055568251062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1835933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1835933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f183591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556824a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556824a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055568248a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555682139e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555682139b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f183591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f183591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f183591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555682139a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (6650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 =
# | ...
# `---data was truncated (10240/10936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557932521eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055793251ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055793252262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0e5d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0e5d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0e5d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0e5ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579324b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579324b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055793249c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055793214be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055793214bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0e5ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0e5cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0e5cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055793214ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (6651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055795f42ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055795f429e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055795f42d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4627533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f462758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4627533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f462751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055795f3c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055795f3c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055795f3a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055795f056e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055795f056b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f462751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f462751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f462751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055795f056a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (6656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/79861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd7f2ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd7f2fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd7f30062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fdf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fdf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fdf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fdf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd7f295bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd7f295a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd7f27a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd7ef29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd7ef29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5fdf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fdf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fdf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd7ef29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (6657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align
# | ...
# `---data was truncated (10240/18311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c07d31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c07d2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c07d3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c43f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c43f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c43f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c43f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c07cc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c07cc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c07cac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c0795be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c0795bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c43f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c43f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c43f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c0795ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (6659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0,
# | ...
# `---data was truncated (10240/28346) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559139a56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559139a53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559139a5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9711c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9711c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9711c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9711c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591399ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591399eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591399d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559139680e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559139680b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9711c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9711c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9711c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559139680a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (6662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e0dd25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e0dd22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e0dd2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79fab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79fab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79fab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79fab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e0dcbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e0dcbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e0dca08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e0d94fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e0d94fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79fab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79fab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79fab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e0d94fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (6664 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm
# | ...
# `---data was truncated (10240/35597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4a4f1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4a4f1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4a4f2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f278c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f278c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f278c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f278c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4a4eb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4a4eb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4a4e9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4a4b49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4a4b49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f278c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f278c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f278c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4a4b49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (6666 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdd241ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdd2419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdd241d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f705ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f705ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f705ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f705ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdd23b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdd23b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdd23978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdd2046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdd2046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f705ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f705ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f705ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdd2046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (6667 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# |  #0 0x0000563a19c52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a19c4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a19c5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f067dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f067dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f067dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f067dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a19be8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a19be8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a19bcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a1987ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a1987cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f067dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f067dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f067dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a1987ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (6668 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccb0008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccb0005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccb000962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f029121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02912725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f029121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0291203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccaff9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccaff9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccaff838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccafc32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccafc32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0291204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02912050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02912050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccafc32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (6670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557067594eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557067591e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055706759562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf8cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf8cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf8cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf8ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055706752abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055706752aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055706750f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570671bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570671beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf8ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf8ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf8ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570671bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (6676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e4a8c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e4a8bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e4a8c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67e5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67e5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67e5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67e5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e4a856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e4a856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e4a83b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e4a4eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e4a4eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67e5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67e5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67e5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e4a4eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (6678 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/69495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa663b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa663afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa663b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54db733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54db78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54db733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54db71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa66348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa66348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa6632d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa65fdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa65fdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54db71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54db71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54db71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa65fdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (6679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/26702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa2e767eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa2e764e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa2e76862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa2e6fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa2e6fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa2e6e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa2e391e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa2e391b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa2e391a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (6681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faf1c8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faf1c87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faf1c8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9975505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f997555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9975505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99754ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faf1c20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faf1c20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faf1c058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faf18b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faf18b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99754eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99754ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99754ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faf18b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (6682 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571a2aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571a2aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571a2af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e93a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e93aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e93a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e93a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571a2a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571a2a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571a2a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571a2719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571a2719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e93a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e93a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e93a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571a2719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (6683 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30c145eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c30c142e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c30c14662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c30c0dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c30c0dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c30c0c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c30bd6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c30bd6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c30bd6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (6684 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr %0, i64 %2)
# |   %4 =
# | ...
# `---data was truncated (10240/33471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618c2bffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618c2bfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618c2c0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7667049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76670a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7667049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7667031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618c2b95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618c2b95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618c2b7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618c2829e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618c2829b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7667032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76670330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76670330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618c2829a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (6687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de7c07beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de7c078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de7c07c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62d3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62d3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62d3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62d3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de7c011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de7c011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de7bff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de7bca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de7bca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62d3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62d3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62d3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de7bca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (6688 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556613040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055661303de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055661304162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5422849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5422849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5422831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556612fd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556612fd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556612fbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556612c6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556612c6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5422832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54228330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556612c6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (6690 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/43507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cbe5a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cbe5a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cbe5a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6c7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cbe539bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cbe539a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cbe51e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cbe1cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cbe1cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6c72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cbe1cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (6691 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/28559) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654b3bc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654b3bc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654b3bc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc88f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc88f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc88f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc88f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654b3b59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654b3b59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654b3b3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654b37ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654b37edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc88f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc88f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc88f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654b37eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (6693 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568687f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568687f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568687f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1cb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1cb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1cb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1cb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055686878ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055686878ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568687738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556868422e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556868422b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1cb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1cb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1cb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556868422a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (6695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <v
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bba3209eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bba3206e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bba320a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d9bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d9bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d9bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d9bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bba319fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bba319fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bba31848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bba2e33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bba2e33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d9bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d9bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d9bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bba2e33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (6697 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe492b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe492ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe492b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4697d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4697d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4697d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4697d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe49246bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe49246a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe4922b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe48edae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe48edab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4697d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4697d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4697d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe48edaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (6699 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567ced05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567ced02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567ced0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f31f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f31f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f31f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f31f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567cec9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567cec9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567cec808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567ce92fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567ce92fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f31f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f31f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f31f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567ce92fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (6700 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9e86deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9e86dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9e86df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f426f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f426f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f426f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f426f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9e8674bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9e8674a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9e86598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9e8308e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9e8308b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f426f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f426f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f426f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9e8308a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (6704 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a27ed47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a27ed44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a27ed4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ed1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ed1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ed1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ed1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a27ecddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a27ecdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a27ecc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a27e971e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a27e971b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ed1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ed1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ed1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a27e971a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (6707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x d
# | ...
# `---data was truncated (10240/19901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581d3f18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581d3f15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581d3f1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0aec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0aeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0aec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0aec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581d3eaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581d3eaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581d3e938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581d3b42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581d3b42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0aec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0aec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0aec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581d3b42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (6710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ca696feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ca696ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ca697062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ac41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ac4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ac41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ac403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ca6905bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ca6905a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ca68ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ca6599e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ca6599b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ac404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ac4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ac4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ca6599a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (6713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/63510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600463cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600463cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600463ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d9f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d9f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d9f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560046363bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560046363a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600463488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560045ff7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560045ff7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d9f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d9f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d9f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560045ff7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (6716 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8
# | ...
# `---data was truncated (10240/24320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ed3a9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ed3a9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ed3a9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82de649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82de6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82de649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82de631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ed3a34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ed3a34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ed3a198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ed36c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ed36c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82de632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82de6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82de6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ed36c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (6717 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e789a09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e789a06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e789a0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa776849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa776849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa776831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e78999fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e78999fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7899848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e789633e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e789633b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa776832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7768330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e789633a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (6718 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | ...
# `---data was truncated (10240/12457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dacffeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dacffbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dacfff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5040b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5040b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5040b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5040b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dacf94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dacf94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dacf798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dacc28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dacc28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5040b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5040b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5040b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dacc28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (6723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0a3753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0a3750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0a375462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c8b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c8b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c8b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c8b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0a36e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0a36e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0a36ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0a337de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0a337db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c8b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c8b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c8b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0a337da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (6724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563526b8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563526b89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563526b8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7156505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f715655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7156505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71564ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563526b22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563526b22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563526b078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635267b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635267b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71564eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71564ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71564ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635267b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (6727 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562926a05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562926a02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562926a0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7865333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f786538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7865333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f786531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292699bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056292699ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629269808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056292662fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056292662fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f786531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f786531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f786531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056292662fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (6729 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c97835aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c978357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c97835b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9782f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9782f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9782d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c977f84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c977f84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c977f84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (6730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d93954aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d939547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d93954b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bafb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bafb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bafb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bafb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9394e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9394e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9394c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d939174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d939174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bafb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bafb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bafb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d939174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (6732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9634d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9634d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9634d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35c8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d96346dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d96346da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9634528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d963101e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d963101b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35c8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d963101a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (6733 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/26764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558581003eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558581000e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055858100462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e3b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e3b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e3b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e3b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558580f99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558580f99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558580f7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558580c2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558580c2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e3b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e3b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e3b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558580c2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (6734 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee139eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee139e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee139ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eed933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eed98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eed933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eed91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee13982bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee13982a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee139678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee13616e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee13616b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1eed91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eed91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eed91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee13616a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (6735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale 
# | ...
# `---data was truncated (10240/30627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de747feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560de747ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560de748062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac0cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac0cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac0cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac0cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de7415bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560de7415a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560de73fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560de70a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560de70a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac0cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac0cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac0cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de70a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (6738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646e8534eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646e8531e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646e853562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd58f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd58f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd58f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd58f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646e84cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646e84caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646e84af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646e815ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646e815eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd58f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd58f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd58f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646e815ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (6739 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f06acaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f06ac7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f06acb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5134133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f513418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5134133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f513411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f06a60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f06a60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f06a458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f066f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f066f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f513411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f513411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f513411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f066f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (6740 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c2dde0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c2dddde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c2dde162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f531d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f531d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f531d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f531d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c2dd76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c2dd76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c2dd5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c2da0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c2da0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f531d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f531d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f531d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c2da0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (6742 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563edd95ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563edd959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563edd95d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47dfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563edd8f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563edd8f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563edd8d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563edd586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563edd586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563edd586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (6748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055814216ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558142169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055814216d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1780333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f178038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1780333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f178031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558142102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558142102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581420e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558141d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558141d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f178031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f178031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f178031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558141d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (6754 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056172cb5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056172cb59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056172cb5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfe5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfe5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfe5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfe5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056172caf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056172caf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056172cad78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056172c786e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056172c786b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfe5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfe5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfe5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056172c786a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (6755 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c2facaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c2fac7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c2facb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bc5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bc518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bc5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bc511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c2fa60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c2fa60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c2fa458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c2f6f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c2f6f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bc511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bc511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bc511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c2f6f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (6756 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %
# | ...
# `---data was truncated (10240/13690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555f2e87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555f2e84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555f2e8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4551133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f455118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4551133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f455111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555f2e1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555f2e1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555f2e028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555f2ab1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555f2ab1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f455111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f455111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f455111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555f2ab1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (6757 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4f36b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4f36b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4f36b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9533b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9533b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9533b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9533b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f364cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4f364ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4f36318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4f32e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4f32e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9533b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9533b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9533b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f32e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (6758 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561443069eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561443066e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056144306a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ca1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ca16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ca1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ca1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561442fffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561442fffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561442fe48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561442c93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561442c93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ca1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ca16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ca16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561442c93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (6759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bd5868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bd5865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bd586962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ac831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bd57febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bd57fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bd57e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bd5492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bd5492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6ac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ac8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bd5492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (6762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d55dce3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d55dce0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d55dce462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d89449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d894a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d89449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d89431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d55dc79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d55dc79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d55dc5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d55d90de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d55d90db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d89432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d894330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d894330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d55d90da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (6763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %1, <vsc
# | ...
# `---data was truncated (10240/12290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbec3e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbec3e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbec3e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c7d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c7d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c7d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c7d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbec37abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbec37aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbec35f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbec00ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbec00eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c7d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c7d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c7d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbec00ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (6767 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562ffe5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562ffe5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562ffe5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fa5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fa52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fa5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fa5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562ffdf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562ffdf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562ffdd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562ffa88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562ffa88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fa5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fa52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fa52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562ffa88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (6768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555776b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555776b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555776b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef3f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef3f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef3f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef3f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055557764dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055557764da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555776328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555772e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555772e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef3f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef3f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef3f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555772e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (6769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055757c6ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055757c6cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055757c6cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca24933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca2498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca24933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca2491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055757c664bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055757c664a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055757c6498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055757c2f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055757c2f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca2491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca2491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca2491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055757c2f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (6770 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056150aeeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056150aee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056150aeeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8f8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056150ae80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056150ae80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056150ae658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056150ab14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056150ab14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8f8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056150ab14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (6772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a59b6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a59b6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a59b6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a59b03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a59b03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a59ae88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a59797e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a59797b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ec8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a59797a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (6773 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa0ca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfa0c9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfa0ca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3db0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3db0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3db0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3db0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa0c38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfa0c38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfa0c1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfa08cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfa08ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3db0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3db0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3db0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa08cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (6774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/11938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6887b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6887b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6887b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c68874bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c68874ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6887308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6883dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6883dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6883dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (6775 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561808b50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561808b4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561808b5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f289f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f289f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f289f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f289f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561808ae6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561808ae6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561808acb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056180877ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056180877ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f289f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f289f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f289f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056180877aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (6777 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/26710) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfaa7b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfaa7b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfaa7b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbe0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbe02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbe0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbe0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfaa74dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfaa74da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfaa7328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfaa3e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfaa3e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbe0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbe02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbe02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfaa3e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (6779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a42fa4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a42fa48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a42fa4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbcc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbcc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbcc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbcc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a42f9e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a42f9e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a42f9c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a42f675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a42f675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbcc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbcc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbcc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a42f675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (6780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd718c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd718bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd718c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a08249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a082a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a08249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a08231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd71857bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd71857a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd7183c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd714ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd714ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a08232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a082330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a082330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd714eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (6782 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055997a4e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055997a4e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055997a4e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56c6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56c658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56c6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56c651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055997a47cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055997a47ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055997a4618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055997a110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055997a110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56c651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56c651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56c651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055997a110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (6787 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, a
# | ...
# `---data was truncated (10240/43486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d34253eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d34253be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d34253f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe821849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe821849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe821831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3424d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3424d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3424b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d342168e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d342168b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe821832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8218330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d342168a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (6788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# | 
# | ...
# `---data was truncated (10240/26460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f714dafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f714dace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f714db062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcdcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcdcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcdcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcdcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f714d45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f714d45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f714d2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7149d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7149d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcdcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcdcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcdcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7149d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (6790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d73273eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d73273be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d73273f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc305933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc30598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc305933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc30591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7326d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7326d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7326b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d732368e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d732368b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc30591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc30591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc30591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d732368a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (6791 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %
# | ...
# `---data was truncated (10240/29809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3b9cd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3b9cd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3b9cd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1d731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3b9c6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3b9c6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3b9c538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3b9902e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3b9902b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1d731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3b9902a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (6792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606fd75aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606fd757e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606fd75b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1861a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1861aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1861a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1861a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606fd6f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606fd6f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606fd6d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606fd384e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606fd384b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1861a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1861a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1861a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606fd384a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (6794 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610e0654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610e0651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610e065562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc70b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc70b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc70b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc70b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e05eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610e05eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610e05cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610e027ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610e027eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc70b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc70b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc70b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e027ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (6795 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.a
# | ...
# `---data was truncated (10240/38299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643f01bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643f01bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643f01be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0ac933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0ac98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0ac933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0ac91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643f0153bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643f0153a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643f01388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643efde7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643efde7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0ac91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0ac91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0ac91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643efde7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (6796 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 
# | ...
# `---data was truncated (10240/26333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589f097ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589f0979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589f097d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd16921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1692725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd16921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd169203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589f0912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589f0912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589f08f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589f05a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589f05a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd169204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1692050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1692050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589f05a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (6799 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574ec9d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574ec9cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574ec9d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01a1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01a12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01a1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01a1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574ec968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574ec968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574ec94d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574ec5fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574ec5fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01a1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01a12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01a12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574ec5fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (6801 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b11f46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b11f43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b11f4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e75649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e75649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e75631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b11edcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b11edca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b11ec18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b11b70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b11b70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e75632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b11b70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (6803 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8abd45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8abd42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8abd4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba7361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba736725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba7361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba73603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8abcdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8abcdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8abcc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8ab96fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8ab96fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba73604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba736050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba736050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8ab96fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (6804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2be809eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2be806e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2be80a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4d1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4d198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4d1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4d191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2be79fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2be79fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2be7848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2be433e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2be433b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4d191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4d191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4d191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2be433a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (6805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056456ae38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056456ae35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056456ae3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056456adcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056456adcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056456adb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056456aa62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056456aa62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16f2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056456aa62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (6811 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64)
# | ...
# `---data was truncated (10240/34765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f5455eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8f5452e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8f545662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bad049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bad0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bad049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bad031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f53ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8f53eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8f53d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8f507fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8f507fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bad032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bad0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bad0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f507fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (6812 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558828da3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558828da0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558828da462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44e3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44e36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44e3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44e3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558828d39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558828d39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558828d1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588289cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588289cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44e3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44e36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44e36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588289cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (6816 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056437601feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056437601ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056437602062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb11c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb11ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb11c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb11c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564375fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564375fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564375f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564375c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564375c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb11c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb11c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb11c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564375c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (6817 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e733a33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e733a30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e733a3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6284f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6284f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6284f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6284f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7339c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7339c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7339ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e73365de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e73365db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6284f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6284f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6284f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e73365da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (6818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/25287) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559268a42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559268a3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559268a4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4dcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4dcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4dcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4dcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592689d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592689d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592689bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055926866ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055926866cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4dcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4dcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4dcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055926866ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (6819 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f13aeb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f13aeb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f13aeba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c54a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c54aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c54a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c54a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f13ae4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f13ae4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f13ae348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f13aae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f13aae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c54a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c54a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c54a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f13aae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (6823 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055763880feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055763880ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055763881062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69a4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69a495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69a4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69a48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576387a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576387a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055763878a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557638439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557638439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69a48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69a48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69a48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557638439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (6827 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c8c4e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c8c4e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c8c4e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f673781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67378725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f673781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6737803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c8c479bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c8c479a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c8c45e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c8c10de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c8c10db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6737804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67378050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67378050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c8c10da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (6828 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6a50f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6a50f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6a50f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe622b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe622b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe622b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe622b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6a5089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6a5089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6a506e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6a4d1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6a4d1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe622b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe622b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe622b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6a4d1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (6830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eee6fcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eee6fc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eee6fcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f916e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f916e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f916e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f916e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eee6f62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eee6f62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eee6f478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eee6bf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eee6bf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f916e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f916e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f916e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eee6bf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (6831 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623bc713eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623bc710e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623bc71462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623bc6a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623bc6a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623bc68e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623bc33de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623bc33db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623bc33da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (6833 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c72d06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c72d03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c72d0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c1a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c1a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c1a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c1a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c72c9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c72c9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c72c818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c72930e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c72930b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c1a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c1a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c1a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c72930a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (6835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cc4da5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cc4da2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cc4da662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd195105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd195105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1950ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cc4d3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cc4d3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cc4d208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cc49cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cc49cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1950eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1950ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1950ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cc49cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (6836 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb84507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb84504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb8450862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63e5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb8449dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb8449da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb844828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb84131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb84131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63e52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb84131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (6838 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e572724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e572721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e57272562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8600d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8600d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8600d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8600d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5726babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5726baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e57269f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e57234ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e57234eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8600d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8600d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8600d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e57234ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (6839 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585253bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585253bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585253be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc846449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc846449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc846431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558525353bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558525353a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585253388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558524fe7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558524fe7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc846432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8464330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558524fe7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (6841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e66d1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e66d17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e66d1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3ce649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ce6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3ce649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3ce631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e66cb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e66cb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e66c958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e66944e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e66944b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3ce632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3ce6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3ce6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e66944a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (6842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566dde1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566dde18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566dde1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa47d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa47d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa47d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566dddb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566dddb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566ddd968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566dda45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566dda45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa47d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa47d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa47d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566dda45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (6843 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat>
# | ...
# `---data was truncated (10240/53686) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635d31c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635d31c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635d31c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ab9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ab9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ab9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ab9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635d315dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635d315da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635d31428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635d2df1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635d2df1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ab9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ab9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ab9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635d2df1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (6844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558351655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558351652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055835165662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faab5d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faab5d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faab5d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faab5ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583515ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583515eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583515d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055835127fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055835127fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faab5ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faab5cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faab5cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055835127fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (6845 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 
# | ...
# `---data was truncated (10240/69943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a23f4feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a23f4fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a23f4ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd324533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd32458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd324533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd32451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a23f494bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a23f494a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a23f4798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a23f128e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a23f128b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd32451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd32451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd32451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a23f128a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (6850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600e7848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600e7845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600e784962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb81849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb81849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb81831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600e77debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600e77dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600e77c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600e7472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600e7472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb81832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600e7472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (6852 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6599eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6599e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6599ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ab1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ab12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ab1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ab1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b659982bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b659982a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6599678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b659616e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b659616b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ab1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ab12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ab12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b659616a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (6853 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b03660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b0365de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b0366162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd19841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1984725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd19841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd198403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b035f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b035f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b035db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b0328ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b0328ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd198404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1984050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1984050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b0328aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (6854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f5a3f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f5a3f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f5a3f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc45c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc45ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc45c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc45c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f5a38dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f5a38da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f5a3728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f5a021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f5a021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc45c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc45c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc45c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f5a021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (6855 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056468d2cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056468d2cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056468d2ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5cbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5cbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5cbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5cbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056468d263bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056468d263a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056468d2488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056468cef7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056468cef7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5cbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5cbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5cbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056468cef7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (6858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595334eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595334ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595334ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d5ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d5ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d5ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d5ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559533484bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559533484a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595334698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559533118e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559533118b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d5ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d5ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d5ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559533118a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (6860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.add
# | ...
# `---data was truncated (10240/14453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9dd3b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9dd3afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9dd3b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f101ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f101ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f101ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f101ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9dd348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9dd348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9dd32d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9dcfdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9dcfdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f101ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f101ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f101ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9dcfdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (6861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/13617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555667641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055566763ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055566764262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b7b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b7b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b7b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b7b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556675d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556675d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556675bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055566726be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055566726bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b7b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b7b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b7b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055566726ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (6862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a64dfedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a64dfeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a64dfee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9709933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f970998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9709933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f970991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a64df83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a64df83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a64df688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a64dc17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a64dc17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f970991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f970991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f970991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a64dc17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (6865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3ea1d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3ea1d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3ea1d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9ecb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3ea16bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3ea16ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3ea1508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3e9dffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3e9dffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3e9dffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (6866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563824bf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563824bf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563824bf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e64933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e6498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e64933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e6491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563824b8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563824b8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563824b728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563824821e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563824821b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e6491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e6491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e6491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563824821a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (6867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vect
# | ...
# `---data was truncated (10240/24229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba85861eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba8585ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba8586262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ba4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ba458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ba4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ba451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba857f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba857f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba857dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba8548be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba8548bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ba451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ba451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ba451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba8548ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (6868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 
# | ...
# `---data was truncated (10240/14824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556ca1a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556ca19ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556ca1a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb02c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb02ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb02c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb02c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556ca137bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556ca137a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556ca11c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556c9dcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556c9dcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb02c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb02c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb02c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556c9dcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (6869 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4d31e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4d31e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4d31e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f364ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f364ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4d3179bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4d3179a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4d315e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4d2e0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4d2e0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f364ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4d2e0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (6870 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c540a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c540a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c540a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f5f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f5f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f5f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f5f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c5403dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c5403da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c540228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c53cd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c53cd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f5f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f5f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f5f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c53cd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (6871 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync
# | ...
# `---data was truncated (10240/10618) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb27c8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb27c8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb27c8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f933fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f933fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f933fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f933fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb27c24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb27c24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb27c098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb278b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb278b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f933fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f933fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f933fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb278b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (6873 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e082314eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e082311e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e08231562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17e0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17e00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17e0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17e0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0822aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0822aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e08228f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e081f3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e081f3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17e0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17e00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17e00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e081f3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (6874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4329e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4329dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4329e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74f9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74f915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74f9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74f90ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f432977bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f432977a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f43295c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f43260be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f43260bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74f90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74f90ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74f90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f43260ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (6875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d4a46beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d4a468e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d4a46c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ed4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ed4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ed4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ed4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d4a401bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d4a401a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d4a3e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d4a095e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d4a095b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ed4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ed4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ed4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d4a095a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (6876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f51ef95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f51ef92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f51ef9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc926649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc926649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc926631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f51ef2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f51ef2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f51ef108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f51ebbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f51ebbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc926632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f51ebbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (6881 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613e33d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613e33cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613e33d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c91733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c9178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c91733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c9171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613e3367bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613e3367a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613e334c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613e2ffbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613e2ffbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c9171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c9171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c9171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613e2ffba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (6882 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d31b4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d31b4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d31b4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94e1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94e18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94e1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94e1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d31ae3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d31ae3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d31ac88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d31777e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d31777b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94e1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94e18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94e18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d31777a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (6884 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edaa4daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edaa4d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edaa4db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31c7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31c758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31c7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31c751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edaa470bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edaa470a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edaa4558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edaa104e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edaa104b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31c751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31c751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31c751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edaa104a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (6885 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c6445eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c6445be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c6445f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ae1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ae1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ae1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ae1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c643f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c643f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c643d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c64088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c64088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ae1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ae1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ae1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c64088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (6887 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556274715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556274712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055627471662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f907ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f907ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f907ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f907ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562746abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562746aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562746908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055627433fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055627433fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f907ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f907ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f907ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055627433fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (6889 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ba7f66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ba7f63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ba7f6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6c3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6c398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6c3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6c391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ba7efcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ba7efca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ba7ee18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ba7b90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ba7b90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6c391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6c391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6c391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ba7b90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (6890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/34581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055990edfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055990edfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055990edff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1149533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f114958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1149533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f114951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055990ed94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055990ed94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055990ed798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055990ea28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055990ea28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f114951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f114951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f114951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055990ea28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (6891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d39d802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d39d7ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d39d80362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feed3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feed38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feed3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feed3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d39d798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d39d798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d39d77d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d39d42ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d39d42cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feed3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feed38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feed38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d39d42ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (6892 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba839dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba839dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba839e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafed733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafed78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafed733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafed71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba83975bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba83975a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba8395a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba83609e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba83609b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafed71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafed71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafed71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba83609a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (6893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643b08f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643b08f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643b08f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa370333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa37038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa370333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa37031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643b088ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643b088ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643b08738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643b0522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643b0522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa37031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa37031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa37031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643b0522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (6894 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a8491ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a84919e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a8491d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f863f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f863f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f863f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f863f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a848b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a848b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a848978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a84546e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a84546b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f863f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f863f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f863f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a84546a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (6895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd0fd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cd0fcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cd0fd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c43a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c43aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c43a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c43a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd0f67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cd0f67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cd0f4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cd0bfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cd0bfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c43a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c43a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c43a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd0bfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (6896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/22375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fb9193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564fb9190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564fb919462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f276e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f276e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f276e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f276e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fb9129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564fb9129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564fb910e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564fb8dbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564fb8dbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f276e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f276e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f276e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fb8dbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (6897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa1c6a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa1c6a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa1c6a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa1c639bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa1c639a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa1c61e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa1c2cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa1c2cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03a9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa1c2cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (6898 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccda8e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccda8e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccda8e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9881933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f988198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9881933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f988191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccda87bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccda87ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccda8608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccda50fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccda50fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f988191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f988191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f988191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccda50fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (6899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16
# | ...
# `---data was truncated (10240/33616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560799476eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560799473e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056079947762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a57133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a5718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a57133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a5711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056079940cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056079940ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607993f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607990a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607990a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a5711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a5711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a5711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607990a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (6901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <
# | ...
# `---data was truncated (10240/14421) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562108dd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562108dd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562108dd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f525b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f525b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f525b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f525b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562108d6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562108d6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562108d518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562108a00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562108a00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f525b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f525b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f525b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562108a00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (6902 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618cf3eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618cf3ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618cf3ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcc0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcc0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcc0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcc0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618cf384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618cf384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618cf3698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618cf018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618cf018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcc0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcc0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcc0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618cf018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (6903 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ba8bc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ba8bbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ba8bc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b57e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b57ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b57e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b57e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ba8b57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ba8b57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ba8b3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ba87ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ba87ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b57e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b57e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b57e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ba87eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (6905 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055948fddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055948fdd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055948fddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e3df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e3df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e3df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e3df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055948fd72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055948fd72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055948fd578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055948fa06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055948fa06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e3df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e3df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e3df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055948fa06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (6907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("ris
# | ...
# `---data was truncated (10240/26965) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71c63feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a71c63ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a71c64062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bc4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bc478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bc4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bc471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71c5d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a71c5d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a71c5ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a71c269e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a71c269b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bc471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bc471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bc471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a71c269a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (6909 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i6
# | ...
# `---data was truncated (10240/35605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629a8fdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629a8fd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629a8fdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa80dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa80dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa80dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa80dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629a8f71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629a8f71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629a8f568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629a8c05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629a8c05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa80dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa80dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa80dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629a8c05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (6913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b35e268eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b35e265e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b35e26962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f625c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f625c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f625c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f625c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b35e1febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b35e1fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b35e1e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b35de92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b35de92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f625c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f625c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f625c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b35de92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (6914 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3435aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3435a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3435ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6c591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f343540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f343540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3435258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3431d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3431d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6c591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3431d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (6915 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d0cccbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d0ccc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d0cccc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70d3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70d3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70d3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70d3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d0cc61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d0cc61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d0cc468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d0c8f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d0c8f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70d3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70d3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70d3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d0c8f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (6920 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625d2e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625d2e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625d2e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6585b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6585b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6585b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6585b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d2dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625d2dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625d2da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625d2a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625d2a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6585b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6585b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6585b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d2a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (6923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c15544eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c15541e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c1554562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5afdd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5afdd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5afdd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5afdced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c154dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c154daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c154bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c1516ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c1516eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5afdceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5afdcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5afdcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c1516ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (6924 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590136aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590136a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590136ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4309449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4309449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4309431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559013642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559013642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590136278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590132d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590132d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4309432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590132d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (6930 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8537f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8537eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8537f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e82649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e82649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e82631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b853787bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b853787a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b85376c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b85341be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b85341bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e82632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e826330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b85341ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (6931 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dea6a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dea6a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dea6a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc53d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc53d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc53d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc53d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dea63ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dea63ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dea6238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dea2d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dea2d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc53d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc53d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc53d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dea2d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (6934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596455c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596455c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596455c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f058b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f058b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f058b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f058b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055964555bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055964555ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596455408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596451efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596451efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f058b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f058b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f058b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596451efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (6937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vsca
# | ...
# `---data was truncated (10240/11229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb4d90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb4d8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb4d9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f714c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f714c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f714c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f714c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb4d26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb4d26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb4d0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb49bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb49bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f714c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f714c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f714c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb49baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (6938 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569ac54beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569ac548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569ac54c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f065ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f065ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f065ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f065ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569ac4e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569ac4e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569ac4c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569ac175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569ac175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f065ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f065ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f065ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569ac175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (6942 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e382d95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e382d92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e382d9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15d0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15d0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15d0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15d0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e382d2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e382d2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e382d108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3829bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3829bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15d0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15d0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15d0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3829bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (6943 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d9687eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d9687be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d9687f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadf5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadf558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadf5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadf551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d96814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d96814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d967f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d964a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d964a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadf551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadf551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadf551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d964a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (6947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600c50f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600c50f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600c50f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1c2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1c2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1c2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1c2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600c508ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600c508ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600c50738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600c4d22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600c4d22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1c2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1c2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1c2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600c4d22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (6948 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640f4c69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640f4c66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640f4c6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdc1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdc158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdc1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdc151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640f4bffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640f4bffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640f4be48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640f4893e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640f4893b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdc151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdc151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdc151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640f4893a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (6950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555c911deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555c911ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555c911e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc380d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc380d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc380d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc380ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555c90b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555c90b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555c90988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555c8d47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555c8d47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc380ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc380cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc380cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555c8d47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (6952 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a40648eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a40648be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a40648f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7f5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7f52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7f5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7f5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a406424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a406424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4064098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4060b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4060b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7f5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7f52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7f52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4060b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (6953 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x 
# | ...
# `---data was truncated (10240/30682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c853caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c853c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c853cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd286249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd286249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd286231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c85360bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c85360a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c853458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c84ff4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c84ff4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd286232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c84ff4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (6954 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> p
# | ...
# `---data was truncated (10240/24606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de25c70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de25c6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de25c7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8e8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8e82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8e8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8e8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de25c06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de25c06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de25beb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de2589ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de2589ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8e8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8e82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8e82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de2589aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (6956 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64
# | ...
# `---data was truncated (10240/32186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617fb676eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617fb673e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617fb67762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ec3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ec338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ec3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ec331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617fb60cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617fb60ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617fb5f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617fb2a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617fb2a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ec331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ec331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ec331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617fb2a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (6960 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3
# | ...
# `---data was truncated (10240/14330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ec88a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ec889de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ec88a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc339f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc339f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc339f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc339f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ec8836bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ec8836a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ec881b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ec84cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ec84cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc339f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc339f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc339f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ec84caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (6961 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d778384eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d778381e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d77838562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79a5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d77831abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d77831aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7782ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d777faee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d777faeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79a5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d777faea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (6962 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a64369eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a64366e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a6436a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb748705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb74875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb748705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7486ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a642ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a642ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a642e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a63f93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a63f93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7486eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7486ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7486ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a63f93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (6963 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, alig
# | ...
# `---data was truncated (10240/26754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b15747eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b15744e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b1574862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98226725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9822603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b156ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b156dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b156c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b15371e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b15371b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9822604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98226050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98226050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b15371a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (6964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nof
# | ...
# `---data was truncated (10240/11966) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056412ea96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056412ea93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056412ea9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5844133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f584418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5844133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f584411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056412ea2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056412ea2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056412ea118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056412e6c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056412e6c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f584411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f584411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f584411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056412e6c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (6966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i
# | ...
# `---data was truncated (10240/41934) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056305d6d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056305d6d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056305d6d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f680d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f680d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056305d669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056305d669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056305d64e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056305d2fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056305d2fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f680d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056305d2fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (6967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0,
# | ...
# `---data was truncated (10240/69839) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626e24f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626e24f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626e24f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96e6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96e638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96e6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96e631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626e248cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626e248ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626e24718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626e2120e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626e2120b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96e631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96e631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96e631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626e2120a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (6968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1a1088eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1a1085e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1a108962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d0d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d0d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d0d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d0d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1a101ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1a101ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1a10038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1a0cb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1a0cb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d0d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d0d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d0d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1a0cb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (6970 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b477f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b477f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b477f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feddb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feddb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feddb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feddb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b4778cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b4778ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b477718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b47420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b47420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feddb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feddb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feddb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b47420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (6971 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1833eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1833e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1833eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f167fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f167fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f167fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f167fc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c183380bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c183380a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1833658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c183014e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c183014b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f167fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f167fc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f167fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c183014a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (6972 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b3140eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b3140be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b3140f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9145933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f914598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9145933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f914591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b313a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b313a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b313898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b31038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b31038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f914591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f914591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f914591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b31038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (6974 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 
# | ...
# `---data was truncated (10240/10944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602738f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602738f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602738f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43ddf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43ddf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43ddf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43ddf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056027388ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056027388ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602738738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560273522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560273522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43ddf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43ddf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43ddf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560273522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (6976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1aa19ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1aa199e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1aa19d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9bde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1aa132bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1aa132a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1aa1178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1a9dc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1a9dc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9bde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1a9dc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (6977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636b61e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636b61e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636b61ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5a6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5a66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5a6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5a6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636b617fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636b617fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636b61648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636b5e13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636b5e13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5a6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5a66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5a66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636b5e13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (6978 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e715c15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e715c12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e715c1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8323533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f832358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8323533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f832351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e715babbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e715baba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e715b908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e71583fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e71583fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f832351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f832351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f832351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e71583fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (6981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noin
# | ...
# `---data was truncated (10240/25042) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c10b1ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c10b1e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c10b1ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8e151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c10b181bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c10b181a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c10b1668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c10ae15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c10ae15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8e151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c10ae15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (6983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a08ea5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a08ea5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a08ea5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e2f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e2f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e2f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e2f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a08e9f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a08e9f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a08e9d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a08e688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a08e688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e2f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e2f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e2f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a08e688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (6987 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vlse16_v_
# | ...
# `---data was truncated (10240/35087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578d240aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578d2407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578d240b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57e4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57e4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57e4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57e4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578d23a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578d23a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578d23858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578d2034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578d2034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57e4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57e4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57e4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578d2034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (6989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c9c1cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c9c1c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c9c1cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff8921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff892725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff8921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff89203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c9c161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c9c161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c9c1468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c9bdf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c9bdf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff89204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff892050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff892050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c9bdf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (6992 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558acf0c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558acf0bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558acf0c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa93c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa93c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa93c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa93c803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558acf056bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558acf056a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558acf03b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aceceae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aceceab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa93c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa93c8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa93c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aceceaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (6993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = loa
# | ...
# `---data was truncated (10240/33443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3fcdb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3fcdb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3fcdb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47d4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47d498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47d4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47d491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3fcd4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3fcd4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3fcd338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3fc9e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3fc9e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47d491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47d491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47d491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3fc9e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (6995 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563caacb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563caacb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563caacb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc059649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0596a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc059649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc059631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563caac49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563caac49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563caac2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563caa8dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563caa8ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc059632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0596330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0596330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563caa8dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (6996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/17403) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dfebc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dfebc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dfebc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f743b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f743b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f743b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f743b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dfeb5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dfeb5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dfeb418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dfe7f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dfe7f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f743b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f743b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f743b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dfe7f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (7001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea6cd8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea6cd87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea6cd8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda09c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda09ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda09c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda09c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea6cd20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea6cd20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea6cd058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea6c9b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea6c9b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda09c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda09c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda09c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea6c9b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (7002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf4f172eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf4f16fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf4f17362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2669d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2669d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2669d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2669ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf4f108bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf4f108a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf4f0ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf4ed9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf4ed9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2669ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2669cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2669cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf4ed9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (7003 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055657c2baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055657c2b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055657c2bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25b6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25b6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25b6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25b6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055657c250bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055657c250a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055657c2358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055657bee4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055657bee4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25b6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25b6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25b6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055657bee4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (7004 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598c2b40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598c2b3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598c2b4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f371441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37144725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f371441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3714403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598c2ad6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598c2ad6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598c2abb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598c276ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598c276ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3714404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37144050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37144050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598c276aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (7006 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdd5debeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdd5de8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdd5dec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdd5d81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdd5d81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdd5d668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdd5a15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdd5a15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdd5a15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (7007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x 
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056372825eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056372825be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056372825f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccf5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637281f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637281f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637281d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563727e88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563727e88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccf52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563727e88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (7008 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align
# | ...
# `---data was truncated (10240/39416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a001bd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a001bd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a001bda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f576e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f576e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f576e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f576e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a001b6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a001b6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a001b548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a001803e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a001803b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f576e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f576e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f576e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a001803a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (7009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde
# | ...
# `---data was truncated (10240/31748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564617404eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564617401e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056461740562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe591649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5916a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe591649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe591631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056461739abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056461739aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056461737f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056461702ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056461702eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe591632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5916330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5916330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056461702ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (7011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563601cc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563601cc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563601cc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb52e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb52e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563601c5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563601c5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563601c3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636018eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636018eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb52e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636018eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (7016 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale 
# | ...
# `---data was truncated (10240/56179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0d9513eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0d9510e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0d951462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9b1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9b1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9b1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9b1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0d94a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0d94a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0d948e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0d913de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0d913db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9b1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9b1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9b1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0d913da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (7018 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"Sma
# | ...
# `---data was truncated (10240/10293) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffb96b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffb96b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffb96b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68e7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68e7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68e7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68e7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffb9649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffb9649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffb962e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffb92dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffb92ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68e7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68e7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68e7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffb92dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (7020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vs
# | ...
# `---data was truncated (10240/10886) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dca7d30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dca7d2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dca7d3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe844533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe84458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe844533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe84451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dca7cc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dca7cc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dca7cab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca795ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca795ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe84451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe84451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe84451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca795aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (7022 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5
# | ...
# `---data was truncated (10240/15508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d6f4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595d6f4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595d6f4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89acf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89acf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89acf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89aceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d6ee4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595d6ee4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595d6ec98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595d6b78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595d6b78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89aceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89aceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89aceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d6b78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (7024 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f3f18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8f3f15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8f3f1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49da505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49da55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49da505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49da4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f3eaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8f3eaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8f3e938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8f3b42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8f3b42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49da4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49da4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49da4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f3b42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (7025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056450ec96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056450ec93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056450ec9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc11ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc11cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc11ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc11ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056450ec2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056450ec2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056450ec118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056450e8c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056450e8c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc11ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc11ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc11ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056450e8c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (7026 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f27d39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f27d36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f27d3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7df2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7df2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7df2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7df2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f27ccfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f27ccfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f27cb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f27963e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f27963b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7df2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7df2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7df2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f27963a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (7028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a4b5a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a4b59ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a4b5a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd99461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9946725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd99461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd994603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4b537bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a4b537a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a4b51c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a4b1cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a4b1cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd994604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9946050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9946050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a4b1cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (7029 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison
# | ...
# `---data was truncated (10240/18569) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601ab4c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601ab4c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601ab4c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0836a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0836aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0836a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0836a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601ab45ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601ab45ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601ab4438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601ab0f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601ab0f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0836a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0836a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0836a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601ab0f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (7030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bf
# | ...
# `---data was truncated (10240/13040) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dae0270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dae026de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dae027162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20bd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dae0206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dae0206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dae01eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dadfe9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dadfe9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dadfe9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (7031 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d2aa4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d2aa4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d2aa5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6574b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6574b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6574b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6574b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d2a9e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d2a9e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d2a9ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d2a679e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d2a679b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6574b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6574b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6574b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d2a679a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (7033 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575e44edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575e44eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575e44ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb63f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb63f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb63f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb63f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575e4483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575e4483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575e44688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575e4117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575e4117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb63f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb63f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb63f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575e4117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (7034 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target
# | ...
# `---data was truncated (10240/23439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb35c45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb35c42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb35c4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cffa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb35bdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb35bdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb35bc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb3586fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb3586fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cffa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb3586fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (7035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650c4f62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650c4f5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650c4f6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15a9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15a9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15a9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15a9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650c4ef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650c4ef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650c4edd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650c4b8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650c4b8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15a9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15a9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15a9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650c4b8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (7037 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651b33f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651b33efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651b33f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7efdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7efdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7efdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7efdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651b3388bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651b3388a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651b336d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651b301ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651b301cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7efdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7efdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7efdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651b301ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (7038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %ba
# | ...
# `---data was truncated (10240/24100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a0da8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a0da87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a0da8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb605d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb605d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb605d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb605d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a0da20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a0da20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a0da058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a0d6b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a0d6b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb605d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb605d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb605d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a0d6b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (7039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/13625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645e349eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645e349be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645e349f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cc441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cc44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cc441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cc4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645e3434bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645e3434a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645e34198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645e30c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645e30c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cc4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cc44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cc44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645e30c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (7040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %m
# | ...
# `---data was truncated (10240/41661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055935ec0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055935ec0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055935ec0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc64b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc64b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc64b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc64b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055935eba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055935eba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055935eb898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055935e838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055935e838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc64b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc64b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc64b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055935e838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (7043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637a4457eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637a4454e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637a445862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f556d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f556d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f556d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f556d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637a43edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637a43eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637a43d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637a4081e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637a4081b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f556d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f556d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f556d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637a4081a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (7044 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>
# | ...
# `---data was truncated (10240/22898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565558b49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565558b46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565558b4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f676ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f676caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f676ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f676ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565558adfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565558adfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565558ac48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565558773e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565558773b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f676ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f676ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f676ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565558773a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (7045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577883ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577883dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577883de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae4fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae4fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae4fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae4fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557788373bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557788373a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577883588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557788007e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557788007b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae4fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae4fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae4fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557788007a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (7046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f30ac4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f30ac47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f30ac4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aeeb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aeeb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aeeb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aeeaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f30abe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f30abe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f30abc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f30a874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f30a874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5aeeaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aeeaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aeeaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f30a874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (7050 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd0ab77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd0ab74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd0ab7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8475449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8475449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8475431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd0ab0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd0ab0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd0aaf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd0a7a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd0a7a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8475432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84754330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd0a7a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (7051 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe7928beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe79288e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe7928c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff095533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff09558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff095533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff09551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe79221bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe79221a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe792068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe78eb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe78eb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff09551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff09551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff09551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe78eb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (7056 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b1b65beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b1b658e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b1b65c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2da4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2da478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2da4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2da471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b1b5f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b1b5f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b1b5d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b1b285e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b1b285b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2da471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2da471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2da471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b1b285a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (7057 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614c3e0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614c3e09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614c3e0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31f8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614c3da2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614c3da2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614c3d878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614c3a36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614c3a36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31f8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614c3a36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (7058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a80fa47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a80fa44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a80fa4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51c2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51c2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51c2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51c2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a80f9ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a80f9dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a80f9c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a80f671e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a80f671b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51c2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51c2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51c2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a80f671a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (7059 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad548aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad548a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad548ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a8b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a8b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a8b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a8b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad54842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad54842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad548278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad544d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad544d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a8b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a8b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a8b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad544d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (7060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/39578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580afd88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580afd85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580afd8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe32ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe32ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe32ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe32ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580afd1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580afd1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580afd038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580af9b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580af9b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe32ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe32ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe32ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580af9b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (7061 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, pt
# | ...
# `---data was truncated (10240/32402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5cf8e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5cf8dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5cf8e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8782d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8782d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8782d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8782ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5cf878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5cf878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5cf85d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5cf50ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5cf50cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8782ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8782cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8782cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5cf50ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (7062 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac64ecaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac64ec7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac64ecb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7e6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7e6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7e6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7e6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac64e60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac64e60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac64e458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac64af4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac64af4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7e6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7e6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7e6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac64af4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (7063 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055948d7bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055948d7bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055948d7be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dec705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dec75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dec705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dec6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055948d753bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055948d753a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055948d7388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055948d3e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055948d3e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dec6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dec6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dec6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055948d3e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (7067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_l
# | ...
# `---data was truncated (10240/13585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f51387eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f51384e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f5138862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbf7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbf7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbf7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbf7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f5131dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f5131da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f513028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f50fb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f50fb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbf7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbf7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbf7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f50fb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (7069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr
# | ...
# `---data was truncated (10240/27541) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a737c78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a737c75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a737c7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aeb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aeb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aeb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aeb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a737c0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a737c0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a737bf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7378a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7378a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aeb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aeb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aeb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7378a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (7071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559577737eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559577734e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055957773862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4009b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4009b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4009b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4009b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595776cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595776cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595776b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559577361e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559577361b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4009b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4009b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4009b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559577361a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (7074 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f0f817eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f0f814e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f0f81862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36d9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36d9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36d9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36d9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f0f7adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f0f7ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f0f7928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f0f441e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f0f441b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36d9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36d9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36d9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f0f441a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (7075 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f32798eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f32795e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f3279962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44726725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4472603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f3272ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f3272ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f327138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f323c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f323c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4472604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44726050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44726050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f323c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (7076 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/22367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd3408feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd3408ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd3409062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe236333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe236333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe23631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd34025bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd34025a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd3400a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd33cb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd33cb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe23631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe23631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe23631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd33cb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (7077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |  
# | ...
# `---data was truncated (10240/28350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056519184eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056519184be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056519184f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb431133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb43118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb431133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb43111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651917e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651917e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651917c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565191478e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565191478b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb43111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb43111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb43111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565191478a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (7078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621e41fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621e41fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621e41fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc56b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc56b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc56b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc56b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621e4193bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621e4193a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621e41788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621e3e27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621e3e27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc56b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc56b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc56b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621e3e27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (7081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/26520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e563c98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e563c95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e563c9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94b351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e563c2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e563c2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e563c138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5638c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5638c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94b351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5638c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (7083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4f55faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4f55f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4f55fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f640b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f640b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f640b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f640b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4f5590bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4f5590a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4f55758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4f5224e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4f5224b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f640b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f640b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f640b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4f5224a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (7084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f734722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f73471fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f73472362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa24f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa24f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa24f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa24f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7346b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7346b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f73469d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f73434ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f73434cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa24f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa24f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa24f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f73434ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (7085 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577c33c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577c33c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577c33c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff28b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff28b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff28b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff28b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577c335dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577c335da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577c33428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577c2ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577c2ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff28b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff28b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff28b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577c2ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (7087 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# | 
# | ...
# `---data was truncated (10240/23255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ed360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0ed35de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0ed36162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe4221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe422725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe4221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe42203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ed2f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0ed2f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0ed2db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0ecf8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0ecf8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe42204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe422050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe422050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ecf8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (7090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d00e3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d00e39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d00e3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8507c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8507ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8507c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8507c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d00dd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d00dd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d00db78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d00a66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d00a66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8507c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8507c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8507c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d00a66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (7091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5aadefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5aadece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5aadf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdddec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdddeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdddec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdddec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5aad85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5aad85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5aad6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5aaa19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5aaa19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdddec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdddec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdddec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5aaa19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (7093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609a0e0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609a0e0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609a0e1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46b551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609a0da5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609a0da5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609a0d8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609a0a39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609a0a39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46b551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609a0a39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (7094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfe96b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfe96b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfe96b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8493333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f849338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8493333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f849331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfe9649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfe9649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfe962e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfe92dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfe92ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f849331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f849331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f849331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfe92dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (7096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055816c7a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055816c7a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055816c7a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff197f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff197f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff197f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff197f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055816c73ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055816c73ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055816c7238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055816c3d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055816c3d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff197f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff197f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff197f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055816c3d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (7097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a931aa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a931a9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a931aa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e98e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e98e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e98e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e98e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a931a38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a931a38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a931a1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9316cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9316ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e98e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e98e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e98e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9316cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (7099 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606616d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606616cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606616d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda83c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda83ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda83c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda83c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560661668bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560661668a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056066164d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606612fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606612fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda83c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda83c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda83c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606612fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (7102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d33157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d33154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d3315862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18bba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18bbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18bba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18bba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d330edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d330eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d330d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d32d81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d32d81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18bba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18bba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18bba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d32d81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (7106 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv
# | ...
# `---data was truncated (10240/47720) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645e74c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645e74c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645e74ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f000b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f000b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f000b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f000b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645e745fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645e745fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645e74448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645e70f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645e70f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f000b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f000b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f000b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645e70f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (7107 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2eaa8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2eaa89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2eaa8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06baf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06baf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06baf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06baf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2eaa22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2eaa22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2eaa078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2ea6b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2ea6b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06baf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06baf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06baf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2ea6b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (7108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651bcb87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651bcb84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651bcb8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4117449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4117449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4117431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651bcb1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651bcb1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651bcb028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651bc7b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651bc7b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4117432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651bc7b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (7109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bf6edfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bf6edce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bf6ee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f4df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f4df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f4df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f4df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf6e75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bf6e75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bf6e5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bf6b09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bf6b09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f4df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f4df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f4df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf6b09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (7110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/34633) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbad9dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbad9d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbad9dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc41cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc41cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc41cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc41cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbad972bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbad972a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbad9578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbad606e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbad606b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc41cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc41cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc41cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbad606a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (7111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae6ad6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae6ad6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae6ad6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2175449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2175449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2175431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae6ad03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae6ad03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae6ace88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae6a997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae6a997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2175432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21754330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae6a997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (7112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca
# | ...
# `---data was truncated (10240/12137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc76a19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc76a16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc76a1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2691333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f269138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2691333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f269131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc769afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc769afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc769948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc76643e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc76643b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f269131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f269131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f269131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc76643a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (7113 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb64bc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb64bc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb64bc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb460a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb460aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb460a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb460a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb64b59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb64b59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb64b3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb647ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb647edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb460a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb460a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb460a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb647eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (7114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d92e744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d92e741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d92e74562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e55533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e5558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e55533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e5551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d92e6dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d92e6daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d92e6bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d92e36ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d92e36eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e5551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e5551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e5551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d92e36ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (7116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa4b1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaa4b1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaa4b1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ca2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ca2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ca2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ca2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa4ab4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaa4ab4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaa4a998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaa4748e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaa4748b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ca2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ca2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ca2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa4748a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (7117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.
# | ...
# `---data was truncated (10240/17879) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9c55d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9c55cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9c55d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4adf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4adf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4adf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4adf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9c5567bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9c5567a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9c554c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9c51fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9c51fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4adf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4adf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4adf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9c51fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (7120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bab95c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bab95c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bab95c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f982fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f982fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f982fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f982fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bab9559bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bab9559a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bab953e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bab91ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bab91edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f982fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f982fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f982fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bab91eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (7123 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7efa53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7efa50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7efa5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfd121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfd12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfd121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfd1203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7ef9e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7ef9e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7ef9ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7ef67de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7ef67db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfd1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfd12050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfd12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7ef67da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (7125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564842846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564842843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056484284762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f893e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f893e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f893e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f893e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648427dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648427dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648427c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564842470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564842470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f893e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f893e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f893e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564842470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (7127 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb96beeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb96bebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb96bef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3155b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3155b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3155b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3155b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb96b84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb96b84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb96b698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb96818e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb96818b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3155b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3155b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3155b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb96818a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (7129 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558892bb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558892bb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558892bb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54d5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54d515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54d5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54d50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558892b4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558892b4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558892b2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588927dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588927deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54d50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54d50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54d50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588927dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (7130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605bfa95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605bfa92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605bfa9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbc6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbc6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbc6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbc6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605bfa2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605bfa2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605bfa108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605bf6bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605bf6bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbc6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbc6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbc6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605bf6bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (7131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c8f2ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c8f2dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c8f2de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b9c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b9c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b9c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b9c203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c8f273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c8f273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c8f2588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c8ef07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c8ef07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b9c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b9c2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b9c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c8ef07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (7132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1f03a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1f03a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1f03a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a9ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a9ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a9ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a9ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1f033bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1f033ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1f03208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1effcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1effcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a9ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a9ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a9ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1effcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (7133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fd2fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fd2fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fd2fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c66ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fd2f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fd2f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fd2f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fd2be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fd2be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c66ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fd2be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (7136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, 
# | ...
# `---data was truncated (10240/24959) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ae6548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ae6545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ae654962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b00b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b00b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b00b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b00b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ae64debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ae64dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ae64c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ae6172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ae6172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b00b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b00b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b00b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ae6172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (7138 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b8d6aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b8d6a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b8d6ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09e5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09e515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09e5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09e50ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b8d640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b8d640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b8d6258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b8d2d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b8d2d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09e50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09e50ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09e50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b8d2d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (7140 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b33b7aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b33b7a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b33b7ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bc6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bc68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bc6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bc6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b33b740bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b33b740a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b33b7258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b33b3d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b33b3d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bc6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bc68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bc68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b33b3d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (7141 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056465ab75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056465ab72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056465ab7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc3e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc3e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc3e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc3e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056465ab0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056465ab0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056465aaf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056465a79fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056465a79fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc3e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc3e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc3e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056465a79fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (7143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055702a3b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055702a3b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055702a3b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23bad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23bad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23bad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23bad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055702a34ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055702a34ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055702a3338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557029fe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557029fe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23bad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23bad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23bad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557029fe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (7144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650f111feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650f111ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650f112062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e8f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650f10b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650f10b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650f109a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650f0d49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650f0d49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650f0d49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (7145 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563329798eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563329795e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056332979962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e2a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e2a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e2a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e2a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056332972ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056332972ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633297138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633293c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633293c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e2a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e2a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e2a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633293c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (7146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d55737aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d557377e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d55737b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb63849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb638a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb63849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb63831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d557310bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d557310a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5572f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d556fa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d556fa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb63832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb638330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb638330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d556fa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (7148 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626a53d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626a53d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626a53d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76b4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76b4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76b4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76b4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626a5369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626a5369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626a534e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626a4ffde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626a4ffdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76b4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76b4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76b4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626a4ffda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (7150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f040f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f040f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f040f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f04089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f04089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f0406e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f03d1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f03d1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f03d1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (7151 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcf9c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcf9c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcf9c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f7ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f7eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f7ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f7ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcf9be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcf9be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcf9bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcf9874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcf9874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f7ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f7ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f7ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcf9874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (7153 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562797576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562797573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056279757762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9933649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99336a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9933649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9933631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056279750cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056279750ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627974f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627971a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627971a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9933632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99336330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99336330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627971a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (7155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d14b797eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d14b794e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d14b79862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97efc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97efca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97efc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97efc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d14b72dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d14b72da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d14b7128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d14b3c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d14b3c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97efc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97efc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97efc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d14b3c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (7158 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# |  #0 0x00005644f00faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644f00f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644f00fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38afc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38afca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38afc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38afc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644f0090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644f0090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644f00758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644efd24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644efd24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38afc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38afc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38afc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644efd24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (7159 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555eed1b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555eed1aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555eed1b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb455905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb45595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb455905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4558ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555eed147bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555eed147a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555eed12c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555eecddbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555eecddbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4558eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4558ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4558ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555eecddba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (7160 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1
# | ...
# `---data was truncated (10240/26772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605013e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605013dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605013e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a5cd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a5cd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a5cd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a5cced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560501376bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560501376a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056050135b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056050100ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056050100ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a5cceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a5ccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a5ccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056050100aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (7161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = loa
# | ...
# `---data was truncated (10240/18917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560eca12beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560eca128e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560eca12c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54dc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560eca0c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560eca0c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560eca0a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ec9d55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ec9d55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54dc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ec9d55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (7162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a3c63aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a3c637e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a3c63b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a28d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a28d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a28d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a28d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a3c5d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a3c5d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a3c5b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a3c264e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a3c264b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a28d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a28d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a28d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a3c264a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (7163 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, flo
# | ...
# `---data was truncated (10240/34773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d158cf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d158cf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d158cfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0b5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0b5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0b5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0b5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d158c8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d158c8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d158c748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d158923e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d158923b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0b5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0b5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0b5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d158923a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (7164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cedbd5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cedbd57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cedbd5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7ba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7ba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7ba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7ba431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cedbcf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cedbcf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cedbcd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cedb984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cedb984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7ba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7ba4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7ba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cedb984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (7165 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6a7460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6a745de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6a746162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc151a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc151aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc151a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc151a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6a73f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6a73f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6a73db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6a708ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6a708ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc151a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc151a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc151a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6a708aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (7167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale
# | ...
# `---data was truncated (10240/14485) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f45c845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f45c842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f45c84662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b88d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b88d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b88d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b88d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f45c7dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f45c7dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f45c7c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f45c46fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f45c46fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b88d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b88d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b88d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f45c46fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (7170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e5a58eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e5a58be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e5a58f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bd7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bd7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bd7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bd7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e5a524bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e5a524a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e5a5098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e5a1b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e5a1b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bd7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bd7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bd7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e5a1b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (7171 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v
# | ...
# `---data was truncated (10240/18520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d6db8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d6db89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d6db8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa7281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa728725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa7281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa72803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d6db22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d6db22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d6db078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d6d7b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d6d7b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa72804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa728050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa728050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d6d7b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (7174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load p
# | ...
# `---data was truncated (10240/28353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598457aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598457a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598457ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9bdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9bdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9bdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9bdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559845742bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559845742a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598457278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598453d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598453d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9bdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9bdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9bdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598453d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (7175 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define d
# | ...
# `---data was truncated (10240/25350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8432aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8432a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8432ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc1a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc1a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc1a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc1a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a843240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a843240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8432258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a842ed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a842ed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc1a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc1a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc1a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a842ed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (7176 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e526aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e526abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e526af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8708e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8708e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8708e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8708e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e52644bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e52644a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e526298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e522d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e522d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8708e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8708e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8708e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e522d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (7177 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee30980eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee3097de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3098162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5615533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f561558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5615533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f561551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee30916bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee30916a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee308fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee305aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee305aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f561551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f561551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f561551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee305aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (7178 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @ll
# | ...
# `---data was truncated (10240/47728) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cafe45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cafe42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cafe4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aecb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cafddbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cafddba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cafdc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cafa6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cafa6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2aecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cafa6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (7179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557abc406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557abc403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557abc40762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7853705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f785375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7853705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78536ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557abc39cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557abc39ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557abc3818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557abc030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557abc030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78536eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78536ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78536ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557abc030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (7180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/41094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056240580aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562405807e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056240580b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08f4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08f435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08f4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08f42ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624057a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624057a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624057858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562405434e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562405434b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08f42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08f42ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08f42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562405434a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (7181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616a069deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616a069ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616a069e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82d501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82d50725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82d501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82d5003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616a0633bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616a0633a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616a06188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616a02c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616a02c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82d5004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82d50050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82d50050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616a02c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (7182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x
# | ...
# `---data was truncated (10240/15375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb35a7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb35a7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb35a7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1c5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1c5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1c5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1c5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb35a13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb35a13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb359f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb356a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb356a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1c5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1c5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1c5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb356a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (7183 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7f8c03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7f8c00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7f8c0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9463b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9463b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9463b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9463b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7f8b99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7f8b99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7f8b7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7f882de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7f882db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9463b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9463b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9463b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7f882da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (7184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642f6b5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f6b5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f6b6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee1bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee1bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee1bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee1bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f6af5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f6af5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f6ada8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f6789e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f6789b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee1bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee1bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee1bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f6789a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (7185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |  
# | ...
# `---data was truncated (10240/19083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bfa70ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bfa709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bfa70d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83c7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bfa6a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bfa6a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bfa6878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bfa336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bfa336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bfa336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (7187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613d076aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613d0767e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613d076b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e4d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e4d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e4d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e4d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613d0700bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613d0700a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613d06e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613d0394e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613d0394b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e4d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e4d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e4d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613d0394a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (7188 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7f415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b7f412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b7f41662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff13b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff13b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff13b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff13b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b7f3abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b7f3aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b7f3908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b7f03fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b7f03fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff13b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff13b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff13b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b7f03fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (7190 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e261adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e261aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e261ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56a8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56a8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56a8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56a8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e26143bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e26143a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e261288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e25dd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e25dd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56a8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56a8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56a8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e25dd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (7192 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x flo
# | ...
# `---data was truncated (10240/29327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b264681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b26467ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b26468262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa58d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa58d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa58d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa58d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b264617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b264617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2645fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2642abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2642abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa58d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa58d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa58d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2642aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (7193 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201293beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562012938e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056201293c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73c5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73c5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73c5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73c5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620128d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620128d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620128b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562012565e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562012565b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73c5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73c5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73c5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562012565a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (7194 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581a2b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581a2b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581a2b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f085f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f085f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f085f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f085f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581a2ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581a2ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581a2ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581a2768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581a2768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f085f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f085f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f085f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581a2768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (7195 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056292fb74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056292fb71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056292fb7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8534533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f853458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8534533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f853451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292fb0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056292fb0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056292faef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056292f79ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056292f79eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f853451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f853451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f853451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056292f79ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (7197 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, p
# | ...
# `---data was truncated (10240/33435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fcabf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fcabf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fcabfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5f0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5f02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5f0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5f0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fcab8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fcab8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fcab748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fca823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fca823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5f0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5f02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5f02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fca823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (7198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b0772aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b07727e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b0772b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b076c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b076c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b076a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b07354e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b07354b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fd2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b07354a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (7200 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563df43aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563df43a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563df43ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f613c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f613c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f613c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f613c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563df4342bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563df4342a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563df43278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563df3fd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563df3fd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f613c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f613c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f613c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563df3fd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (7201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645bb201eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645bb1fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645bb20262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7817049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7817049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7817031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645bb197bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645bb197a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645bb17c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645bae2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645bae2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7817032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78170330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645bae2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (7202 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564490cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564490cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564490ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51b4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51b4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51b4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51b4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556449063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556449063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564490488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556448cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556448cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51b4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51b4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51b4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556448cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (7205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vsc
# | ...
# `---data was truncated (10240/65701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2345a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2345a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2345a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa143449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1434a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa143449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa143431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f23453cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f23453ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2345218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2341d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2341d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa143432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1434330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1434330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2341d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (7206 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i6
# | ...
# `---data was truncated (10240/18619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f56c8f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f56c8f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f56c8f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f56c88ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f56c88ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f56c8738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f56c522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f56c522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f56c522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (7209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562892a53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562892a50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562892a5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628929e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628929e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628929ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056289267de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056289267db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff1bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056289267da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (7210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a03e4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a03e49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a03e4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc040649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0406a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc040649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc040631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a03de2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a03de2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a03dc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a03a76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a03a76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc040632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0406330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0406330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a03a76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (7211 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb410faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb410f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb410fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cb9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cb9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cb9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cb9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb41090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb41090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb410758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb40d24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb40d24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cb9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cb9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cb9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb40d24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (7212 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef70a3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef70a3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef70a3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f479b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f479b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f479b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f479b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef709d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef709d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef709b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef70668e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef70668b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f479b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f479b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f479b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef70668a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (7213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | ...
# `---data was truncated (10240/78234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6692bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6692b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6692bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b669251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b669251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6692368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b668ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b668ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b668ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (7215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc5b76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bc5b73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bc5b7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f806e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f806e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f806e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f806e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc5b0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bc5b0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bc5af18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bc57a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bc57a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f806e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f806e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f806e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc57a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (7216 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fee1d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fee1d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fee1d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe39133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe3918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe39133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe3911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fee16abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fee16aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fee14f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557feddfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557feddfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe3911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe3911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe3911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557feddfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (7218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# | ...
# `---data was truncated (10240/30866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055953070eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055953070be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055953070f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7084e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7084ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7084e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7084e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595306a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595306a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595306898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559530338e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559530338b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7084e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7084e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7084e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559530338a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (7219 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b08a288eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b08a285e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b08a28962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f715ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f715eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f715ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f715ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b08a21ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b08a21ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b08a2038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b089eb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b089eb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f715ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f715ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f715ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b089eb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (7220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564165e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564165e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564165e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb313649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb313649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb313631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564165dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564165dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564165da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564165a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564165a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb313632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3136330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564165a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (7223 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056199ca9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056199ca9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056199ca9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe85981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8598725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe85981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe859803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056199ca33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056199ca33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056199ca188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056199c6c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056199c6c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe859804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8598050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8598050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056199c6c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (7224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f01913aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f019137e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f01913b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb69333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb6938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb69333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb6931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0190d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0190d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0190b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f018d64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f018d64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb6931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb6931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb6931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f018d64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (7225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0fccbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0fccbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0fccbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe945f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe945f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe945f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe945f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0fcc54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0fcc54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0fcc398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0fc8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0fc8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe945f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe945f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe945f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0fc8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (7227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe5fb09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe5fb06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe5fb0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2248e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2248ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2248e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2248e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe5fa9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe5fa9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe5fa848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe5f733e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe5f733b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2248e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2248e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2248e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe5f733a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (7228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/33764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b50254eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b50251e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b5025562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac9791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b501eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b501eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b501cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b4fe7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b4fe7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac9791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b4fe7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (7229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556427280eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055642727de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055642728162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccfb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccfb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccfb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccfb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556427216bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556427216a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564271fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556426eaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556426eaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccfb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccfb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccfb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556426eaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (7232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056148b5c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056148b5bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056148b5c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37ec049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37ec0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37ec049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37ec031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056148b558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056148b558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056148b53d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056148b1ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056148b1ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37ec032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37ec0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37ec0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056148b1eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (7237 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a0d0a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a0d0a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a0d0a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7c781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7c78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7c781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7c7803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a0d03ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a0d03ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a0d0238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a0ccd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a0ccd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7c7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7c78050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7c78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a0ccd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (7238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c0e15feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c0e15ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c0e16062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1e2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1e2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1e2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1e2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c0e0f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c0e0f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c0e0da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c0dd89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c0dd89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1e2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1e2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1e2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c0dd89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (7240 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2
# | ...
# `---data was truncated (10240/32570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b82acf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b82acf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b82acf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7be9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7be9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7be9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7be9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b82ac8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b82ac8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b82ac738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b82a922e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b82a922b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7be9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7be9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7be9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b82a922a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (7241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610e61e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610e61e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610e61e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62fda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62fdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62fda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62fda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e617cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610e617ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610e61618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610e5e10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610e5e10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62fda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62fda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62fda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e5e10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (7243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | de
# | ...
# `---data was truncated (10240/12091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed3717aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed37177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed3717b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaaf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaaf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaaf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaaf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed37110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed37110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed370f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed36da4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed36da4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaaf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaaf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaaf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed36da4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (7246 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee3187eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee3187be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3187f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb64133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb6418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb64133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb6411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee31814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee31814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee317f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee314a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee314a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb6411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb6411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb6411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee314a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (7248 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569a6270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569a626de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569a627162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f953a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f953a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f953a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f953a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569a6206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569a6206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569a61eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569a5e9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569a5e9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f953a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f953a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f953a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569a5e9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (7249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561cdc82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561cdc7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561cdc8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8667333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f866738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8667333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f866731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561cdc18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561cdc18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561cdbfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561cd8ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561cd8acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f866731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f866731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f866731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561cd8aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (7250 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/24982) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577e5ac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577e5abde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577e5ac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dedb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dedb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dedb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dedb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577e5a56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577e5a56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577e5a3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577e56eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577e56eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dedb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dedb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dedb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577e56eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (7251 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6db2f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6db2f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6db2f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f2381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f238725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f2381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f23803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6db28bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6db28ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6db2708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6daf1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6daf1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f23804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f238050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f238050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6daf1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (7255 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4e118deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4e118ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4e118e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee6e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee6e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee6e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee6e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4e1123bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4e1123a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4e11088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4e0db7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4e0db7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee6e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee6e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee6e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4e0db7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (7257 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e27ed8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e27ed8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e27ed8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c50449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c50449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c50431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e27ed23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e27ed23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e27ed088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e27e9b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e27e9b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c50432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e27e9b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (7259 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589565e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589565e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589565e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b78649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b786a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b78649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b78631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055895657bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055895657ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589565608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055895620fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055895620fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b78632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b786330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b786330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055895620fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (7262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, alig
# | ...
# `---data was truncated (10240/32578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1478a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1478a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1478aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ca7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ca718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ca7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ca711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e14783fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e14783fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1478248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1474d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1474d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ca711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ca711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ca711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1474d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (7263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llv
# | ...
# `---data was truncated (10240/20513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db53ef1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db53eeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db53ef262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15df71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db53e87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db53e87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db53e6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db53b1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db53b1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15df71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db53b1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (7264 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb3897deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb3897ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb3897e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff954733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff95478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff954733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff95471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb38913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb38913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb388f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb385a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb385a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff95471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff95471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff95471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb385a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (7265 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dc123aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dc1237e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dc123b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe880733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe88078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe880733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe88071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dc11d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dc11d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dc11b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dc0e64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dc0e64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe88071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe88071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe88071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dc0e64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (7267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef038c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef038c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef038c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ec1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ec10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ec1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ec1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef0385ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef0385ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef038438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef034f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef034f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ec1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ec10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ec10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef034f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (7269 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d14e96ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d14e969e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d14e96d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b4eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b4eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b4eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b4eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d14e902bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d14e902a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d14e8e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d14e596e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d14e596b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b4eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b4eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b4eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d14e596a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (7270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/18873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdbde3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdbde38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdbde3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5b4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5b418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5b4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5b411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdbddd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdbddd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdbddb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdbda65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdbda65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5b411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5b411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5b411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdbda65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (7276 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac92215eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac92212e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac9221662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30a3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30a375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30a3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30a36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac921abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac921aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac921908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac91e3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac91e3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30a36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30a36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30a36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac91e3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (7277 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056055614feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056055614ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056055615062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb876133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb87618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb876133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb87611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605560e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605560e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605560ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560555d79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560555d79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb87611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb87611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb87611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560555d79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (7278 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596cf5e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596cf5e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596cf5e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce59733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce5978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce59733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce5971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596cf57abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596cf57aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596cf55f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596cf20ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596cf20eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce5971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce5971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce5971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596cf20ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (7279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c84871eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c84871be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c84871f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cc2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cc22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cc2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cc2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8486b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8486b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8486998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c848348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c848348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cc2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cc22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cc22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c848348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (7280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1,
# | ...
# `---data was truncated (10240/28354) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055573c2d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055573c2cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055573c2d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0449333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f044938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0449333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f044931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055573c268bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055573c268a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055573c24d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055573befce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055573befcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f044931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f044931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f044931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055573befca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (7281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1bed79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1bed76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1bed7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe41bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe41bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe41bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe41bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1bed0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1bed0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1becf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1be9a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1be9a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe41bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe41bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe41bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1be9a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (7282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c21c776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c21c773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c21c77762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8812d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8812d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8812d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8812d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c21c70cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c21c70ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c21c6f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c21c3a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c21c3a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8812d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8812d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8812d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c21c3a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (7283 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557da03ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557da03dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557da03de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f044dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f044dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f044dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f044dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557da0373bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557da0373a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557da03588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557da0007e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557da0007b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f044dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f044dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f044dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557da0007a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (7284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.
# | ...
# `---data was truncated (10240/28162) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564603a5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564603a5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564603a5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b90ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646039f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646039f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646039d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564603688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564603688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03b90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b90ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564603688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (7286 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbb0dd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbb0dd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbb0dd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffad6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffad658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffad6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffad651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbb0d6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbb0d6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbb0d538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbb0a02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbb0a02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffad651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffad651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffad651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbb0a02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (7291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c2874eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c2874be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c2874f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f034e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f034e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f034e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f034e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c286e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c286e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c286c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c28378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c28378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f034e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f034e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f034e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c28378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (7295 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631c3b43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631c3b40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631c3b4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24f221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24f22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24f221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24f2203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631c3ad9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631c3ad9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631c3abe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631c376de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631c376db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24f2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24f22050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24f22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631c376da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (7296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a77b4b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a77b4ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a77b4b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4d1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4d10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4d1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4d1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a77b446bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a77b446a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a77b42b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a77b0dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a77b0dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4d1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4d10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4d10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a77b0daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (7297 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055616eee3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055616eee0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055616eee462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9978849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9978849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9978831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055616ee79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055616ee79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055616ee5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055616eb0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055616eb0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9978832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99788330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055616eb0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (7298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d74662eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d7465fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d7466362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c7d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c7d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c7d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c7d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d745f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d745f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d745dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d7428ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d7428cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c7d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c7d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c7d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d7428ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (7299 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9e8cadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9e8caae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9e8cae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe16ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe16ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe16ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe16ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9e8c43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9e8c43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9e8c288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9e88d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9e88d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe16ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe16ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe16ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9e88d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (7300 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570fc5fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570fc5fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570fc5fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35afb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35afb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35afb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35afb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570fc593bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570fc593a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570fc5788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570fc227e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570fc227b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35afb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35afb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35afb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570fc227a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (7302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ac98bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ac98bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ac98be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f46849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f46849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f46831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ac9853bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ac9853a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ac98388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ac94e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ac94e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f46832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f468330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ac94e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (7304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0b2b90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0b2b8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0b2b9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0daad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0daad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0daad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0daad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0b2b26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0b2b26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0b2b0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0b27bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0b27bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0daad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0daad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0daad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0b27baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (7305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c42f28ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c42f289e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c42f28d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f159cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f159cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f159cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f159cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c42f222bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c42f222a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c42f2078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c42eeb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c42eeb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f159cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f159cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f159cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c42eeb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (7307 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0e409aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0e4097e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0e409b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a6c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a6c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a6c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a6c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0e4030bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0e4030a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0e40158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0e3cc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0e3cc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a6c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a6c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a6c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0e3cc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (7309 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bba72f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bba72f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bba72f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa994c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa994c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa994c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa994c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bba728cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bba728ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bba72718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bba6f20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bba6f20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa994c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa994c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa994c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bba6f20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (7312 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x
# | ...
# `---data was truncated (10240/29267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b96654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b96651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b9665562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b5c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b5c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b5c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b5c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b965eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b965eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b965cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b9627ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b9627eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b5c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b5c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b5c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b9627ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (7314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ff7a2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ff7a2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ff7a2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe99d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe99d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe99d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe99d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ff79c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ff79c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ff79a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ff7658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ff7658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe99d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe99d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe99d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ff7658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (7315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556345774eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556345771e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055634577562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d37449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d374a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d37449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d37431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055634570abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055634570aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563456ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055634539ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055634539eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d37432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d374330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d374330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055634539ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (7319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c39a005eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c39a002e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c39a00662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7929733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f792978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7929733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f792971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c399f9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c399f9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c399f808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c399c2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c399c2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f792971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f792971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f792971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c399c2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (7323 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a2c4bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a2c4b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a2c4bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f3e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f3e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f3e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f3e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a2c451bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a2c451a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a2c4368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a2c0e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a2c0e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f3e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f3e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f3e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a2c0e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (7324 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = c
# | ...
# `---data was truncated (10240/41433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629af94aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629af947e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629af94b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fbf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fbf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fbf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fbf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629af8e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629af8e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629af8c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629af574e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629af574b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fbf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fbf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fbf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629af574a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (7325 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612fef52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612fef4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612fef5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb7761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb776725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb7761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb77603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612feee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612feee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612feecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612feb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612feb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb77604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb776050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb776050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612feb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (7327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4223c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4223c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4223c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1bce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1bcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1bce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1bce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f42235ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f42235ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4223438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f421ff2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f421ff2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1bce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1bce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1bce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f421ff2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (7328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e317338eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e317335e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e31733962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd7f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd7f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd7f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd7f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3172cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3172cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3172b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e316f62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e316f62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd7f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd7f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd7f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e316f62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (7330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f83d23aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f83d237e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f83d23b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1652449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1652449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1652431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f83d1d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f83d1d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f83d1b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f83ce64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f83ce64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1652432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16524330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f83ce64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (7332 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 
# | ...
# `---data was truncated (10240/39226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0065f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0065f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0065f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0022333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f002238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0022333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f002231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b00658cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b00658ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0065718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b006220e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b006220b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f002231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f002231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f002231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b006220a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (7333 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f75d2c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f75d2c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f75d2c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb65ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb65ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb65ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb65ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f75d25cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f75d25ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f75d2418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f75cef0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f75cef0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb65ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb65ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb65ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f75cef0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (7335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056103d5aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056103d5a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056103d5ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efca7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efca798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efca7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efca791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056103d542bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056103d542a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056103d5278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056103d1d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056103d1d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efca791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efca791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efca791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056103d1d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (7338 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6b3871eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6b386ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6b387262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3056849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30568a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3056849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3056831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6b3807bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6b3807a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6b37ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6b349be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6b349bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3056832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30568330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30568330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6b349ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (7339 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565483d28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565483d25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565483d2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b1bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b1bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b1bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b1beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565483cbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565483cbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565483ca38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565483952e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565483952b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b1beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b1beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b1beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565483952a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (7340 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddba97aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddba977e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddba97b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc200933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc20098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc200933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc20091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddba910bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddba910a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddba8f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddba5a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddba5a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc20091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc20091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc20091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddba5a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (7341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a895293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a895290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a89529462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32f9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a895229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a895229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a89520e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a894ebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a894ebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32f96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a894ebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (7342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fd6f72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fd6f6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fd6f7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f837281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83728725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f837281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8372803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fd6f08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fd6f08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fd6eed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fd6b9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fd6b9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8372804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83728050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83728050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fd6b9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (7343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604604adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604604aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604604ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ef4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ef4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ef4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ef4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560460443bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560460443a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604604288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604600d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604600d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ef4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ef4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ef4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604600d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (7344 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, 
# | ...
# `---data was truncated (10240/30635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d243a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d2439ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d243a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc67649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc67649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc67631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d24337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d24337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d2431c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d23fcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d23fcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc67632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d23fcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (7345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d009fd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d009fd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d009fd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41dc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41dc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41dc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41dc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d009f6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d009f6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d009f528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d009c01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d009c01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41dc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41dc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41dc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d009c01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (7348 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe9cb03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe9cb00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe9cb0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa28a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa28a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa28a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa28a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe9ca99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe9ca99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe9ca7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe9c72de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe9c72db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa28a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa28a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa28a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe9c72da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (7349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7ed724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7ed721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7ed72562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e14a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e14aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e14a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e14a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7ed6babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7ed6baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7ed69f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7ed34ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7ed34eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e14a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e14a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e14a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7ed34ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (7350 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractva
# | ...
# `---data was truncated (10240/22708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da95350eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da9534de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da9535162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f745e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f745e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f745e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f745e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da952e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da952e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da952cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da94f7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da94f7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f745e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f745e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f745e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da94f7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (7351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555938f5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555938f57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555938f5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555938ef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555938ef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555938ed58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555938b84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555938b84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555938b84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (7352 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dcf212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dcf20fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dcf21362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e9c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e9c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e9c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e9c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dcf1a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dcf1a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dcf18d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dcee3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dcee3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e9c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e9c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e9c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dcee3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (7354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fdbb44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fdbb41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fdbb4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e3f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e3f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e3f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e3f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fdbadabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fdbadaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fdbabf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fdb76ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fdb76eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e3f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e3f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e3f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fdb76ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (7355 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a39629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a39626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a3962a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff89101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8910725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff89101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff891003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a395bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a395bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a395a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a39253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a39253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff891004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8910050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8910050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a39253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (7356 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b18da35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b18da32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b18da3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73ae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73ae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73ae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73ae71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b18d9cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b18d9cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b18d9b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b18d65fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b18d65fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73ae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73ae71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73ae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b18d65fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (7358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632ff0f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632ff0ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632ff0f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0673733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f067378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0673733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f067371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632ff086bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632ff086a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632ff06b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632fed1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632fed1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f067371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f067371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f067371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632fed1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (7359 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.a
# | ...
# `---data was truncated (10240/33190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee61e14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee61e11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee61e1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee61daabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee61daaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee61d8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee61a3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee61a3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57f091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee61a3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (7361 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback 
# | ...
# `---data was truncated (10240/15245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559661811eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055966180ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055966181262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f933bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f933bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f933bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f933bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596617a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596617a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055966178c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055966143be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055966143bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f933bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f933bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f933bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055966143ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (7362 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec08e5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec08e5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec08e6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec08df5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec08df5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec08dda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec08a89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec08a89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec08a89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (7365 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f9fabbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f9fab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f9fabc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dac533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dac58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dac533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dac51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f9fa51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f9fa51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f9fa368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f9f6e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f9f6e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dac51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dac51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dac51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f9f6e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (7366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define 
# | ...
# `---data was truncated (10240/18595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9385a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9385a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9385a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb61001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6100725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb61001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb610003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d93853cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d93853ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9385218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9381d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9381d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb610004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6100050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6100050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9381d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (7367 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056386643beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563866438e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056386643c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dcae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dcaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dcae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dcae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638663d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638663d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638663b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563866065e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563866065b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5dcae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dcae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dcae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563866065a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (7368 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557697689eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557697686e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055769768a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc163f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc163f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc163f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc163f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055769761fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055769761fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576976048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576972b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576972b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc163f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc163f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc163f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576972b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (7369 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4767f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4767f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4767f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41e0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41e08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41e0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41e0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f47678cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f47678ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4767718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f476420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f476420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41e0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41e08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41e08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f476420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (7370 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x 
# | ...
# `---data was truncated (10240/12463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7bd6aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7bd6a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7bd6ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2026c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2026ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2026c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2026c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7bd642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7bd642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7bd6278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7bd2d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7bd2d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2026c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2026c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2026c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7bd2d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (7371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628138f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628138eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628138f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bd0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bd0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bd0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bd0a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562813887bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562813887a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056281386c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056281351be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056281351bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bd0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bd0a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bd0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056281351ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (7373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567e17b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567e17b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567e17b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f264d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f264d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f264d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f264d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567e174abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567e174aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567e172f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567e13dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567e13deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f264d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f264d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f264d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567e13dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (7375 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056538b098eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056538b095e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056538b09962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9850449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9850449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9850431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056538b02ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056538b02ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056538b0138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056538acc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056538acc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9850432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056538acc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (7376 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdabb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdabafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdabb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe129933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe12998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe129933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe12991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdab48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdab48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdab2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bda7dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bda7dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe12991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe12991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe12991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bda7dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (7377 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vundefined_bf16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vundefined_bf16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vundefined_bf16m1() #0 {
# | entry:
# |   ret <vscale x 4 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vundefined_bf16m2() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vundefined_bf16m4() #0 {
# | entry:
# |   ret <vscale x 16 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vundefined_bf16m8() #0 {
# | entry:
# |   ret <vscale x 32 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vundefined_bf16mf4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vundefined_bf16mf4x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vundefined_bf16mf4x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vundefined_bf16mf4x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vundefined_bf16mf4x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vundefined_bf16mf4x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vundefined_bf16mf4x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vundefined_bf16mf2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vundefined_bf16mf2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vundefined_bf16mf2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vundefined_bf16mf2x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vundefined_bf16mf2x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vundefined_bf16mf2x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vundefined_bf16mf2x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vundefined_bf16m1x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vundefined_bf16m1x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vundefined_bf16m1x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vundefined_bf16m1x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vundefined_bf16m1x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vundefined_bf16m1x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vundefined_bf16m1x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vundefined_bf16m2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vundefined_bf16m2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vundefined_bf16m2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vundefined_bf16m4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd71cf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd71cf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd71cf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f329ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f329eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f329ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f329ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd71c8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd71c8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd71c6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd7191ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd7191eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f329ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f329ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f329ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd7191ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (7379 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a07135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a07132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a0713662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a070cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a070cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a070b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a06d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a06d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a06d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (7380 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fce82e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fce82dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fce82e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f722d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f722d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f722d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f722d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fce8278bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fce8278a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fce825d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fce7f0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fce7f0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f722d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f722d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f722d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fce7f0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (7381 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dbcc99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dbcc96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dbcc9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dbcc2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dbcc2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dbcc148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dbc8c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dbc8c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dbc8c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (7382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b522aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b522a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b522ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c27449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c274a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c27449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c27431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b52240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b52240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b522258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b51ed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b51ed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c27432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c274330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c274330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b51ed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (7383 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582d9c15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582d9c12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582d9c1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb55d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb55d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb55d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb55d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582d9babbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582d9baba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582d9b908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582d983fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582d983fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb55d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb55d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb55d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582d983fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (7384 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627568aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627568a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627568ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66e7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66e738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66e7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66e731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562756842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562756842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627568278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627564d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627564d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66e731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66e731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66e731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627564d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (7385 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad07fb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad07fafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad07fb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95d2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95d298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95d2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95d291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad07f48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad07f48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad07f2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad07bdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad07bdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95d291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95d291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95d291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad07bdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (7386 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/26512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562af11efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562af11ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562af11f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f23533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f2358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f23533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f2351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562af1185bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562af1185a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562af116a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562af0e19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562af0e19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f2351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f2351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f2351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562af0e19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (7388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f2dd43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f2dd40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f2dd4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3924333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f392438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3924333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f392431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f2dcd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f2dcd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f2dcbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f2d96de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f2d96db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f392431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f392431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f392431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f2d96da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (7391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbabd70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbabd6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbabd7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dc321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dc32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dc321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dc3203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbabd06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbabd06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbabceb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbab99ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbab99ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dc3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dc32050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dc32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbab99aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (7394 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056278c889eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056278c886e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056278c88a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25cc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25cc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25cc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25cc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056278c81fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056278c81fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056278c8048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056278c4b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056278c4b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25cc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25cc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25cc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056278c4b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (7395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578774eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578774ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578774ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f927d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f927d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557877484bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557877484a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578774698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557877118e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557877118b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f927d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557877118a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (7396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564747b84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564747b81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564747b8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb76049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb76049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb76031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564747b1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564747b1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564747aff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647477aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647477aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb76032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb760330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647477aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (7400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 nounde
# | ...
# `---data was truncated (10240/26592) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b86b84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b86b81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b86b8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62e1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62e138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62e1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62e131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b86b1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b86b1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b86aff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b867aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b867aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62e131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62e131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62e131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b867aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (7401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055603f79ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055603f799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055603f79d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff31d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603f732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603f732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055603f7178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055603f3c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055603f3c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055603f3c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (7402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %o
# | ...
# `---data was truncated (10240/65883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558219601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582195fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055821960262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ded649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ded6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ded649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ded631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558219597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558219597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055821957c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055821922be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055821922bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ded632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ded6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ded6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055821922ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (7403 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c40e6f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c40e6f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c40e6fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2873c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2873ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2873c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2873c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c40e68fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c40e68fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c40e6748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c40e323e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c40e323b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2873c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2873c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2873c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c40e323a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (7404 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d555321eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d55531ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d55532262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57ae449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57ae4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57ae449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57ae431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5552b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5552b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d55529c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d554f4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d554f4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57ae432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57ae4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57ae4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d554f4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (7405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f1690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590f168de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590f169162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9334f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9334f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9334f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9334f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f1626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590f1626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590f160b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590f12bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590f12bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9334f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9334f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9334f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f12baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (7406 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale 
# | ...
# `---data was truncated (10240/39900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a0f229eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a0f226e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a0f22a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e3aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a0f1bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a0f1bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a0f1a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a0ee53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a0ee53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50e3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e3aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a0ee53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (7407 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056226d9fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056226d9fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056226d9fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0978a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0978aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0978a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0978a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056226d993bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056226d993a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056226d9788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056226d627e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056226d627b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0978a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0978a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0978a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056226d627a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (7410 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2aa63eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2aa63be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2aa63f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95a7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95a70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95a7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95a7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2aa5d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2aa5d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2aa5b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2aa268e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2aa268b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95a7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95a70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95a70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2aa268a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (7411 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b14da42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b14da3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b14da4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a4de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a4de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a4de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a4de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b14d9d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b14d9d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b14d9bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b14d66ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b14d66cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a4de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a4de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a4de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b14d66ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (7412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571c9ac4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571c9ac1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571c9ac562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c9a5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571c9a5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571c9a3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571c96eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571c96eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c96eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/cx-complex-range-real.c (7413 of 27910)
******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %mul.rl = fmul float %a.real, %0
# |   %mul.il = fmul float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.il, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul.rl = fmul float %.real, %0
# |   %mul.il = fmul float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %mul.rl, ptr %.realp1, align 4
# |   store float %mul.il, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca float, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul.rl = fmul float %0, %b.real
# |   %mul.ir = fmul float %0, %b.imag
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.ir, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = fdiv float %a.real, %0
# |   %2 = fdiv float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %1, ptr %retval.realp, align 4
# |   store float %2, ptr %retval.imagp, align 4
# |   %3 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %2 = fdiv float %.real, %0
# |   %3 = fdiv float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %2, ptr %.realp1, align 4
# |   store float %3, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load double, ptr %a.imagp, align 8
# |   %2 = load double, ptr %b.addr, align 8
# |   %3 = fdiv double %a.real, %2
# |   %4 = fdiv double %a.imag, %2
# |   %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1
# |   store double %3, ptr %retval.realp, align 8
# |   store double %4, ptr %retval.imagp, align 8
# |   %5 = load { double, double }, ptr %retval, align 8
# |   ret { double, double } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { double, double }, align 8
# |   %a.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %1, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %2 = load double, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   %b.real = load double, ptr %b.realp, align 8
# |   %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   %b.imag = load double, ptr %b.imagp, align 8
# |   %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2
# |   %3 = extractvalue { double, double } %call, 0
# |   %4 = extractvalue { double, double } %call, 1
# |   %conv = fptrunc double %3 to float
# |   %conv1 = fptrunc double %4 to float
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %conv, ptr %retval.realp, align 4
# |   store float %conv1, ptr %retval.imagp, align 4
# |   %5 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %5
# | }
# | 
# | declare { double, double } @__divdc3(double, double, double, double)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca double, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.real = load double, ptr %.realp, align 8
# |   %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   %.imag = load double, ptr %.imagp, align 8
# |   %2 = fdiv double %.real, %0
# |   %3 = fdiv double %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   store double %2, ptr %.realp1, align 8
# |   store double %3, ptr %.imagp2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %retval = alloca { x86_fp80, x86_fp80 }, align 16
# |   %b.addr = alloca x86_fp80, align 16
# |   store x86_fp80 %b, ptr %b.addr, align 16
# |   %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0
# |   %a.real = load x86_fp80, ptr %a.realp, align 16
# |   %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1
# |   %a.imag = load x86_fp80, ptr %a.imagp, align 16
# |   %0 = load x86_fp80, ptr %b.addr, align 16
# |   %1 = fdiv x86_fp80 %a.real, %0
# |   %2 = fdiv x86_fp80 %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1
# |   store x86_fp80 %1, ptr %retval.realp, align 16
# |   store x86_fp80 %2, ptr %retval.imagp, align 16
# |   %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16
# |   ret { x86_fp80, x86_fp80 } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %a.addr 
# | ...
# `---data was truncated (10240/11567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000555ceb1bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ceb1b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ceb1bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc6ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc6ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc6ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc6ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ceb151bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ceb151a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ceb1368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ceade5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ceade5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc6ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc6ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc6ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ceade5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (7415 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0
# | ...
# `---data was truncated (10240/29136) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055752fbe2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055752fbdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055752fbe362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7896f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7896f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7896f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7896f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055752fb78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055752fb78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055752fb5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055752f80ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055752f80cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7896f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7896f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7896f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055752f80ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (7416 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561387d82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561387d7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561387d8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0386533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f038658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0386533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f038651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561387d18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561387d18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561387cfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613879ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613879acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f038651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f038651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f038651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613879aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (7417 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565218106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565218103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056521810762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83bd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83bd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83bd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83bd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056521809cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056521809ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652180818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565217d30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565217d30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83bd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83bd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83bd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565217d30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (7418 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ae229feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ae229ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ae22a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f633201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f633201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6332003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ae2235bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ae2235a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ae221a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ae1ec9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ae1ec9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6332004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63320050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ae1ec9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (7419 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639878caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639878c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639878cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9538105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f953815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9538105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95380ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563987860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563987860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639878458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639874f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639874f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95380eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95380ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95380ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639874f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (7420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffbc843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffbc840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffbc84462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe63fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe63faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe63fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe63fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffbc7d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffbc7d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffbc7be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffbc46de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffbc46db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe63fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe63fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe63fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffbc46da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (7421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e494aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e494a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e494ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0418849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0418849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0418831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e49440bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e49440a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e494258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e490d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e490d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0418832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04188330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e490d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (7422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef
# | ...
# `---data was truncated (10240/14333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f934958eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f934955e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f93495962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a85333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a8538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a85333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a8531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9348eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9348eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9348d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f934582e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f934582b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a8531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a8531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a8531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f934582a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (7424 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl
# | ...
# `---data was truncated (10240/27434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee17d0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee17d0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee17d0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe486333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe48638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe486333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe48631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee17ca3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee17ca3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee17c888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee17937e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee17937b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe48631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe48631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe48631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee17937a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (7425 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561adb2d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561adb2cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561adb2d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb64b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb64b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb64b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb64b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561adb268bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561adb268a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561adb24d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561adaefce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561adaefcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb64b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb64b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb64b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561adaefca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (7428 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f92009eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f92009be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f92009f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8286049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8286049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8286031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f920034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f920034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9200198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f91fcc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f91fcc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8286032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82860330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f91fcc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (7429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscal
# | ...
# `---data was truncated (10240/26704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1a7d4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1a7d4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1a7d5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f568cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f568cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f568cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f568cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1a7ce5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1a7ce5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1a7cca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1a7979e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1a7979b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f568cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f568cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f568cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1a7979a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (7430 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604391abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604391a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604391ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e76c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e76ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e76c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e76c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560439141bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560439141a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604391268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560438dd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560438dd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e76c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e76c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e76c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560438dd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (7432 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9b6fb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9b6fb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9b6fb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f091fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f091fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f091fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f091fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9b6f49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9b6f49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9b6f2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9b6bdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9b6bddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f091fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f091fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f091fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9b6bdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (7433 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650a86eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650a86ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650a86ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8f4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8f438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8f4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8f431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650a8684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650a8684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650a86698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650a8318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650a8318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8f431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8f431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8f431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650a8318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (7434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff993bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff993b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff993bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3200f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3200f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3200f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3200f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff99351bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff99351a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff993368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff98fe5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff98fe5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3200f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3200f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3200f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff98fe5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (7439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed25810eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed2580de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed2581162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64d4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64d418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64d4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64d411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed257a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed257a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed2578b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed2543ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed2543ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64d411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64d411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64d411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed2543aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (7440 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_
# | ...
# `---data was truncated (10240/11895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0b9081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0b907ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0b908262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd3a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd3a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd3a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd3a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0b9017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0b9017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0b8ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0b8cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0b8cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd3a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd3a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd3a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0b8caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (7441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale 
# | ...
# `---data was truncated (10240/40937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e8debeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e8debbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e8debf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba5c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba5c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba5c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba5c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e8de54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e8de54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e8de398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e8dae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e8dae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba5c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba5c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba5c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e8dae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (7442 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556261c77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556261c74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556261c7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71f9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71f938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71f9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71f931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556261c0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556261c0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556261bf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562618a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562618a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71f931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71f931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71f931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562618a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (7443 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64
# | ...
# `---data was truncated (10240/29259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557579fd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557579fd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557579fd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85bbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85bbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85bbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85bbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557579f6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557579f6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557579f518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557579c00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557579c00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85bbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85bbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85bbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557579c00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (7445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloc
# | ...
# `---data was truncated (10240/27533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573bea00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573be9fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573bea0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06b5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06b5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06b5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06b5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573be996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573be996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573be97b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573be62ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573be62ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06b5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06b5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06b5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573be62aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (7446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c09544deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c09544ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c09544e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ea4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ea418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ea4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ea411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0953e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0953e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0953c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c095077e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c095077b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ea411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ea411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ea411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c095077a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (7448 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9ccc33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9ccc30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9ccc3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bd8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bd818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bd8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bd811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9ccbc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9ccbc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9ccbae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9cc85de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9cc85db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bd811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bd811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bd811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9cc85da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (7449 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056414d9b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056414d9b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056414d9ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d8ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414d94fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056414d94fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056414d9348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056414d5e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056414d5e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5d8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d8cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056414d5e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (7450 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c89fa9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c89fa9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c89fa9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dc9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dc96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dc9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dc9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c89fa33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c89fa33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c89fa188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c89f6c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c89f6c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dc9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dc96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dc96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c89f6c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (7451 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581c0c93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581c0c90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581c0c9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb18733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb1878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb18733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb1871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581c0c29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581c0c29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581c0c0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581c08bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581c08bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb1871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb1871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb1871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581c08bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (7453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbaf8dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbaf8d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbaf8dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6598c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6598ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6598c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6598c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbaf872bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbaf872a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbaf8578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbaf506e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbaf506b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6598c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6598c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6598c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbaf506a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (7454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641f33e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641f33e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641f33e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f378e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f378e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f378e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f378e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641f337abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641f337aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641f335f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641f300ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641f300eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f378e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f378e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f378e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641f300ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (7455 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri
# | ...
# `---data was truncated (10240/20523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055953b6dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055953b6dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055953b6e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dadb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dadb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dadb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dadb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055953b675bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055953b675a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055953b65a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055953b309e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055953b309b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dadb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dadb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dadb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055953b309a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (7457 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562237360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056223735de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056223736162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30a8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30a86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30a8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30a8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622372f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622372f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622372db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562236f8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562236f8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30a8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30a86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30a86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562236f8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (7458 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   
# | ...
# `---data was truncated (10240/19123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056241f9fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056241f9f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056241f9fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17b5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17b5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17b5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17b5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056241f991bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056241f991a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056241f9768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056241f625e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056241f625b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17b5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17b5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17b5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056241f625a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (7459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593b4938eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593b4935e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593b493962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f089a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f089a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f089a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f089a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593b48cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593b48cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593b48b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593b4562e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593b4562b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f089a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f089a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f089a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593b4562a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (7460 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055662d94feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055662d94ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055662d95062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff22d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff22d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff22d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff22d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662d8e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055662d8e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055662d8ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055662d579e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055662d579b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff22d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff22d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff22d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055662d579a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (7462 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2_m(<vscale x 2 x i1> %mask,
# | ...
# `---data was truncated (10240/13544) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580a44c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580a44c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580a44c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f87449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f87449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f87431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580a4459bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580a4459a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580a443e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580a40ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580a40edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f87432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580a40eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (7463 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d3f9ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d3f9cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d3f9cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f003d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f003d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f003d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f003d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d3f964bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d3f964a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d3f9498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d3f5f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d3f5f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f003d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f003d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f003d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d3f5f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (7466 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c2351aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c23517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c2351b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7655d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7655d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7655d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7655ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c234b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c234b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c234958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c23144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c23144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7655ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7655cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7655cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c23144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (7467 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 
# | ...
# `---data was truncated (10240/28361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eedb6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556eedb69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556eedb6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8636449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8636449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8636431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eedb02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556eedb02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556eedae78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eed796e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eed796b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8636432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eed796a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (7469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564412f18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564412f15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564412f1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa15e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa15ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa15e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa15e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564412eaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564412eaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564412e938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564412b42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564412b42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa15e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa15e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa15e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564412b42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (7470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr,
# | ...
# `---data was truncated (10240/23056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ada7335eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ada7332e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ada733662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ada72cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ada72cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ada72b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ada6f5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ada6f5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ada6f5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (7471 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f75d077eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f75d074e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f75d07862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19fcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19fcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19fcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19fcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f75d00dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f75d00da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f75cff28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f75cca1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f75cca1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19fcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19fcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19fcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f75cca1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (7473 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d910f4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d910f48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d910f4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f399de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f399dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f399de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f399de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d910ee1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d910ee1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d910ec68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d910b75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d910b75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f399de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f399de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f399de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d910b75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (7477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772a5d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055772a5d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055772a5da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c5df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772a56fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055772a56fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055772a5548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055772a203e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055772a203b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772a203a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (7478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afa8555eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afa8552e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afa855662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e8b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e8b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e8b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e8b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afa84ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afa84eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afa84d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afa817fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afa817fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e8b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e8b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e8b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afa817fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (7479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577935d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577935cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577935d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8acae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8acaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8acae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8acae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557793568bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557793568a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055779354d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577931fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577931fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8acae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8acae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8acae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577931fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (7481 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fb2a4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564fb2a48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564fb2a4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fb29e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564fb29e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564fb29c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564fb2675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564fb2675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fb2675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (7482 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5cc133eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5cc130e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5cc13462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb677333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb67738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb677333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb67731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5cc0c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5cc0c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5cc0ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5cbd5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5cbd5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb67731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb67731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb67731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5cbd5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (7487 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc70629eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc70626e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc7062a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a73b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a73b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a73b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a73b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc705bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc705bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc705a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc70253e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc70253b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a73b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a73b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a73b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc70253a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (7488 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569af108eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569af105e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569af10962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a98333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a9838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a98333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a9831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569af09ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569af09ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569af0838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569aed32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569aed32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a9831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a9831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a9831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569aed32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (7490 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a9981deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a9981ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a9981e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f80a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f80a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f80a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f80a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a997b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a997b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a997988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a99447e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a99447b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f80a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f80a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f80a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a99447a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (7491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563131c52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563131c4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563131c5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f532fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f532fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f532fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f532fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563131be8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563131be8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563131bcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056313187ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056313187cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f532fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f532fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f532fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056313187ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (7492 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eebfafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563eebface85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563eebfb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafba71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eebf45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563eebf45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563eebf2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eebbd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eebbd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafba71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eebbd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (7493 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556074839eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556074836e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055607483a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdebd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560747cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560747cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560747b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556074463e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556074463b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556074463a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (7495 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c11ee18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c11ee15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c11ee1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb903849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9038a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb903849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb903831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c11edaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c11edaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c11ed938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c11ea42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c11ea42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb903832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9038330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9038330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c11ea42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (7498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556a0a22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556a0a1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556a0a2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f070fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f070fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f070fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f070fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556a09b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556a09b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556a099d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556a064ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556a064cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f070fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f070fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f070fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556a064ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (7500 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d1f984eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d1f981e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1f98562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f689b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f689b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f689b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f689b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d1f91abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d1f91aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d1f8ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d1f5aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d1f5aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f689b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f689b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f689b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d1f5aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (7501 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da403fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da403f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da403fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80fac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80faca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80fac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80fac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da40391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da40391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da403768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da40025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da40025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80fac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80fac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80fac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da40025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (7502 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f9fd54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f9fd51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f9fd5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9779305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f977935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9779305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97792ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f9fceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f9fceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f9fccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f9f97ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f9f97eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97792eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97792ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97792ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f9f97ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (7503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad33573eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad33570e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad3357462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6836449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6836449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6836431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad33509bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad33509a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad334ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad3319de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad3319db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6836432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad3319da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (7504 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566bed29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566bed26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566bed2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb66a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb66a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb66a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb66a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566becbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566becbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566beca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566be953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566be953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb66a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb66a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb66a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566be953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (7505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vsc
# | ...
# `---data was truncated (10240/21473) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d73df6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d73df3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d73df762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2940933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f294098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2940933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f294091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d73d8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d73d8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d73d718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d73a20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d73a20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f294091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f294091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f294091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d73a20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (7506 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %v
# | ...
# `---data was truncated (10240/23064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e45aedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e45aeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e45aee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51e9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51e92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51e9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51e9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e45a83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e45a83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e45a688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e45717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e45717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51e9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51e92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51e92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e45717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (7507 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %
# | ...
# `---data was truncated (10240/27994) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563043673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563043670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056304367462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563043609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563043609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630435ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056304329de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056304329db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056304329da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (7508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb4e695eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb4e692e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb4e69662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4f2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4f2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4f2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4f2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb4e62bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb4e62ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb4e6108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb4e2bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb4e2bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4f2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4f2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4f2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb4e2bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (7509 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x
# | ...
# `---data was truncated (10240/24328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640b054ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640b0549e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640b054d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1995b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1995b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1995b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1995aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640b04e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640b04e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640b04c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640b0176e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640b0176b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1995aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1995aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1995aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640b0176a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (7510 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592cd044eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592cd041e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592cd04562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b8e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b8e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b8e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b8e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592ccfdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592ccfdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592ccfbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592ccc6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592ccc6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b8e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b8e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b8e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592ccc6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (7513 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6bbde0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6bbddde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6bbde162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd19e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd19e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd19e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6bbd76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6bbd76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6bbd5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6bba0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6bba0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd19e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd19e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd19e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6bba0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (7515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055685ff02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055685feffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055685ff0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3befd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3befd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3befd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3befd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055685fe98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055685fe98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055685fe7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055685fb2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055685fb2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3befd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3befd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3befd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055685fb2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (7517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571c087eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571c087be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571c087f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f059b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f059b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f059b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f059b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571c0814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571c0814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571c07f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571c04a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571c04a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f059b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f059b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f059b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571c04a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (7518 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i
# | ...
# `---data was truncated (10240/14325) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb76975eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb76972e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb7697662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd6b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd6b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd6b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd6b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb7690bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb7690ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb768f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb7659fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb7659fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd6b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd6b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd6b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb7659fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (7519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b18193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b18190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b1819462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5579649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55796a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5579649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5579631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b18129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b18129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b1810e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b17dbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b17dbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5579632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55796330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55796330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b17dbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (7520 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   
# | ...
# `---data was truncated (10240/13255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590a2356eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590a2353e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590a235762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe23f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe23f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe23f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590a22ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590a22eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590a22d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590a1f80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590a1f80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe23f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe23f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe23f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590a1f80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (7523 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7d12d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7d12d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7d12d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd819c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd819ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd819c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd819c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7d126cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7d126ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7d12518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7d0f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7d0f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd819c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd819c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd819c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7d0f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (7524 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055758ee17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055758ee14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055758ee1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2764305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f276435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2764305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27642ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055758edadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055758edada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055758ed928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055758ea41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055758ea41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27642eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27642ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27642ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055758ea41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (7525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1d537deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1d537ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1d537e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f069b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f069b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f069b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f069b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1d5313bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1d5313a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1d52f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1d4fa7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1d4fa7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f069b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f069b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f069b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1d4fa7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (7527 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.
# | ...
# `---data was truncated (10240/15486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a04530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a0452de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a0453162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f4c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f4c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f4c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f4c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a044c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a044c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a044ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a0415ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a0415ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f4c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f4c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f4c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a0415aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (7529 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cc97eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cc97e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cc97eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c3621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c362725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c3621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c36203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cc9780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cc9780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cc97658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cc9414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cc9414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c36204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c362050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c362050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cc9414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (7530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7c19d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7c19cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7c19d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5265333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f526538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5265333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f526531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7c1968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7c1968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7c194d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7c15fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7c15fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f526531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f526531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f526531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7c15fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (7531 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b38625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b38622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b3862662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a74333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a7438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a74333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a7431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b385bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b385bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b385a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b3824fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b3824fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a7431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a7431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a7431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b3824fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (7532 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>
# | ...
# `---data was truncated (10240/47764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f5b562eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f5b55fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f5b56362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad36f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad36f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad36f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad36f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f5b4f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f5b4f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f5b4dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f5b18ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f5b18cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad36f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad36f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad36f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f5b18ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (7533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa6e986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa6e983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa6e98762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2399d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2399d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2399d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2399d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa6e91cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa6e91ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa6e9018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa6e5b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa6e5b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2399d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2399d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2399d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa6e5b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (7535 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055826f40feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055826f40ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055826f41062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055826f3a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055826f3a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055826f38a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055826f039e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055826f039b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055826f039a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (7536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556415297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556415294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055641529862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7225b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7225b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7225b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7225b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055641522dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055641522da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564152128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556414ec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556414ec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7225b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7225b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7225b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556414ec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (7538 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, a
# | ...
# `---data was truncated (10240/28358) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c6bb4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c6bb49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c6bb4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcd4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcd495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcd4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcd48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c6bae2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c6bae2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c6bac78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c6b776e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c6b776b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcd48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcd48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcd48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c6b776a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (7539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/26996) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056527c1d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056527c1d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056527c1d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc603249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6032a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc603249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc603231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056527c16cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056527c16ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056527c1518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056527be00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056527be00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc603232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6032330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6032330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056527be00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (7540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056365d52aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056365d527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056365d52b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd226449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd226449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd226431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365d4c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056365d4c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056365d4a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056365d154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056365d154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd226432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056365d154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (7542 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d1587ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d15879e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d1587d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefa9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefa9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefa9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefa9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d15812bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d15812a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d157f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d154a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d154a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefa9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefa9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefa9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d154a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (7544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b34b746eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b34b743e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b34b74762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe207b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe207b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe207b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe207aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b34b6dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b34b6dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b34b6c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b34b370e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b34b370b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe207aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe207aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe207aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b34b370a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (7546 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5303e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5303dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5303e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe173249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe173249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe173231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f530378bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f530378a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f53035d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f53000ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f53000cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe173232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f53000ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (7547 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564648abeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564648abbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564648abf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febc3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febc358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febc3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febc351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564648a54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564648a54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564648a398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646486e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646486e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febc351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febc351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febc351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646486e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (7549 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564207e33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564207e30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564207e3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4c9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4c98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4c9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4c9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564207dc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564207dc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564207dae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564207a5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564207a5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4c9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4c98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4c98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564207a5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (7552 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639f0136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639f0133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639f013762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f00849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f008a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f00849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f00831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639f00ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639f00cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639f00b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639efd60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639efd60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f00832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f008330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f008330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639efd60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (7553 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | defin
# | ...
# `---data was truncated (10240/13035) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5938b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5938b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5938b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3df249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3df2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3df249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3df231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b59384dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b59384da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5938328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5934e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5934e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3df232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3df2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3df2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5934e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (7554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c16d8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c16d8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c16d8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea6cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea6cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea6cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea6cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c16d24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c16d24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c16d098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c169b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c169b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea6cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea6cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea6cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c169b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (7556 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdbf7aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdbf7a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdbf7ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc099333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc09938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc099333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc09931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdbf742bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdbf742a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdbf7278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdbf3d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdbf3d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc09931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc09931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc09931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdbf3d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (7557 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.
# | ...
# `---data was truncated (10240/11504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a09572eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a0956fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a0957362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ed4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ed438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ed4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ed431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a09508bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a09508a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a094ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a0919ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a0919cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ed431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ed431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ed431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a0919ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (7558 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bb4788eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bb4785e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bb478962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a3e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a3e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a3e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a3e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bb471ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bb471ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bb47038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bb43b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bb43b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a3e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a3e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a3e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bb43b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (7559 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, a
# | ...
# `---data was truncated (10240/18875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c35d45feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c35d45ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c35d46062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45dbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45dbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45dbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45dbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c35d3f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c35d3f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c35d3da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c35d089e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c35d089b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45dbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45dbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45dbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c35d089a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (7560 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056472d8d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056472d8d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056472d8d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f678341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67834725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f678341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6783403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056472d86bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056472d86ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056472d8508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056472d4ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056472d4ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6783404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67834050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67834050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056472d4ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (7561 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561231208eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561231205e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056123120962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd16fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd16fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd16fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd16fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056123119ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056123119ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612311838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561230e32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561230e32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd16fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd16fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd16fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561230e32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (7562 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfe4e0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfe4e0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfe4e1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f143bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f143bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f143bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f143beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfe4da5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfe4da5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfe4d8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfe4a39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfe4a39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f143beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f143beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f143beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfe4a39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (7563 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i6
# | ...
# `---data was truncated (10240/11946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e58a41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e58a3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e58a4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40d2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40d2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40d2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40d2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e589d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e589d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e589bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e5866be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e5866bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40d2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40d2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40d2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e5866ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (7564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.ad
# | ...
# `---data was truncated (10240/26762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561002c3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561002c38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561002c3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a17649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a176a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a17649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a17631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561002bd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561002bd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561002bb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561002865e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561002865b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a17632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a176330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a176330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561002865a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (7565 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556289e71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556289e6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556289e7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3013933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f301398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3013933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f301391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556289e07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556289e07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556289dec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556289a9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556289a9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f301391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f301391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f301391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556289a9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (7566 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f1216aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f12167e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f1216b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f760fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f760fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f12100bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f12100a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f120e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f11d94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f11d94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f11d94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (7567 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 
# | ...
# `---data was truncated (10240/11237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e296a8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e296a8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e296a9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6737849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67378a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6737849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6737831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e296a25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e296a25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e296a0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2966b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2966b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6737832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67378330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67378330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2966b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (7569 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a29d35beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a29d358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a29d35c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc181733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc18178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc181733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc18171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a29d2f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a29d2f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a29d2d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a29cf85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a29cf85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc18171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc18171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc18171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a29cf85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (7571 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565092373eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565092370e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056509237462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdda2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdda26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdda2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdda2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565092309bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565092309a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650922ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565091f9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565091f9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdda2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdda26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdda26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565091f9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (7573 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a554a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a554a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a554aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc732133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc73218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc732133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc73211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a5543fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a5543fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a554248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a550d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a550d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc73211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc73211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc73211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a550d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (7575 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a5a2d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a5a2cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a5a2d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadf5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadf5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadf5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadf5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a5a268bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a5a268a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a5a24d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a59efce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a59efcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadf5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadf5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadf5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a59efca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (7576 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af36228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af36225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af3622962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04c221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04c22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04c221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04c2203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af361bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af361bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af361a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af35e52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af35e52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04c2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04c22050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04c22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af35e52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (7578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2ae64eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2ae64be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2ae64f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2ae5e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2ae5e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2ae5c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2ae278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2ae278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2ae278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (7579 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x bfloa
# | ...
# `---data was truncated (10240/12528) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d282bfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d282bf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d282bfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd58449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd58449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd58431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d282b91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d282b91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d282b768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d282825e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d282825b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd58432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd584330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d282825a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (7580 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fda3b7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fda3b77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fda3b7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96a8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96a8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96a8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96a8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fda3b10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fda3b10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fda3af58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fda37a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fda37a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96a8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96a8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96a8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fda37a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (7582 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563db9956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563db9953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563db995762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c07249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c072a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c07249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c07231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563db98ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563db98eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563db98d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563db9580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563db9580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c07232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c072330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c072330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563db9580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (7583 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c28400deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c28400ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c28400e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6dbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6dbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6dbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6dbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c283fa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c283fa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c283f888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c283c37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c283c37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6dbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6dbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6dbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c283c37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (7584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c20080eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c2007de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c2008162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efeaec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efeaeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efeaec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efeaec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c20016bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c20016a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c1fffb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c1fcaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c1fcaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efeaec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efeaec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efeaec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c1fcaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (7586 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dbe98feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dbe98ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dbe99062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d4b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d4b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d4b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d4b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dbe925bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dbe925a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dbe90a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dbe5b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dbe5b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d4b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d4b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d4b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dbe5b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (7587 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056080523feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056080523ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056080524062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6698133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f669818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6698133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f669811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608051d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608051d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608051ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560804e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560804e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f669811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f669811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f669811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560804e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (7589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f757efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f757ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f757f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f330fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f330fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f75785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f75785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f7576a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f75419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f75419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f330fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f75419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (7591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/30690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574c2425eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574c2422e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574c242662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf5b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf5b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf5b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf5b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574c23bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574c23bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574c23a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574c204fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574c204fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf5b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf5b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf5b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574c204fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (7595 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/22298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559308bdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559308bd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559308bdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68d9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68d955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68d9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68d94ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559308b71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559308b71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559308b568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559308805e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559308805b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68d94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68d94ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68d94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559308805a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (7596 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nou
# | ...
# `---data was truncated (10240/25034) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd2b1f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd2b1f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd2b1f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd6b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd6b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd6b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd6b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd2b18dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd2b18da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd2b1728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd2ae21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd2ae21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd6b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd6b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd6b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd2ae21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (7597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1
# | ...
# `---data was truncated (10240/19049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b961d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b961d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b961d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7203449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72034a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7203449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7203431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b9616dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b9616da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b961528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b95e01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b95e01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7203432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72034330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72034330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b95e01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (7599 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556c6cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556c6cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556c6cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f491ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f491ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f491ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f491ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556c6c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556c6c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556c6c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556c6906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556c6906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f491ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f491ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f491ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556c6906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (7600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr
# | ...
# `---data was truncated (10240/29319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ab55e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ab55dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ab55e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe23533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe2358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe23533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe2351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ab5578bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ab5578a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ab555d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ab520ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ab520cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe2351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe2351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe2351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ab520ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (7601 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613d3857eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613d3854e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613d385862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f630b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f630b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f630b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f630b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613d37edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613d37eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613d37d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613d3481e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613d3481b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f630b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f630b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f630b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613d3481a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (7602 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/15211) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ae68d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ae68cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ae68d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0a3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0a378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0a3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0a371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ae6868bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ae6868a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ae684d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ae64fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ae64fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0a371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0a371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0a371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ae64fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (7603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/12433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564964f7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564964f78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564964f7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1da333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1da38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1da333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1da31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564964f11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564964f11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564964ef68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564964ba5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564964ba5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1da31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1da31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1da31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564964ba5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (7605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde
# | ...
# `---data was truncated (10240/16083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feb604feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feb604ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feb605062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3bd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3bd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3bd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3bd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feb5fe5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feb5fe5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feb5fca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feb5c79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feb5c79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3bd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3bd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3bd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feb5c79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (7607 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558943143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558943140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055894314462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f608bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f608bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f608bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f608bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589430d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589430d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589430be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558942d6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558942d6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f608bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f608bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f608bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558942d6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (7609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>,
# | ...
# `---data was truncated (10240/11969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056345b6abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056345b6a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056345b6ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98ac01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98ac0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98ac01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98ac003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056345b641bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056345b641a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056345b6268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056345b2d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056345b2d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98ac004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98ac0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98ac0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056345b2d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (7610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8a362aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8a3627e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8a362b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fb2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fb2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fb2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fb2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8a35c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8a35c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8a35a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8a3254e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8a3254b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fb2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fb2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fb2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8a3254a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (7611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e637f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e637f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e637fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ec1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ec1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ec1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ec1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e6378fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e6378fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e637748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e63423e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e63423b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ec1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ec1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ec1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e63423a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (7612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056043773deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056043773ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056043773e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9d391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604376d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604376d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604376b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560437367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560437367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9d391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560437367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (7613 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559302e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559302e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559302e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0844905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f084495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0844905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08448ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559302dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559302deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559302dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559302a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559302a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08448eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08448ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08448ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559302a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (7615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c922203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c922200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c92220462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2526733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f252678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2526733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f252671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c922199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c922199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c92217e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c921e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c921e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f252671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f252671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f252671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c921e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (7617 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbd9061eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbd905ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbd906262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b3ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b3ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbd8ff7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbd8ff7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbd8fdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbd8c8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbd8c8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b3ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b3ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b3ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbd8c8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (7618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/32702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f65c009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f65c006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f65c00a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb47b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb47b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb47b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb47b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f65bf9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f65bf9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f65bf848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f65bc33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f65bc33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb47b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb47b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb47b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f65bc33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (7619 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644a9423eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644a9420e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644a942462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644a93b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644a93b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644a939e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644a904de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644a904db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644a904da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (7621 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d418ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d418cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d418cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf1bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d41864bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d41864a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d418498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d414f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d414f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d414f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (7622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cbab9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cbab9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cbaba062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c01733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c01733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cbab35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cbab35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cbab1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cba7c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cba7c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c0171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cba7c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (7623 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b868168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b868165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b86816962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18f6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18f6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18f6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18f6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8680febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8680fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8680e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b867d92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b867d92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18f6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18f6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18f6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b867d92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (7624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc36312eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc3630fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc3631362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe76f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe76f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe76f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe76f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc362a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc362a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc3628d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc35f3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc35f3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe76f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe76f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe76f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc35f3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (7625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555650fa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555650fa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555650fa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff220c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff220ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff220c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff220c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555650f3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555650f3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555650f238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555650bd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555650bd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff220c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff220c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff220c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555650bd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (7626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ec9ce1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ec9cdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ec9ce262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ec9c77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ec9c77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ec9c5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ec990be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ec990bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ec990ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (7627 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5da84beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5da848e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5da84c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a61933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a6198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a61933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a6191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5da7e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5da7e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5da7c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5da475e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5da475b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a6191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a6191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a6191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5da475a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (7630 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555748ad6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555748ad3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555748ad762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25a2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25a2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25a2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25a2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555748a6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555748a6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555748a518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555748700e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555748700b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25a2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25a2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25a2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555748700a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (7632 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dd11cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dd11cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dd11ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ed9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ed9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ed9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ed9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dd1163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dd1163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dd11488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dd0df7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dd0df7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ed9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ed9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ed9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dd0df7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (7633 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c3f5a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c3f5a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c3f5a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b43c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b43ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b43c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b43c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c3f53abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c3f53aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c3f51f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c3f1cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c3f1ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b43c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b43c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b43c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c3f1cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (7634 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, al
# | ...
# `---data was truncated (10240/13263) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565504456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565504453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056550445762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc750133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc75018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc750133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc75011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005655043ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005655043eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005655043d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565504080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565504080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc75011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc75011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc75011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565504080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (7635 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640cab0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640cab07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640cab0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d2521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d252725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d2521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d25203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640caaa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640caaa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640caa858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640ca734e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640ca734b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d25204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d252050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d252050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640ca734a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (7636 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614b28bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614b28b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614b28bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614b2851bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614b2851a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614b28368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614b24e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614b24e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbd8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614b24e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (7637 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ce150deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ce150ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ce150e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01ed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01ed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01ed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01ed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ce14a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ce14a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ce14888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ce1137e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ce1137b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01ed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01ed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01ed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ce1137a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (7639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64 noundef
# | ...
# `---data was truncated (10240/29167) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b27ae0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b27adde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b27ae162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f765c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f765c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f765c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f765c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b27a76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b27a76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b27a5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b2770ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b2770ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f765c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f765c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f765c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b2770aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (7640 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5a9bbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5a9bbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5a9bc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3910533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f391058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3910533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f391051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5a9b55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5a9b55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5a9b3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5a97e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5a97e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f391051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f391051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f391051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5a97e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (7641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b216063eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b216060e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b21606462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3df449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3df4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3df449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3df431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b215ff9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b215ff9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b215fde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b215c8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b215c8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3df432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3df4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3df4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b215c8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (7642 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622509a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622509a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622509a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056225093dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056225093da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622509228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622505d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622505d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622505d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (7643 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x 
# | ...
# `---data was truncated (10240/26696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebcc3a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebcc3a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebcc3a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefeb81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefeb8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefeb81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefeb803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebcc33abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebcc33aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebcc31f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebcbfcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebcbfceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefeb804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefeb8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefeb8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebcbfcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (7646 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610f28afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610f28ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610f28b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1f581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1f58725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1f581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1f5803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610f2845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610f2845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610f282a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610f24d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610f24d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1f5804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1f58050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1f58050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610f24d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (7648 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9bee9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9bee99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9bee9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee2c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee2c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9bee32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9bee32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9bee178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9beac6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9beac6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee2c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9beac6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (7649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 
# | ...
# `---data was truncated (10240/24206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfa7efbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfa7ef8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfa7efc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b13c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b13ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b13c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b13c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfa7e91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfa7e91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfa7e768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfa7b25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfa7b25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b13c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b13c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b13c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfa7b25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (7650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efd89a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efd89a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efd89a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5774f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5774f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5774f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5774f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efd893bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efd893ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efd89208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efd85cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efd85cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5774f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5774f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5774f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efd85cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (7651 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c60d81eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c60d81be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c60d81f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8470849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8470849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8470831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c60d7b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c60d7b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c60d7998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c60d448e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c60d448b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8470832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84708330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c60d448a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (7652 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619392c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619392c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619392ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f326a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f326a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f326a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f326a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056193925fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056193925fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619392448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561938ef3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561938ef3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f326a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f326a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f326a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561938ef3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (7653 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577dadb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577dadafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577dadb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f060b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f060b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f060b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f060b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577dad48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577dad48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577dad2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577da9dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577da9dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f060b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f060b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f060b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577da9dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (7654 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f44c0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f44c0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f44c0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd57ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd57baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd57ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd57ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f44ba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f44ba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f44b888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f44837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f44837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd57ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd57ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd57ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f44837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (7656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf4_f16(<vscale x 1 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf2_f16(<vscale x 2 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m1_f16(<vscale x 4 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m2_f16(<vscale x 8 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m4_f16(<vscale x 16 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m8_f16(<vscale x 32 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32mf2_f32(<vscale x 1 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m1_f32(<vscale x 2 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m2_f32(<vscale x 4 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m4_f32(<vscale x 8 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m8_f32(<vscale x 16 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m1_f64(<vscale x 1 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m2_f64(<vscale x 2 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m4_f64(<vscale x 4 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m8_f64(<vscale x 8 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605e658deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605e658ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605e658e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d5dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605e6523bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605e6523a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605e65088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605e61b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605e61b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605e61b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (7659 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565e205feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565e205ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565e206062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec54d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec54d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec54d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec54d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565e1ff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565e1ff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565e1fda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565e1c89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565e1c89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec54d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec54d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec54d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565e1c89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (7661 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr,
# | ...
# `---data was truncated (10240/30874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cf3176eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cf3173e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cf317762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75fef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75fef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75fef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75fef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cf310cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cf310ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cf30f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cf2da0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cf2da0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75fef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75fef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75fef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cf2da0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (7662 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559164cf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559164cf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559164cfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61d891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559164c8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559164c8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559164c748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559164923e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559164923b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61d891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559164923a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (7665 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b28370ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b283709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b28370d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09fb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09fb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09fb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09fb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2836a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2836a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2836878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b283336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b283336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09fb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09fb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09fb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b283336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (7667 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a560959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a560956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a56095a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1a2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1a238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1a2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1a231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5608efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5608efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5608d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a560583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a560583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1a231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1a231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1a231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a560583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (7669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b3e472eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b3e46fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b3e47362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9231733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f923178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9231733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f923171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b3e408bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b3e408a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b3e3ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b3e09ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b3e09cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f923171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f923171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f923171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b3e09ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (7670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568b1c4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568b1c47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568b1c4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ff1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ff1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ff1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ff1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568b1be0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568b1be0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568b1bc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568b1874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568b1874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ff1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ff1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ff1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568b1874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (7671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/27055) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609df82aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609df827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609df82b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa833e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa833ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa833e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa833e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609df7c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609df7c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609df7a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609df454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609df454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa833e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa833e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa833e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609df454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (7672 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a8bfa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a8bfa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a8bfa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9cc61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9cc6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9cc61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9cc603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a8bf3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a8bf3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a8bf218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a8bbd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a8bbd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9cc604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9cc6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9cc6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a8bbd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (7674 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055741f264eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055741f261e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055741f26562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2ae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2ae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2ae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2ae11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055741f1fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055741f1faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055741f1df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055741ee8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055741ee8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2ae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2ae11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2ae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055741ee8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (7676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   
# | ...
# `---data was truncated (10240/17236) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e842161eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e84215ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e84216262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dcf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dcf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dcf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dcf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8420f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8420f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8420dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e841d8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e841d8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5dcf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dcf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dcf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e841d8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (7678 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634c78d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634c78d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634c78d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d2341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d234725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d2341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d23403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634c7869bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634c7869a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634c784e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634c74fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634c74fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d23404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d234050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d234050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634c74fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (7679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 
# | ...
# `---data was truncated (10240/27063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c703c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c703c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c703c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeeb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeeb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeeb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeeb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c703bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c703bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c703bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c70385de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c70385db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeeb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeeb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeeb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c70385da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (7681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e90c19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e90c16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e90c1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb69f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb69f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb69f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb69f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e90bafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e90bafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e90b948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e90843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e90843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb69f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb69f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb69f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e90843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (7684 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6745a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6745a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6745a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd946a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd946aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd946a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd946a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d67453cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d67453ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6745218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6741d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6741d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd946a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd946a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd946a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6741d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (7686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c320bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c320b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c320bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d75533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d7558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d75533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d7551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c32052bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c32052a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c320378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c31ce6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c31ce6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d7551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d7551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d7551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c31ce6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (7687 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055791a17beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055791a178e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055791a17c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f0c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f0c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f0c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f0c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055791a111bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055791a111a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055791a0f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557919da5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557919da5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f0c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f0c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f0c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557919da5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (7688 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0ededbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0eded8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0ededc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb585d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb585d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb585d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb585ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0ede71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0ede71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0ede568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0edb05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0edb05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb585ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb585cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb585cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0edb05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (7689 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cc857deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cc857ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cc857e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51aa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51aa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51aa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51aa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cc8513bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cc8513a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cc84f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cc81a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cc81a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51aa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51aa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51aa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cc81a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (7690 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7d856aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7d8567e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7d856b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7d8500bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7d8500a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7d84e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7d8194e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7d8194b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd44aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7d8194a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (7694 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a7d2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645a7d29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645a7d2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf05649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf05649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf05631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a7cc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645a7cc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645a7ca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645a7956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645a7956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf05632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf056330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a7956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (7695 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff8c007eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff8c004e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff8c00862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72ea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72ea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72ea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72ea431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff8bf9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff8bf9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff8bf828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff8bc31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff8bc31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72ea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72ea4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72ea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff8bc31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (7699 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f31ab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f31ab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f31ab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efebb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efebb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efebb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efebb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f31a4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f31a4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f31a318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f316e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f316e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efebb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efebb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efebb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f316e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (7700 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3abf52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3abf4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3abf5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93df049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93df0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93df049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93df031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3abee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3abee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3abecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3abb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3abb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93df032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93df0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93df0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3abb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (7701 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect
# | ...
# `---data was truncated (10240/32932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556da37bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556da37b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556da37bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa629933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa62998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa629933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa62991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556da3751bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556da3751a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556da37368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556da33e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556da33e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa62991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa62991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa62991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556da33e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (7705 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643a1dc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643a1dbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643a1dc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fded921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fded92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fded921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fded9203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643a1d57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643a1d57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643a1d3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643a19ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643a19ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fded9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fded92050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fded92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643a19eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (7706 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 
# | ...
# `---data was truncated (10240/28683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e20b00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e20afde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e20b0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9049049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90490a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9049049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9049031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e20a96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e20a96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e20a7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e2072ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e2072ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9049032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90490330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90490330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e2072aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (7707 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2abf9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2abf9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2abfa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa69d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa69d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa69d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa69d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2abf35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2abf35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2abf1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2abbc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2abbc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa69d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa69d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa69d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2abbc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (7709 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b42ee84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b42ee81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b42ee8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b42ee1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b42ee1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b42edff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b42eaaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b42eaaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b42eaaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (7710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmset_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmset_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmset_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmset_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmset_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmset_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmset_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e1b317eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e1b314e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e1b31862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb7b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb7b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb7b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb7b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e1b2adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e1b2ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e1b2928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e1af41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e1af41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb7b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb7b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb7b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e1af41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (7712 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606db45ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606db459e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606db45d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f123921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12392725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f123921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1239203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606db3f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606db3f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606db3d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606db086e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606db086b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1239204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12392050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12392050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606db086a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (7713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nounwind }
# | attributes #2 = { nounwind memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559829b51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559829b4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559829b5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1517449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1517449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1517431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559829ae7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559829ae7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559829acc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055982977be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055982977bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1517432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055982977ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (7715 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af7a442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af7a43fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af7a44362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbea7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbea70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbea7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbea7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af7a3d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af7a3d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af7a3bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af7a06ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af7a06cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbea7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbea70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbea70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af7a06ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (7717 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd3687eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd3687be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd3687f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc79449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc794a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc79449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc79431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd36814bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd36814a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd367f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd364a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd364a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc79432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc794330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc794330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd364a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (7719 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a3bc18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a3bc15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a3bc1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7746733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f774678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7746733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f774671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a3bbaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a3bbaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a3bb938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a3b842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a3b842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f774671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f774671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f774671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a3b842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (7721 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f0c3b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f0c3b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f0c3b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ae2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ae26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ae2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ae2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f0c34bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f0c34ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f0c3308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f0bfdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f0bfdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ae2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ae26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ae26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f0bfdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (7723 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4342baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4342b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4342bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2371249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2371249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2371231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f434250bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f434250a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4342358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f433ee4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f433ee4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2371232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23712330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f433ee4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (7724 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fe0ff1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fe0feee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fe0ff262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6554133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6554133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f655411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fe0f87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fe0f87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fe0f6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fe0c1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fe0c1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f655411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f655411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f655411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fe0c1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (7726 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0502bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0502b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0502bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdad2d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdad2d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdad2d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdad2ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b050252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b050252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0502378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b04fee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b04fee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdad2ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdad2cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdad2cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b04fee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (7727 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ebbb67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ebbb64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ebbb6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0931133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0931133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ebbafdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ebbafda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ebbae28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ebb791e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ebb791b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f093111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ebb791a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (7728 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558640924eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558640921e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055864092562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa55ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa55ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa55ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa55ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586408babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586408baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055864089f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055864054ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055864054eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa55ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa55ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa55ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055864054ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (7730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582df1a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582df1a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582df1aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18e5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18e518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18e5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18e511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582df13fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582df13fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582df1248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582dedd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582dedd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18e511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18e511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18e511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582dedd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (7731 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b3ddcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b3ddcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b3ddce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b21133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b21133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b3dd63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b3dd63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b3dd488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b3d9f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b3d9f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b2111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b3d9f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (7732 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe6a83beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe6a838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe6a83c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0c8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0c8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0c8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0c8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe6a7d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe6a7d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe6a7b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe6a465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe6a465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0c8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0c8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0c8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe6a465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (7734 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559423908eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559423905e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055942390962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7024e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7024ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7024e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7024e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055942389ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055942389ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594238838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559423532e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559423532b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7024e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7024e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7024e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559423532a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (7735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb085aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb0857e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb085b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb07f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb07f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb07d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb0484e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb0484b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb0484a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (7736 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c1c192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c1c18fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c1c19362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f111d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f111d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f111d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f111d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c1c128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c1c128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c1c10d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c1bdbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c1bdbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f111d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f111d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f111d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c1bdbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (7737 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store targ
# | ...
# `---data was truncated (10240/14667) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baf507deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baf507ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baf507e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecd2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecd22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecd2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecd2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baf5013bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baf5013a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baf4ff88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baf4ca7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baf4ca7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecd2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecd22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecd22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baf4ca7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (7738 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b72abdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b72abdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b72abe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f750b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f750b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f750b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f750b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b72ab75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b72ab75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b72ab5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b72a809e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b72a809b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f750b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f750b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f750b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b72a809a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (7741 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a76c91beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a76c918e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a76c91c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a76c8b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a76c8b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a76c8968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a76c545e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a76c545b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a76c545a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (7744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4c71f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4c71f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4c71f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7f2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7f2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7f2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7f2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4c718bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4c718ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4c71708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4c6e1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4c6e1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7f2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7f2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7f2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4c6e1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (7747 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f9b05deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f9b05ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f9b05e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62b6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62b6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62b6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62b6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9aff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f9aff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f9afd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f9ac87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f9ac87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62b6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62b6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62b6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9ac87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (7748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563136deeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563136debe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563136def62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe082249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0822a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe082249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe082231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563136d84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563136d84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563136d698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563136a18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563136a18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe082232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0822330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0822330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563136a18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (7750 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/13581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a9f7f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a9f7f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a9f7f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81c7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81c738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81c7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81c731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a9f78cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a9f78ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a9f7718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a9f420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a9f420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81c731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81c731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81c731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a9f420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (7753 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba2f9d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba2f9cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba2f9d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f053521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05352725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f053521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0535203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba2f966bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba2f966a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba2f94b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba2f5fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba2f5fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0535204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05352050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05352050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba2f5faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (7756 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d226f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d226eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d226f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f296f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f296f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f296f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f296f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d22687bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d22687a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d2266c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d2231be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d2231bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f296f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f296f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f296f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d2231ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (7757 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f98dabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f98da8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f98dac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca53b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca53b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca53b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca53b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f98d41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f98d41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f98d268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f989d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f989d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca53b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca53b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca53b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f989d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (7759 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558228a9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558228a9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558228aa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a4bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a4bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a4bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a4bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558228a35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558228a35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558228a1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582286c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582286c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a4bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a4bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a4bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582286c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (7760 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583d1644eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583d1641e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583d164562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a40733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a4078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a40733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a4071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583d15dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583d15daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583d15bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583d126ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583d126eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a4071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a4071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a4071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583d126ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (7761 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cc2fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cc2fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cc2fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3715249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37152a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3715249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3715231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cc2f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cc2f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cc2f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cc2c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cc2c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3715232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37152330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37152330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cc2c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (7762 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/33772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f169731eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f16972ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f16973262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c82849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c828a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c82849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c82831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1696c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1696c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1696ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f16935be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f16935bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c82832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c828330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c828330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f16935ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (7763 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc26463eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc26460e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc2646462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f776bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f776bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f776bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f776bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc263f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc263f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc263de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc2608de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc2608db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f776bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f776bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f776bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc2608da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (7764 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.ris
# | ...
# `---data was truncated (10240/18562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd9c443eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd9c440e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd9c44462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd9c3d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd9c3d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd9c3be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd9c06de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd9c06db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fe631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd9c06da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (7766 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6aba4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6aba4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6aba4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2a6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2a62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2a6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2a6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6ab9e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6ab9e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6ab9c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6ab678e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6ab678b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2a6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2a62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2a62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6ab678a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (7767 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d62bcd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d62bcd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d62bcd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff390449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff390449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff390431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d62bc6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d62bc6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d62bc538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d62b902e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d62b902b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff390432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3904330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d62b902a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (7768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556571d82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556571d7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556571d8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556571d18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556571d18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556571cfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565719ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565719acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565719aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (7769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599cb4c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599cb4c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599cb4c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd055733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd05578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd055733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd05571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599cb459bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599cb459a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599cb43e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599cb0ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599cb0edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd05571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd05571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd05571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599cb0eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (7771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee9aea3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee9aea0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee9aea462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2be133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2be18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2be133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2be11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee9ae39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee9ae39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee9ae1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee9aacde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee9aacdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2be11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2be11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2be11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee9aacda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (7772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5d830deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5d830ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5d830e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5d82a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5d82a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5d82888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5d7f37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5d7f37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e5e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5d7f37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (7774 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 
# | ...
# `---data was truncated (10240/21465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d2b3e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d2b3e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d2b3e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaa2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaa2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaa2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaa2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d2b37bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d2b37ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d2b3608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d2b00fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d2b00fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaa2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaa2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaa2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d2b00fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (7776 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/18925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee001afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee001ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee001b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3742505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f374255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3742505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37424ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee00145bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee00145a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee0012a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edffdd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edffdd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37424eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37424ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37424ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edffdd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (7779 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608d55dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608d55d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608d55dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1695c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1695c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1695c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1695c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d5572bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608d5572a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608d55578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608d5206e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608d5206b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1695c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1695c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1695c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d5206a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (7780 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2
# | ...
# `---data was truncated (10240/32198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056100dc49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056100dc46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056100dc4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa37e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa37e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa37e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa37e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100dbdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056100dbdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056100dbc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056100d873e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056100d873b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa37e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa37e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa37e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056100d873a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (7785 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f09a7b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f09a7b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f09a7b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45d7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f09a749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f09a749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f09a72e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f09a3dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f09a3ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45d74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f09a3dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (7787 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a90b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a90b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a90b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd6aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd6aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd6aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd6aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a90ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a90ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a90ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a90775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a90775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd6aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd6aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd6aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a90775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (7788 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d08c5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d08c5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d08c5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c15849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c15849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c15831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d08bf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d08bf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d08bd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d08887e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d08887b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c15832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c158330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d08887a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (7790 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/12648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055808ecd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055808ecd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055808ecd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff358f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff358f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff358f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff358f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055808ec6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055808ec6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055808ec508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055808e8ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055808e8ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff358f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff358f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff358f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055808e8ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (7791 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed4ea26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed4ea23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed4ea2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c82933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c82933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed4e9bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed4e9bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed4e9a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed4e650e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed4e650b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c8291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed4e650a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (7792 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double %0, i64 %1)
# |   
# | ...
# `---data was truncated (10240/30849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562682ac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562682abde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562682ac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f900fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f900fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f900fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f900fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562682a56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562682a56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562682a3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626826eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626826eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f900fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f900fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f900fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626826eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (7793 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4c5b53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4c5b50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4c5b5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff68e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff68e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff68e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff68e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4c5ae9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4c5ae9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4c5ace8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4c577de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4c577db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff68e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff68e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff68e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4c577da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (7795 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, 
# | ...
# `---data was truncated (10240/20307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f10606feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f10606ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f10607062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56bae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56bae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56bae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56bae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f106005bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f106005a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f105fea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f105c99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f105c99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56bae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56bae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56bae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f105c99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (7797 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560606b92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560606b8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560606b9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d81d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d81d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d81d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d81d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560606b28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560606b28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560606b0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606067bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606067bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d81d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d81d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d81d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606067bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (7799 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621ff338eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621ff335e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621ff33962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8abca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8abca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8abca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8abca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621ff2cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621ff2cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621ff2b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621fef62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621fef62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8abca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8abca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8abca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621fef62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (7803 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bee9d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bee9d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bee9d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5b9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5b9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5b9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5b9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bee96cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bee96ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bee9518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bee600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bee600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5b9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5b9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5b9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bee600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (7804 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfb9823eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfb9820e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfb982462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92b7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfb97b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfb97b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfb979e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfb944de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfb944db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92b7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfb944da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (7805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a0d433eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a0d430e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a0d43462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6238133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f623818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6238133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f623811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a0d3c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a0d3c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a0d3ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a0d05de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a0d05db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f623811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f623811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f623811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a0d05da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (7806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e2f99feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e2f99ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e2f9a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd24649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd24649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd24631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e2f935bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e2f935a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e2f91a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e2f5c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e2f5c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd24632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd246330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e2f5c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (7807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de25e81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de25e7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de25e8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef42a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef42a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef42a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef42a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de25e17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de25e17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de25dfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de25aabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de25aabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef42a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef42a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef42a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de25aaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (7808 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv
# | ...
# `---data was truncated (10240/20082) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc8625eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc8625be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc8625f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70d3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70d3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70d3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70d3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc861f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc861f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc861d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc85e88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc85e88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70d3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70d3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70d3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc85e88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (7809 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b85dcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b85dcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b85dce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a12e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a12ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a12e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a12e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b85d63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b85d63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b85d488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b859f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b859f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a12e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a12e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a12e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b859f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (7810 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b59045beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b590458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b59045c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc84f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc84f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc84f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc84f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5903f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5903f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5903d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b590085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b590085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc84f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc84f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc84f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b590085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (7812 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_v
# | ...
# `---data was truncated (10240/29273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d806c46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d806c43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d806c4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f311de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f311de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f311de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f311de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d806bdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d806bdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d806bc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d806870e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d806870b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f311de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f311de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f311de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d806870a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (7814 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c43b9aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c43b9a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c43b9ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7767533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f776758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7767533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f776751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c43b942bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c43b942a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c43b9278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c43b5d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c43b5d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f776751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f776751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f776751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c43b5d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (7815 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a9cdcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a9cdcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a9cdce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f670fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f670fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f670fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f670fc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a9cd63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a9cd63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a9cd488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a9c9f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a9c9f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f670fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f670fc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f670fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a9c9f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (7817 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594d5dd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594d5dd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594d5dd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4c0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4c0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4c0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4c0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594d5d6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594d5d6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594d5d518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594d5a00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594d5a00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4c0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4c0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4c0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594d5a00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (7818 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558465b69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558465b66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558465b6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feda7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feda7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feda7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feda7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558465affbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558465affa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558465ae48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558465793e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558465793b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feda7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feda7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feda7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558465793a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (7820 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/34589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056348861ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563488619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056348861d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb242649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb242649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb242631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634885b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634885b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634885978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563488246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563488246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb242632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2426330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563488246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (7822 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae10d84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae10d81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae10d8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe976f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe976f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe976f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe976f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae10d1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae10d1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae10cff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae109aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae109aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe976f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe976f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe976f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae109aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (7824 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/39586) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c293ab7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c293ab4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c293ab862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0214b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0214b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0214b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0214b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c293a4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c293a4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c293a328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2936e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2936e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0214b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0214b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0214b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2936e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (7825 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4bfab2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4bfaafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4bfab362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c44133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c4418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c44133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c4411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4bfa48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4bfa48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4bfa2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4bf6dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4bf6dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c4411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c4411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c4411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4bf6dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (7829 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577043c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577043c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577043c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c38f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c38f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c38f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c38f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055770435abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055770435aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055770433f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557703feee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557703feeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c38f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c38f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c38f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557703feea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (7830 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b867beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632b8678e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632b867c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25ef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25ef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25ef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25ef91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b8611bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632b8611a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632b85f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632b82a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632b82a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25ef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25ef91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25ef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b82a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (7831 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8a35e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8a35dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8a35e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaa4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaa44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaa4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaa4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8a3578bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8a3578a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8a355d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8a320ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8a320cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffaa4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaa44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaa44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8a320ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (7832 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645d199deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645d199ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645d199e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf12831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645d1933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645d1933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645d19188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645d15c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645d15c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf128330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645d15c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (7834 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a20cbb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a20cbafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a20cbb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda4b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda4b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda4b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda4b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a20cb48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a20cb48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a20cb2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a20c7dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a20c7dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda4b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda4b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda4b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a20c7dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (7835 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625f490eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625f490be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625f490f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7982c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7982ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7982c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7982c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625f48a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625f48a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625f48898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625f4538e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625f4538b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7982c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7982c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7982c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625f4538a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (7838 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/26756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599f1cdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599f1cdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599f1cdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599f1c74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599f1c74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599f1c598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599f1908e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599f1908b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599f1908a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (7839 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605af24ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605af249e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605af24d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ee7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ee7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ee7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ee7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605af1e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605af1e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605af1c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605aee76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605aee76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ee7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ee7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ee7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605aee76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (7840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558488b5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558488b5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558488b5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dd241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dd24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dd241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dd2403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558488af3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558488af3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558488ad88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558488787e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558488787b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1dd2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dd24050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dd24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558488787a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (7841 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c999cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c999cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c999ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd503333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd50338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd503333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd50331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c99963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c99963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c999488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c995f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c995f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd50331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd50331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd50331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c995f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (7842 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c365fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c365f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c365fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2179249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21792a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2179249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2179231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c36591bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c36591a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c365768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c36225e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c36225b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2179232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21792330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21792330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c36225a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (7844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cf90f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cf90eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cf90f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa851733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa85178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa851733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa85171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cf9087bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cf9087a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cf906c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cf8d1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cf8d1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa85171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa85171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa85171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cf8d1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (7847 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584f2e59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584f2e56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584f2e5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7e7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7e70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7e7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7e7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f2defbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584f2defa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584f2dd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584f2a83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584f2a83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7e7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7e70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7e70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584f2a83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (7848 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd7ad7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd7ad7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd7ad7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8880933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f888098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8880933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f888091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd7ad13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd7ad13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd7acf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd7a9a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd7a9a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f888091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f888091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f888091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd7a9a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (7850 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f93aceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f93acbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f93acf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b1081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b108725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b1081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b10803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f93a64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f93a64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f93a498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f936f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f936f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b10804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b108050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b108050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f936f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (7851 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563003511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056300350ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056300351262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1012e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1012ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1012e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1012e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630034a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630034a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056300348c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056300313be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056300313bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1012e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1012e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1012e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056300313ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (7852 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c7c127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c7c124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c7c12862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2b7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2b74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2b7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2b7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c7c0bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c7c0bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c7c0a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c7bd51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c7bd51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2b7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2b74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2b74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c7bd51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (7854 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba27640eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba2763de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba2764162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f383d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f383d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f383d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f383d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba275d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba275d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba275bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba2726ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba2726ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f383d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f383d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f383d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba2726aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (7855 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e3a898eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e3a895e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e3a89962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee4d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee4d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee4d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee4d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e3a82ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e3a82ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e3a8138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e3a4c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e3a4c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee4d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee4d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee4d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e3a4c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (7856 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056283ee9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056283ee9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056283ee9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38f3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38f3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38f3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38f3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056283ee34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056283ee34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056283ee198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056283eac8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056283eac8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38f3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38f3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38f3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056283eac8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (7857 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056236f41ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056236f419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056236f41d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d22333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d2238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d22333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d2231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056236f3b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056236f3b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056236f3978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056236f046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056236f046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d2231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d2231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d2231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056236f046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (7858 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a990c1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a990c17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a990c1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52cee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52cee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52cee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52cee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a990bb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a990bb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a990b958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a990844e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a990844b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52cee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52cee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52cee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a990844a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (7860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64 immar
# | ...
# `---data was truncated (10240/14780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561299d43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561299d40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561299d4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0da1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0da118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0da1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0da111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561299cd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561299cd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561299cbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056129996de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056129996db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0da111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0da111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0da111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056129996da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (7861 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d60ca84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d60ca81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d60ca8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f999a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f999a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f999a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f999a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d60ca1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d60ca1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d60c9ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d60c6aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d60c6aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f999a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f999a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f999a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d60c6aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (7862 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa1c281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa1c27ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa1c28262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a16b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a16b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a16b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a16b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa1c217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa1c217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa1c1fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa1beabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa1beabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a16b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a16b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a16b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa1beaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (7863 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5c084aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5c0847e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5c084b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3815933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f381598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3815933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f381591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5c07e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5c07e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5c07c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5c0474e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5c0474b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f381591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f381591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f381591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5c0474a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (7864 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556077b33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556077b30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556077b3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ed5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ed558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ed5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ed551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556077ac9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556077ac9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556077aae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055607775de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055607775db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ed551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ed551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ed551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055607775da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (7865 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f400557eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f400554e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f40055862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabbc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabbc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabbc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabbc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4004edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4004eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4004d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f400181e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f400181b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabbc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabbc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabbc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f400181a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (7866 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cbbce3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cbbce0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cbbce462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8b4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8b4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8b4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8b4aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cbbc79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cbbc79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cbbc5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cbb90de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cbb90db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8b4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8b4aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8b4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cbb90da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (7867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558738beceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558738be9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558738bed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfd2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfd238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfd2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfd231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558738b82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558738b82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558738b678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558738816e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558738816b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfd231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfd231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfd231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558738816a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (7868 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb07b70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb07b6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb07b7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f2cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f2cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f2cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f2cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb07b06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb07b06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb07aeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb0779ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb0779ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f2cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f2cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f2cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb0779aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (7870 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563926494eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563926491e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056392649562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effadb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effadb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effadb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effadb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056392642abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056392642aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056392640f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639260bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639260beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effadb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effadb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effadb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639260bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (7875 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604eba70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604eba6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604eba7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65be049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65be0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65be049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65be031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604eba06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604eba06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604eb9eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604eb69ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604eb69ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65be032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65be0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65be0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604eb69aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (7876 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625ddd47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625ddd44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625ddd4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ff6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ff62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ff6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ff6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625ddcddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625ddcdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625ddcc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625dd971e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625dd971b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ff6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ff62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ff62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625dd971a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (7877 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d647a61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d647a5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d647a6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe054449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0544a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe054449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe054431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6479f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6479f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6479dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d64768be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d64768bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe054432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0544330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0544330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d64768ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (7878 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b839775eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b839772e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b83977662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97f4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97f40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97f4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97f4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b83970bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b83970ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8396f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b83939fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b83939fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97f4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97f40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97f40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b83939fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (7879 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @ll
# | ...
# `---data was truncated (10240/20090) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7e459eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7e459be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7e459f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3f871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7e4534bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7e4534a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7e45198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7e41c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7e41c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3f871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7e41c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (7880 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/20131) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559805986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559805983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055980598762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa17d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa17d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa17d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa17d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055980591cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055980591ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598059018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598055b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598055b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa17d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa17d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa17d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598055b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (7881 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vs
# | ...
# `---data was truncated (10240/23775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d04fe2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d04fe2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d04fe2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9f5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9f5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9f5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9f5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d04fdc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d04fdc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d04fda98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d04fa58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d04fa58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9f5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9f5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9f5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d04fa58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (7883 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b0e92beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b0e928e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b0e92c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc67ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc67ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc67ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc67ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b0e8c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b0e8c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b0e8a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b0e555e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b0e555b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc67ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc67ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc67ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b0e555a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (7886 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578260dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578260d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578260dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557826072bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557826072a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578260578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557825d06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557825d06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557825d06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (7887 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0e12aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0e12a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0e12ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7882d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7882d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7882d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7882ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0e1240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0e1240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0e12258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0e0ed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0e0ed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7882ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7882cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7882cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0e0ed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (7888 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616c1486eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616c1483e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616c148762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87a9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87a938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87a9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87a931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616c141cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616c141ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616c14018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616c10b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616c10b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87a931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87a931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87a931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616c10b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (7890 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale
# | ...
# `---data was truncated (10240/11640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055778179beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557781798e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055778179c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80a0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80a018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80a0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80a011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557781731bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557781731a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577817168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577813c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577813c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80a011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80a011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80a011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577813c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (7891 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644ce6f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644ce6f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644ce6f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ed0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ed0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ed0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ed0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644ce68ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644ce68ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644ce6738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644ce322e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644ce322b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ed0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ed0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ed0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644ce322a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (7892 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | 
# | ...
# `---data was truncated (10240/40891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7496cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7496c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7496cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d749661bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d749661a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7496468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7492f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7492f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cd7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7492f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (7893 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, a
# | ...
# `---data was truncated (10240/29450) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3e3694eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3e3691e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3e369562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc038449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc038449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc038431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3e362abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3e362aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3e360f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3e32bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3e32beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc038432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0384330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3e32bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (7894 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfde652eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfde64fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfde65362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff167533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff16758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff167533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff16751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfde5e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfde5e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfde5cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfde27ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfde27cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff16751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff16751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff16751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfde27ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (7896 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db11690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db1168de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db1169162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8a111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db11626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db11626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db1160b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db112bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db112bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8a111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db112baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (7897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600252aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600252a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600252ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1a291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560025240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560025240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600252258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560024ed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560024ed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1a291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560024ed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (7899 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561261764eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561261761e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056126176562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f632bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f632bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f632bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f632baed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612616fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612616faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612616df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056126138ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056126138eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f632baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f632baef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f632baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056126138ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (7901 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dce3b82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dce3b7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dce3b8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dfd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dfd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dfd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dfd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dce3b18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dce3b18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dce3afd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dce37ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dce37acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dfd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dfd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dfd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dce37aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (7907 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562380084eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562380081e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056238008562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc2f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc2f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc2f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc2f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056238001abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056238001aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056237ffff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056237fcaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056237fcaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc2f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc2f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc2f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056237fcaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (7909 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614ec88beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614ec888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614ec88c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e73a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614ec821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614ec821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614ec8068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614ec4b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614ec4b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e73a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614ec4b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (7910 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f56feeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f56febe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f56fef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f122d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f122d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f56f84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f56f84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f56f698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f56c18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f56c18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f122d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f56c18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (7911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db4eb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555db4eb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555db4eb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db4e49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555db4e49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555db4e2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555db4adde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555db4addb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95c1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db4adda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (7913 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c4f3d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c4f3cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c4f3d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dae31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c4f368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c4f368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c4f34d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c4effce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c4effcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dae31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c4effca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (7915 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dba8bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dba8bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dba8c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4110933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f411098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4110933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f411091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dba855bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dba855a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dba83a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dba4e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dba4e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f411091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f411091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f411091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dba4e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (7916 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560920cb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560920cb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560920cb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd36a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd36a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd36a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560920c4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560920c4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560920c2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609208dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609208deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd36a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd36a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd36a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609208dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (7918 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d636a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d636a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d636a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6369a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6369a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d63698b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d63663ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d63663ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cd3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d63663aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (7923 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2a70aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2a70a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2a70ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2a7040bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2a7040a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2a70258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2a6cd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2a6cd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efff2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2a6cd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (7924 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src, ptr %src.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %src.addr, align 8
# |   %1 = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)
# |   ret <vscale x 4 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, <vscale x 4 x i64> %val) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %val.addr = alloca <vscale x 4 x i64>, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, ptr %dest.addr, align 8
# |   store <vscale x 4 x i64> %val, ptr %val.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %dest.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %val.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, <vscale x 4 x i64> %1, i32 1)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), <vscale x 4 x i64>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fd0b63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fd0b60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fd0b6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa073449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa073449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa073431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fd0af9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fd0af9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fd0ade8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fd078de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fd078db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa073432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0734330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fd078da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (7925 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa80f60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa80f5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa80f6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c2f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c2f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c2f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c2f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa80ef6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa80ef6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa80edb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa80b8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa80b8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c2f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c2f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c2f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa80b8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (7926 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055722d24aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055722d247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055722d24b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1627649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16276a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1627649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1627631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055722d1e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055722d1e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055722d1c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055722ce74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055722ce74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1627632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16276330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16276330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055722ce74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (7927 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsca
# | ...
# `---data was truncated (10240/24214) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c6298aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c62987e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c6298b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc854c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc854c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc854c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc854c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c62920bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c62920a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c629058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c625b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c625b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc854c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc854c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc854c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c625b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (7928 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab19251eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab1924ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab1925262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c2f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab191e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab191e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab191cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab18e7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab18e7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab18e7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (7929 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64
# | ...
# `---data was truncated (10240/29175) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563416736eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563416733e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056341673762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc209249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc209249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc209231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634166ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634166cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634166b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563416360e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563416360b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc209232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563416360a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (7932 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555da82a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555da82a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555da82a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88b7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88b74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88b7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88b7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555da823cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555da823ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555da82218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555da7ed0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555da7ed0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88b7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88b74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88b74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555da7ed0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (7934 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555d9adfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555d9adce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555d9ae062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe3bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe3bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe3bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe3bced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555d9a75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555d9a75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555d9a5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555d9709e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555d9709b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe3bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe3bcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe3bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555d9709a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (7935 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.ad
# | ...
# `---data was truncated (10240/13903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560221e4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560221e47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560221e4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4d9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4d918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4d9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4d911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560221de0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560221de0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560221dc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560221a74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560221a74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4d911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4d911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4d911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560221a74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (7936 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563821f3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563821f39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563821f3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5120a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5120aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5120a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5120a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563821ed2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563821ed2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563821eb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563821b66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563821b66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5120a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5120a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5120a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563821b66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (7937 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8b9174eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8b9171e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8b917562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0890b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0890b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0890b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0890b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8b910abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8b910aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8b90ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8b8d9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8b8d9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0890b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0890b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0890b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8b8d9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (7938 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f305e0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f305e08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f305e0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f751bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f751bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f751bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f751bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f305da1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f305da1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f305d868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f305a35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f305a35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f751bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f751bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f751bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f305a35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (7939 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.
# | ...
# `---data was truncated (10240/18641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056161ebdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056161ebd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056161ebdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8209933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f820998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8209933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f820991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056161eb70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056161eb70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056161eb558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056161e804e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056161e804b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f820991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f820991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f820991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056161e804a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (7940 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560829131eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056082912ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056082913262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f615541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61554725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f615541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6155403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608290c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608290c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608290ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560828d5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560828d5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6155404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61554050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61554050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560828d5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (7941 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056524edf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056524edf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056524edf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf0b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf0b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf0b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf0b2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056524ed8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056524ed8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056524ed6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056524ea1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056524ea1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf0b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf0b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf0b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056524ea1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (7943 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b5fb81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b5fb7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b5fb8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa35f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa35f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa35f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa35f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b5fb17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b5fb17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b5fafc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b5f7abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b5f7abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa35f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa35f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa35f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b5f7aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (7944 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055accecf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055accecf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055accecf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d4f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055accec8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055accec8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055accec728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055acce921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055acce921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acce921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (7945 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2c3759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2c3756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2c375a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8584933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f858498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8584933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f858491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2c36efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2c36efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2c36d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2c3383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2c3383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f858491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f858491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f858491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2c3383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (7946 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b860b59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b860b56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b860b5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b860aefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b860aefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b860ad48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b860783e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b860783b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b860783a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (7947 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 
# | ...
# `---data was truncated (10240/12465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5f6637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5f6634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5f663862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1674733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f167478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1674733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f167471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5f65cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5f65cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5f65b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5f6261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5f6261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f167471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f167471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f167471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5f6261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (7949 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/12680) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7fd430eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7fd42de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7fd43162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effcd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effcd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effcd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effcd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7fd3c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7fd3c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7fd3ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7fd05ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7fd05ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effcd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effcd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effcd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7fd05aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (7950 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0cb078eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0cb075e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0cb07962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce99705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce9975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce99705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce996ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0cb00ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0cb00ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0caff38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0caca2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0caca2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce996eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce996ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce996ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0caca2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (7951 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3e4938eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3e4935e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3e493962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddc8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddc8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddc8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddc8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3e48cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3e48cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3e48b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3e4562e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3e4562b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddc8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddc8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddc8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3e4562a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (7952 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556615d1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556615d1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556615d1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6980649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6980649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6980631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556615cb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556615cb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556615c988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556615947e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556615947b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6980632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556615947a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (7955 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d1671aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d16717e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d1671b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7992133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f799218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7992133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f799211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d166b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d166b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d166958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d16344e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d16344b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f799211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f799211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f799211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d16344a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (7956 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7cc9b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7cc9b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7cc9b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ced933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ced98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ced933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ced91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7cc949bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7cc949a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7cc92e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7cc5dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7cc5ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ced91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ced91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ced91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7cc5dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (7957 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600eceeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600ecee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600eceeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3dcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3dcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3dcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3dcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600ece80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600ece80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600ece658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600ecb14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600ecb14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3dcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3dcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3dcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600ecb14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (7959 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd771beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfd7718e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfd771c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58f831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd76b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfd76b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfd76968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfd7345e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfd7345b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58f831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd7345a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (7961 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b93aa08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b93aa05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b93aa0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb570733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb57078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb570733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb57071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b93a99ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b93a99ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b93a9838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b93a632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b93a632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb57071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb57071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb57071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b93a632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (7962 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cfb554eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cfb551e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cfb55562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39db31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cfb4eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cfb4eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cfb4cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cfb17ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cfb17eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39db31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cfb17ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (7963 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fbd3f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fbd3f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fbd3f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26aef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26aef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26aef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26aef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbd38abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fbd38aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fbd36f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fbd01ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fbd01eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26aef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26aef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26aef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fbd01ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (7964 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae74f94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae74f91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae74f9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a6be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a6bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a6be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a6be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae74f2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae74f2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae74f0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae74bbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae74bbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a6be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a6be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a6be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae74bbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (7965 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cca0b35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cca0b32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cca0b3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5d7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cca0acbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cca0acba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cca0ab08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cca075fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cca075fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5d78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cca075fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (7966 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee5dfe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee5dfe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee5dfe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60fb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60fb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60fb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60fb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee5df7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee5df7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee5df618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee5dc10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee5dc10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60fb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60fb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60fb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee5dc10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (7967 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca43afdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca43afae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca43afe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2736849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27368a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2736849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2736831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca43a93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca43a93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca43a788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca43727e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca43727b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2736832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27368330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27368330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca43727a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (7968 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056416fd27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056416fd24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056416fd2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb50649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb506a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb50649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb50631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056416fcbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056416fcbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056416fca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056416f951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056416f951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb50632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb506330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb506330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056416f951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (7974 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c118cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c118c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c118cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facf8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facf8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facf8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facf8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c11862bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c11862a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c118478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c114f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c114f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facf8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facf8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facf8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c114f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (7976 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056093652ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560936529e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056093652d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f581b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f581b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f581b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f581b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609364c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609364c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609364a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560936156e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560936156b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f581b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f581b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f581b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560936156a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (7977 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdbeaefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdbeaece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdbeaf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8f1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8f178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8f1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8f171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdbea85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdbea85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdbea6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdbe719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdbe719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8f171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8f171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8f171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdbe719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (7979 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc2bac1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc2babee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc2bac262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f573ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f573aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f573ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f573ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2ba57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc2ba57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc2ba3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc2b6ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc2b6ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f573ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f573ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f573ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc2b6eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (7980 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c90786eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c90783e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c9078762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa162049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1620a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa162049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa162031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9071cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c9071ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c907018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c903b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c903b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa162032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1620330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1620330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c903b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (7981 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4c05dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4c05dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4c05e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a52c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a52ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a52c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a52c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4c0575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4c0575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4c055a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4c0209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4c0209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a52c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a52c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a52c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4c0209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (7982 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efd52e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efd52e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efd52e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac00133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac0018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac00133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac0011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efd527ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efd527ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efd52638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efd4f12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efd4f12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac0011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac0011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac0011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efd4f12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (7983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d17cd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d17cd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d17cd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0be133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0be18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0be133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0be11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d17c6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d17c6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d17c538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d17902e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d17902b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0be11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0be11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0be11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d17902a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (7985 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | ...
# `---data was truncated (10240/12958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563f682deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563f682ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563f682e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4628b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4628b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4628b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4628b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563f67c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563f67c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563f67a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563f6457e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563f6457b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4628b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4628b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4628b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563f6457a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (7989 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056510753beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565107538e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056510753c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4bcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651074d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651074d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651074b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565107165e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565107165b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565107165a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (7990 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e536cb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e536cb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e536cb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91e151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e536c4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e536c4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e536c2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5368dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5368deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91e151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5368dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (7991 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca56d41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca56d3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca56d4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14f9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14f9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14f9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14f9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca56cd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca56cd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca56cbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca5696be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca5696bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14f9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14f9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14f9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca5696ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (7993 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e435e19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e435e16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e435e1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb176049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb176049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb176031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e435dafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e435dafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e435d948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e435a43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e435a43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb176032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1760330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e435a43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (7994 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590cc764eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590cc761e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590cc76562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff044b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff044b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff044b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff044b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590cc6fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590cc6faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590cc6df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590cc38ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590cc38eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff044b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff044b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff044b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590cc38ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (7997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vsca
# | ...
# `---data was truncated (10240/14360) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b00822ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b008229e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b00822d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6953533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f695358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6953533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f695351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0081c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0081c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0081a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b007e56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b007e56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f695351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f695351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f695351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b007e56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (7998 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc8f68beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc8f688e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc8f68c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7788133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f778818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7788133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f778811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc8f621bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc8f621a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc8f6068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc8f2b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc8f2b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f778811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f778811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f778811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc8f2b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (8000 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc897d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc897d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc897da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea83f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea83f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea83f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea83eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc8976fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc8976fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc897548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc89403e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc89403b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea83eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea83eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea83eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc89403a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (8001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055843efe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055843efe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055843efe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0ead05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0ead5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0ead05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0eaced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055843ef7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055843ef7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055843ef608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055843ec0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055843ec0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0eaceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0eacef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0eacef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055843ec0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (8002 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nx
# | ...
# `---data was truncated (10240/25567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578327c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578327bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578327c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3373f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3373f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3373f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3373f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557832757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557832757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055783273c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578323ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578323ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3373f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3373f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3373f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578323eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (8003 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c187034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c187031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c18703562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe25049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe25049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe25031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c186fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c186fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c186faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c186c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c186c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe25032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe250330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c186c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (8004 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557cb1e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557cb1e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557cb1e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36eef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36eef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36eef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36eef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557cb17cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557cb17ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557cb1618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557cae10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557cae10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36eef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36eef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36eef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557cae10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (8007 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb40d82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb40d7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb40d8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb931249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9312a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb931249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb931231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb40d18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb40d18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb40cfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb409ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb409acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb931232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9312330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9312330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb409aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (8008 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056464b093eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056464b090e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056464b09462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d3d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d3d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d3d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d3d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056464b029bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056464b029a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056464b00e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056464acbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056464acbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d3d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d3d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d3d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056464acbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (8009 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5f9502eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5f94ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5f950362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5f9498bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5f9498a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5f947d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5f912ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5f912cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5f912ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (8010 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056467406aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564674067e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056467406b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc97b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc97b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc97b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc97b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564674000bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564674000a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564673fe58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564673c94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564673c94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc97b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc97b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc97b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564673c94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (8011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561857530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056185752de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056185753162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64e6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64e698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64e6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64e691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618574c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618574c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618574ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056185715ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056185715ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64e691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64e691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64e691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056185715aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (8012 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055879fce9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055879fce6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055879fcea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd276333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd27638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd276333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd27631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055879fc7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055879fc7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055879fc648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055879f913e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055879f913b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd27631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd27631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd27631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055879f913a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (8014 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr 
# | ...
# `---data was truncated (10240/26240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30c42ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c30c429e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c30c42d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6573b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6573b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6573b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6573b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c30c3c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c30c3c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c30c3a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c30c056e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c30c056b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6573b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6573b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6573b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c30c056a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (8015 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1d0d7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1d0d79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1d0d7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60a8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60a878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60a8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60a871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1d0d12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1d0d12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1d0cf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1d09a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1d09a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60a871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60a871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60a871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1d09a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (8020 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd8f62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfd8f5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfd8f6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3dd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd8ef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfd8ef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfd8edd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfd8b8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfd8b8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd8b8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (8022 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651c3bb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651c3bb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651c3bba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd85ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd85ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651c3b4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651c3b4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651c3b348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651c37e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651c37e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd85ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651c37e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (8023 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e66c11aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e66c117e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e66c11b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d53c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d53ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d53c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d53c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e66c0b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e66c0b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e66c0958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e66bd44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e66bd44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d53c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d53c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d53c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e66bd44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (8025 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac5174beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac51748e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac5174c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac516e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac516e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac516c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac51375e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac51375b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6b8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac51375a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (8027 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e3ca1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e3ca17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e3ca1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f416a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f416a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f416a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f416a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e3c9b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e3c9b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e3c9958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e3c644e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e3c644b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f416a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f416a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f416a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e3c644a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (8028 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,102
# | ...
# `---data was truncated (10240/10769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a4fcaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a4fca7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a4fcab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f721d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f721d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f721d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f721d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a4fc40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a4fc40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a4fc258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a4f8d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a4f8d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f721d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f721d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f721d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a4f8d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (8029 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f7e49aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f7e497e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f7e49b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a2931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f7e430bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f7e430a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f7e4158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f7e0c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f7e0c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a2931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f7e0c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (8030 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/32694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558729c7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558729c77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558729c7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcece31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558729c10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558729c10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558729bf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587298a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587298a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcece330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587298a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (8032 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/11958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6db558eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6db555e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6db55962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1221733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1221733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6db4eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6db4eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6db4d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6db182e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6db182b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f122171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6db182a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (8035 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558283f28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558283f25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558283f2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b29905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b2995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b29905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b298ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558283ebebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558283ebea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558283ea38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558283b52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558283b52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b298eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b298ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b298ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558283b52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (8038 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4102d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4102d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4102d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1da9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1da90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1da9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1da9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f41026bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f41026ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4102508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f40feffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f40feffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1da9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1da90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1da90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f40feffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (8039 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adeaf06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055adeaf03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055adeaf0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b6a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b6a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adeae9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055adeae9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055adeae818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055adeab30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055adeab30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b6a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adeab30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (8040 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e024b83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e024b80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e024b8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86c7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86c7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86c7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86c7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e024b19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e024b19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e024afe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0247ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0247adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86c7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86c7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86c7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0247ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (8043 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6cbfd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6cbfd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6cbfd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7f0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7f0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7f0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7f0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6cbf69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6cbf69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6cbf4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6cbbfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6cbbfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7f0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7f0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7f0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6cbbfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (8045 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0d5bd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0d5bcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0d5bd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0d7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0d7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0d7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0d7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0d5b67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0d5b67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0d5b4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0d57fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0d57fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0d7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0d7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0d7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0d57fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (8046 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eee45c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eee45c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eee45c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff628249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6282a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff628249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff628231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eee455dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eee455da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eee45428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eee41f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eee41f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff628232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6282330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6282330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eee41f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (8047 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ba3069eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ba3066e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ba306a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4c8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4c8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4c8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4c8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ba2fffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ba2fffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ba2fe48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ba2c93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ba2c93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4c8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4c8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4c8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ba2c93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (8048 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/18691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9f8191eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9f818ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9f819262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd77e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd77ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd77e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd77e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f8127bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9f8127a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9f810c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9f7dbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9f7dbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd77e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd77e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd77e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f7dbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (8049 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594be872eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594be86fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594be87362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f420041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42004725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f420041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4200403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594be808bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594be808a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594be7ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594be49ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594be49cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4200404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42004050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42004050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594be49ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (8050 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f610bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f610bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f610bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f732b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f732b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f732b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f732b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f610b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f610b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f610b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6107e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6107e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f732b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f732b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f732b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6107e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (8052 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a66bb4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a66bb47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a66bb4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae4c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae4c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae4c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae4c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a66bae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a66bae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a66bac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a66b774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a66b774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae4c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae4c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae4c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a66b774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (8053 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple,
# | ...
# `---data was truncated (10240/27986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635ebfbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635ebfbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635ebfbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efede61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efede6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efede61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efede603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635ebf53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635ebf53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635ebf388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635ebbe7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635ebbe7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efede604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efede6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efede6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635ebbe7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (8054 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056078a1d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056078a1d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056078a1d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21d3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21d3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21d3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21d3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056078a16cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056078a16ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056078a1518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560789e00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560789e00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21d3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21d3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21d3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560789e00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (8058 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f015e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f015e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f015e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd491e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd491e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd491e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd491e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f0157ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f0157ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f015638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f01212e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f01212b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd491e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd491e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd491e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f01212a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (8060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2079a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e20799de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2079a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58b7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e207936bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e207936a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e20791b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2075cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2075cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58b78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2075caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (8065 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b835ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b835eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b835ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f3741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f374725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f3741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f37403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b835e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b835e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b835e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b835ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b835ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f37404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f374050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f374050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b835ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (8066 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056092c32deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056092c32ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056092c32e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa2dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa2dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa2dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa2dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056092c2c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056092c2c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056092c2a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056092bf57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056092bf57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa2dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa2dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa2dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056092bf57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (8067 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load 
# | ...
# `---data was truncated (10240/29128) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6822a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a68229ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6822a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4121049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41210a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4121049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4121031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a682237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a682237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a68221c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a681ecbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a681ecbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4121032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41210330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41210330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a681ecba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (8068 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd0a76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfd0a73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfd0a7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb7d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb7d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb7d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb7d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd0a0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfd0a0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfd09f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfd06a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfd06a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb7d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb7d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb7d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd06a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (8069 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558799479eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558799476e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055879947a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6859b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6859b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6859b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6859b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055879940fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055879940fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587993f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587990a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587990a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6859b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6859b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6859b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587990a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (8071 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e245f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e245eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e245f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fbaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fbaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fbaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fbaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e24587bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e24587a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e2456c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e2421be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e2421bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fbaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fbaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fbaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e2421ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (8072 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bcc358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bcc355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bcc35962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f151bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f151bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f151bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f151bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bcc2eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bcc2eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bcc2d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bcbf82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bcbf82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f151bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f151bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f151bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bcbf82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (8073 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocall
# | ...
# `---data was truncated (10240/12425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056079f51aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056079f517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056079f51b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb56133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb5618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb56133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb5611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056079f4b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056079f4b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056079f4958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056079f144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056079f144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb5611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb5611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb5611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056079f144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (8075 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cd3ae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cd3ae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cd3ae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dbdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dbdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dbdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dbdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cd3a7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cd3a7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cd3a618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cd3710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cd3710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dbdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dbdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dbdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cd3710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (8077 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559631b77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559631b74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559631b7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8146449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8146449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8146431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559631b0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559631b0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559631af28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596317a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596317a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8146432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81464330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596317a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (8078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558152f53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558152f50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558152f5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f729f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f729f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f729f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f729f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558152ee9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558152ee9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558152ece8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558152b7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558152b7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f729f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f729f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f729f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558152b7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (8080 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563989095eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563989092e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056398909662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6cc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6cc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6cc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6cc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056398902bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056398902ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639890108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563988cbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563988cbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6cc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6cc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6cc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563988cbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (8081 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f8a0beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f8a0bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f8a0bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda09649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda096a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda09649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda09631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f8a054bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f8a054a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f8a0398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f89ce8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f89ce8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda09632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda096330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda096330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f89ce8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (8082 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f8fe31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f8fe2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f8fe3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99f5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99f518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99f5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99f511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f8fdc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f8fdc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f8fdac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f8fa5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f8fa5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99f511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99f511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99f511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f8fa5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (8083 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrga
# | ...
# `---data was truncated (10240/28435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561477b4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561477b4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561477b4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff77ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff77ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561477ae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561477ae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561477ac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561477778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561477778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff77ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561477778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (8084 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649fa1eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649fa1e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649fa1eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6304933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f630498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6304933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f630491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649fa180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649fa180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649fa1658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649f9e14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649f9e14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f630491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f630491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f630491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649f9e14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (8086 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d9cc0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9cc0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9cc0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72d9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72d9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72d9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72d9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d9cba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d9cba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d9cb888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d9c837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d9c837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72d9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72d9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72d9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d9c837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (8088 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/12431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f2cb9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f2cb9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f2cba062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f79c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f79c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f79c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f79c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f2cb35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f2cb35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f2cb1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f2c7c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f2c7c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f79c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f79c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f79c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f2c7c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (8089 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.
# | ...
# `---data was truncated (10240/30759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b31a2bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b31a2b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b31a2bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01ed449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01ed4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01ed449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01ed431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b31a251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b31a251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b31a2368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b319ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b319ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01ed432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01ed4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01ed4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b319ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (8090 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616c8caceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616c8ca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616c8cad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0743c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0743ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0743c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0743c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616c8c42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616c8c42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616c8c278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616c88d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616c88d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0743c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0743c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0743c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616c88d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (8091 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/10610) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f109d78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f109d75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f109d7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faec781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faec78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faec781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faec7803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f109d0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f109d0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f109cf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1099a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1099a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faec7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faec78050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faec78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1099a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (8092 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f955821eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f95581ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f95582262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f398ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f398ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f398ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f398ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9557b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9557b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f95579c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f95544be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f95544bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f398ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f398ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f398ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f95544ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (8093 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed36178eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed36175e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed3617962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9eba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9ebaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9eba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9eba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed3610ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed3610ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed360f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed35da2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed35da2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9eba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9eba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9eba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed35da2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (8094 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/31876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578a0d17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578a0d14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578a0d1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15efb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578a0cadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578a0cada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578a0c928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578a0941e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578a0941b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578a0941a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (8096 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/26984) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9fdc26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9fdc23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9fdc2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dc5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dc5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dc5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dc5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9fdbbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9fdbbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9fdba18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9fd850e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9fd850b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dc5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dc5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dc5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9fd850a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (8097 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd69ee2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd69edfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd69ee362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe750249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7502a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe750249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe750231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd69e78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd69e78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd69e5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd69b0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd69b0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe750232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7502330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7502330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd69b0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (8098 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9c7152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9c714fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9c715362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96dd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9c70e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9c70e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9c70cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9c6d7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9c6d7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9c6d7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (8101 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576d820deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576d820ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576d820e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2e881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2e88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2e881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2e8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576d81a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576d81a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576d81888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576d7e37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576d7e37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2e8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2e88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2e88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576d7e37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (8102 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |  
# | ...
# `---data was truncated (10240/22074) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056408f699eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056408f696e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056408f69a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77ece1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77ece725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77ece1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77ece03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056408f62fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056408f62fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056408f6148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056408f2c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056408f2c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77ece04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77ece050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77ece050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056408f2c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (8103 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f175bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f175b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f175bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33dc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33dc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33dc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33dc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f17552bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f17552a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f175378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f171e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f171e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33dc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33dc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33dc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f171e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (8107 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556df3ae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556df3ae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556df3ae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa974f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa974f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa974f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa974eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556df3a79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556df3a79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556df3a5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556df370de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556df370db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa974eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa974eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa974eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556df370da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (8108 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563496b4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563496b4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563496b5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc21a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc21a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc21a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc21a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563496ae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563496ae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563496aca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563496779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563496779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc21a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc21a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc21a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563496779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (8109 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cc8542eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cc853fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cc854362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc479933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc47998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc479933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc47991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cc84d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cc84d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cc84bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cc816ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cc816cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc47991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc47991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc47991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cc816ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (8110 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double
# | ...
# `---data was truncated (10240/29119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9e1fd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9e1fd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9e1fd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f144ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f144cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f144ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f144ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9e1f6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9e1f6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9e1f528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9e1c01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9e1c01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f144ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f144ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f144ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9e1c01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (8111 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b59805eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b59805be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b59805f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a41f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a41f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a41f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a41f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b597ff4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b597ff4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b597fd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b597c88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b597c88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a41f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a41f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a41f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b597c88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (8112 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c6d3bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c6d3b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c6d3bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f215d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f215d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f215d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f215d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c6d352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c6d352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c6d3378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c6cfe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c6cfe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f215d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f215d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f215d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c6cfe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (8114 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055955d03aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055955d037e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055955d03b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055955cfd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055955cfd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055955cfb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055955cc64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055955cc64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055955cc64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (8115 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650658c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650658bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650658c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06f8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565065857bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565065857a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056506583c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650654ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650654ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06f86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650654eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (8116 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e2feb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e2feb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e2feb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe53101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5310725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe53101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe531003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e2fe4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e2fe4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e2fe328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e2fae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e2fae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe531004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5310050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5310050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e2fae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (8117 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c74f02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c74effe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c74f0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8792c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8792ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8792c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8792c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c74e98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c74e98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c74e7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c74b2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c74b2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8792c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8792c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8792c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c74b2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (8118 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdecf73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdecf70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdecf7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0984e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0984ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0984e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0984e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdecf09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdecf09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdeceee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdecb9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdecb9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0984e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0984e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0984e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdecb9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (8119 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c528071eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c52806ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c52807262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f973d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f973d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f973d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f973d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c528007bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c528007a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c527fec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c527c9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c527c9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f973d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f973d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f973d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c527c9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (8120 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557223c22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557223c1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557223c2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6db733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6db78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6db733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6db71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557223bb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557223bb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557223b9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055722384ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055722384cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6db71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6db71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6db71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055722384ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (8121 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055817ece0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055817ecdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055817ece162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4ec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4ec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4ec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4ec11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055817ec76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055817ec76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055817ec5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055817e90ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055817e90ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4ec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4ec11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4ec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055817e90aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (8124 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e034b3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e034b38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e034b3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dd2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dd258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dd2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dd251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e034ad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e034ad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e034ab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e034765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e034765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dd251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dd251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dd251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e034765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (8125 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce454a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce454a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce454aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cb2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cb298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cb2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cb291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce4543fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce4543fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce454248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce450d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce450d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cb291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cb291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cb291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce450d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (8126 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577d4b87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577d4b84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577d4b8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7499a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7499aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7499a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7499a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577d4b1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577d4b1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577d4b028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577d47b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577d47b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7499a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7499a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7499a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577d47b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (8130 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599ebc9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599ebc98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599ebc9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe30c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe30c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe30c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe30c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599ebc31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599ebc31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599ebc168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599eb8c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599eb8c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe30c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe30c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe30c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599eb8c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (8131 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629ece5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629ece57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629ece5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32eef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32eef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32eef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32eeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629ecdf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629ecdf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629ecdd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629eca84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629eca84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32eeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32eeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32eeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629eca84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (8132 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555fad51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555fad4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555fad5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a2ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a2ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a2ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a2ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555face7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555face7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555faccc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555fa97be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555fa97bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a2ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a2ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a2ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555fa97ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (8133 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0b1e88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0b1e85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0b1e8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f738b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f738b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f738b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f738b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0b1e1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0b1e1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0b1e038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0b1ab2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0b1ab2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f738b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f738b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f738b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0b1ab2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (8136 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f42d54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f42d51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f42d5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe096133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe09618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe096133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe09611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f42ceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f42ceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f42ccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f4297ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f4297eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe09611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe09611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe09611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f4297ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (8139 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4
# | ...
# `---data was truncated (10240/25575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b185282eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b18527fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b18528362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae96b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae96b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae96b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae96b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b185218bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b185218a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1851fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b184eace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b184eacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae96b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae96b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae96b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b184eaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (8143 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 =
# | ...
# `---data was truncated (10240/26564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d31759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d31756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d3175a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a22a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a22aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a22a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a22a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d316efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d316efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d316d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d31383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d31383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a22a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a22a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a22a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d31383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (8144 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, a
# | ...
# `---data was truncated (10240/30276) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642a2a72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642a2a6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642a2a7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff95849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff958a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff95849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff95831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642a2a08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642a2a08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642a29ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642a269ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642a269cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff95832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff958330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff958330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642a269ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (8145 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a62391aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a623917e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a62391b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe9cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe9cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe9cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe9caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6238b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6238b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6238958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a623544e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a623544b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe9caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe9caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe9caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a623544a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (8146 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af46068eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af46065e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af4606962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3f4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3f438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3f4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3f431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af45ffebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af45ffea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af45fe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af45c92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af45c92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3f431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3f431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3f431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af45c92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (8150 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e3426eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e3426be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e3426f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfcff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfcff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfcff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfcfeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e34204bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e34204a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e341e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e33e98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e33e98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfcfeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfcfeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfcfeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e33e98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (8151 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639601a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639601a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639601a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa288449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2884a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa288449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa288431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056396013bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056396013ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639601208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056395fdcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056395fdcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa288432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2884330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2884330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056395fdcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (8152 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale 
# | ...
# `---data was truncated (10240/13048) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc1a41aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc1a417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc1a41b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f804a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f804a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f804a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f804a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc1a3b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc1a3b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc1a3958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc1a044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc1a044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f804a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f804a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f804a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc1a044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (8154 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561757e6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561757e67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561757e6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd87f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd87f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd87f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd87f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561757e00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561757e00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561757de58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561757a94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561757a94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd87f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd87f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd87f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561757a94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (8155 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce971e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce971e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce971e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc37f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc37f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc37f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc37f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce9717abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce9717aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce9715f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce96e0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce96e0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc37f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc37f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc37f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce96e0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (8158 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, 
# | ...
# `---data was truncated (10240/26468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055915a65aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055915a657e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055915a65b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7aae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7aaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7aae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7aae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055915a5f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055915a5f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055915a5d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055915a284e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055915a284b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7aae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7aae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7aae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055915a284a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (8161 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c5361ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c53619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c5361d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63f0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63f0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63f0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63f0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c535b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c535b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c535978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c53246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c53246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63f0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63f0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63f0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c53246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (8162 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/14493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8285f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8285f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8285f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f078cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f078cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f078cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f078cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b828589bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b828589a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b82856e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b82821de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b82821db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f078cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f078cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f078cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b82821da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (8163 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055603ea32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055603ea2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055603ea3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54b0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055603e9c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055603e9c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055603e9ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055603e65ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055603e65cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055603e65ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (8164 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559575acbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559575ac8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559575acc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e2a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e2a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e2a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e2a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559575a61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559575a61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559575a468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595756f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595756f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e2a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e2a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e2a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595756f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (8166 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d24daf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d24daede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d24daf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faceee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faceeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faceee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faceee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d24da86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d24da86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d24da6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d24d71ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d24d71ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faceee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faceee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faceee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d24d71aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (8167 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562957ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562957ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562957ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b63333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b6338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b63333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b6331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562957a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562957a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562957a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562957703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562957703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b6331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b6331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b6331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562957703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (8168 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651f60c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651f60bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651f60c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb131049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb131049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb131031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651f6057bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651f6057a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651f603c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651f5cebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651f5cebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb131032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1310330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651f5ceba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (8169 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b8962deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b8962ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b8962e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8209249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8209249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8209231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b895c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b895c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b895a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b89257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b89257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8209232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b89257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (8170 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d20ecbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d20ecbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d20ecbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb705933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb70598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb705933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb70591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d20ec54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d20ec54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d20ec398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d20e8e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d20e8e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb70591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb70591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb70591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d20e8e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (8173 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570fad60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570fad5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570fad6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e67c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e67ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e67c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e67c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570facf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570facf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570facdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570fa98ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570fa98ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e67c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e67c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e67c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570fa98aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (8174 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fabe089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fabe086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fabe08a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff46ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff46caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff46ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff46ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fabe01fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fabe01fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fabe0048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fabdcb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fabdcb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff46ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff46ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff46ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fabdcb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (8176 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563a2ae0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563a2adde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563a2ae162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd49ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd49cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd49ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd49ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563a2a76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563a2a76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563a2a5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563a270ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563a270ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd49ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd49ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd49ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563a270aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (8177 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638b19a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638b199ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638b19a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ace1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ace725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ace1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ace03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638b1937bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638b1937a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638b191c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638b15cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638b15cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ace04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ace050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ace050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638b15cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (8179 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609adcc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609adcc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609adcc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6368f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6368f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6368f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6368f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609adc5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609adc5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609adc438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609ad8f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609ad8f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6368f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6368f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6368f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ad8f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (8180 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056293a3c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056293a3c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056293a3ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb50c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb50c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb50c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb50c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056293a35fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056293a35fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056293a3448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562939ff3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562939ff3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb50c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb50c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb50c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562939ff3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (8181 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %bas
# | ...
# `---data was truncated (10240/29817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055810ad25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055810ad22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055810ad2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2f0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2f0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2f0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2f0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055810acbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055810acbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055810aca08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055810a94fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055810a94fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2f0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2f0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2f0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055810a94fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (8182 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 
# | ...
# `---data was truncated (10240/22890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056402069feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056402069ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640206a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff614d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff614d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff614d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff614d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564020635bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564020635a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056402061a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640202c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640202c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff614d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff614d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff614d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640202c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (8184 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596b549ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596b5499e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596b549d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd731f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd731f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd731f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd731f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596b5432bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596b5432a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596b54178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596b50c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596b50c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd731f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd731f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd731f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596b50c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (8185 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/14832) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d113828eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d113825e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d11382962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57fe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57fe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57fe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57fe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1137bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1137bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1137a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d113452e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d113452b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57fe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57fe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57fe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d113452a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (8186 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscal
# | ...
# `---data was truncated (10240/12471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e23ca9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e23ca6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e23caa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaeac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaeaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaeac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaeac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e23c3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e23c3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e23c248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e238d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e238d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaeac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaeac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaeac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e238d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (8187 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0504bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0504b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0504bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c53049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c530a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c53049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c53031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c050452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c050452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0504378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0500e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0500e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c53032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c530330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c530330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0500e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (8189 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b1d44ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b1d449e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b1d44d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2654133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f265418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2654133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f265411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b1d3e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b1d3e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b1d3c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b1d076e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b1d076b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f265411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f265411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f265411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b1d076a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (8191 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e90d25feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e90d25ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e90d26062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc246e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc246e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc246e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc246e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e90d1f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e90d1f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e90d1da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e90ce89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e90ce89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc246e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc246e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc246e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e90ce89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (8194 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aec6348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aec6345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aec634962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4934c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4934ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4934c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4934c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aec62debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aec62dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aec62c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aec5f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aec5f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4934c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4934c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4934c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aec5f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (8196 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9b9206eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9b9203e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9b920762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd82f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd82f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd82f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd82f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9b919cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9b919ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9b91818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9b8e30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9b8e30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd82f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd82f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd82f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9b8e30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (8198 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555582070eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055558206de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055558207162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f927f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f927f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555582006bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555582006a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555581feb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555581c9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555581c9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f927f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555581c9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (8201 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce144b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce144b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce144b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e06e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e06ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e06e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e06e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce1444cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce1444ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce144318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce140e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce140e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e06e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e06e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e06e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce140e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (8202 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600bc7bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600bc7b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600bc7bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f1e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f1e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f1e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f1e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600bc752bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600bc752a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600bc7378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600bc3e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600bc3e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f1e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f1e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f1e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600bc3e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (8203 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f15deb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f15deb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f15deb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb77d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb77d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb77d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb77d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f15de4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f15de4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f15de2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f15dadee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f15dadeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb77d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb77d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb77d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f15dadea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (8205 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055837dd54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055837dd51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055837dd5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd88b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd88b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd88b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd88aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055837dceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055837dceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055837dccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055837d97ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055837d97eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd88aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd88aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd88aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055837d97ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (8207 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e1a53aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e1a537e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e1a53b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f810f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f810f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f810f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f810f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e1a4d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e1a4d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e1a4b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e1a164e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e1a164b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f810f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f810f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f810f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e1a164a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (8209 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591ffa7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591ffa79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591ffa7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe13733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe1378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe13733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe1371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591ffa12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591ffa12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591ff9f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591ff6a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591ff6a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe1371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe1371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe1371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591ff6a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (8210 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.ris
# | ...
# `---data was truncated (10240/12914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616d97a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616d97a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616d97a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a94a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a94aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a94a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a94a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616d973cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616d973ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616d97218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616d93d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616d93d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a94a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a94a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a94a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616d93d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (8212 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmclr_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmclr_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmclr_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmclr_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmclr_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmclr_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmclr_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629507bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629507b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629507bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc55bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc55bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc55bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc55bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562950752bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562950752a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629507378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629503e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629503e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc55bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc55bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc55bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629503e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (8213 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d986d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d986d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d986d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cf4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cf478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cf4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cf471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d9866cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d9866ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d986518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d98300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d98300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0cf471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cf471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cf471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d98300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (8215 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560181bf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560181bf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560181bf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ef31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560181b89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560181b89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560181b6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056018181de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056018181db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056018181da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (8217 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbe4bceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbe4bcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbe4bcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe4b64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbe4b64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbe4b498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbe47f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbe47f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe47f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (8218 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1768cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1768cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1768d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f632b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f632b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f632b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f632b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c176865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c176865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c17684a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1764f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1764f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f632b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f632b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f632b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1764f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (8220 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556470f53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556470f50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556470f5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc589649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc589649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc589631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556470ee9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556470ee9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556470ece8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556470b7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556470b7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc589632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5896330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556470b7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (8222 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aac40ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562aac409e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562aac40d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2674849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26748a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2674849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2674831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aac3a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562aac3a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562aac3878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562aac036e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562aac036b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2674832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26748330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26748330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aac036a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (8224 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <v
# | ...
# `---data was truncated (10240/12083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649abe57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649abe54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649abe5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe538e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe538ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe538e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe538e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649abdedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649abdeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649abdd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649aba81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649aba81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe538e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe538e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe538e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649aba81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (8225 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb33ec8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb33ec5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb33ec962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32c0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32c0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32c0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32c0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb33e5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb33e5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb33e438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb33af2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb33af2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32c0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32c0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32c0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb33af2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (8227 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0ac8e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0ac8e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0ac8e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfcad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfcad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfcad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfcad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0ac87abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0ac87aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0ac85f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0ac50ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0ac50eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfcad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfcad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfcad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0ac50ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (8228 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x 
# | ...
# `---data was truncated (10240/11632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0148efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0148ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0148f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99c2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99c2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99c2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99c2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b014885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b014885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b01486a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b014519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b014519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99c2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99c2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99c2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b014519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (8229 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5d7651eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5d764ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5d765262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09de933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09de98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09de933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09de91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5d75e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5d75e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5d75cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5d727be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5d727bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09de91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09de91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09de91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5d727ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (8230 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/26976) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dc8634eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dc8631e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dc863562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe097333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe09738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe097333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe09731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dc85cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dc85caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dc85af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dc825ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dc825eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe09731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe09731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe09731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dc825ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (8231 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557567933eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557567930e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055756793462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5af6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5af658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5af6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5af651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575678c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575678c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575678ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055756755de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055756755db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5af651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5af651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5af651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055756755da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (8232 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562896e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562896e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562896e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b362725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b36203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055628967abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055628967aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055628965f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055628930ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055628930eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b36204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b362050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b362050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055628930ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (8233 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b2a6c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b2a6c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b2a6c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc967b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc967b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc967b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc967b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b2a65bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b2a65ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b2a6408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b2a2efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b2a2efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc967b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc967b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc967b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b2a2efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (8236 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a9140deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a9140ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a9140e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc75d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc75d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc75d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc75d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a913a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a913a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a913888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a91037e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a91037b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc75d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc75d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc75d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a91037a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (8237 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555da62e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555da62e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555da62e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc1201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc120725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc1201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc12003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555da627bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555da627ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555da62608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555da5f0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555da5f0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc12004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc120050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc120050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555da5f0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (8238 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563217362eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056321735fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056321736362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa26ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa26ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa26ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa26ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632172f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632172f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632172dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563216f8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563216f8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa26ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa26ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa26ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563216f8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (8239 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare 
# | ...
# `---data was truncated (10240/20139) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056369de6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056369de6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056369de6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3d5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3d5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3d5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3d5e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056369de03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056369de03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056369dde88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056369da97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056369da97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3d5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3d5e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3d5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369da97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (8241 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec8d2c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec8d2bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec8d2c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10cf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10cf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10cf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10cf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec8d258bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec8d258a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec8d23d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec8ceece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec8ceecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10cf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10cf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10cf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec8ceeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (8243 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/15203) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6d44f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6d44f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6d44f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0449449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04494a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0449449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0449431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6d448abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6d448aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6d446f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6d411ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6d411eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0449432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04494330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04494330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6d411ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (8246 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636bffb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636bffb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636bffb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67dc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67dc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67dc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67dc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636bff4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636bff4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636bff338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636bfbe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636bfbe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67dc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67dc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67dc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636bfbe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (8247 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ace480beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ace4808e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ace480c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7102f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7102f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7102f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7102f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ace47a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ace47a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ace47868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ace4435e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ace4435b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7102f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7102f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7102f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ace4435a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (8248 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/13593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636bb41ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636bb419e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636bb41d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f160a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f160a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f160a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f160a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636bb3b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636bb3b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636bb3978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636bb046e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636bb046b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f160a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f160a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f160a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636bb046a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (8249 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac84848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac84845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac8484962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac847debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac847dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac847c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac84472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac84472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90a8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac84472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (8250 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560419814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560419811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056041981562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f7e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f7e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f7e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f7e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604197aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604197aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056041978f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056041943ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056041943eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f7e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f7e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f7e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056041943ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (8252 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b96986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b96983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b9698762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2104b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2104b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2104b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2104b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b9691cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b9691ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b969018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b965b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b965b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2104b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2104b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2104b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b965b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (8253 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055790499deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055790499ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055790499e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d6e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d6e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d6e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d6e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557904933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557904933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579049188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579045c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579045c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d6e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d6e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d6e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579045c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (8254 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9980d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9980d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9980d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14b0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14b098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14b0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14b091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a998069bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a998069a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a99804e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a997cfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a997cfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14b091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14b091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14b091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a997cfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (8258 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdc325eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdc322e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdc32662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f335fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f335fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdc2bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdc2bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdc2a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bdbf4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bdbf4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f335fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdbf4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (8259 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d67757deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d67757ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d67757e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27d2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27d2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27d2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27d2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d677513bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d677513a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6774f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6771a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6771a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27d2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27d2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27d2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6771a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (8262 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b861a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b861a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b861a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2300049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23000a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2300049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2300031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b8613bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b8613ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b861208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b85dcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b85dcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2300032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23000330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23000330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b85dcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/SystemZ/zvector.c (8266 of 27910)
******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector  -emit-llvm -o - -W -Wall -Werror  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c"
# | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
# | target triple = "s390x-unknown-linux-gnu"
# | 
# | @sc2 = global <16 x i8> zeroinitializer, align 8
# | @sc = global <16 x i8> zeroinitializer, align 8
# | @uc2 = global <16 x i8> zeroinitializer, align 8
# | @uc = global <16 x i8> zeroinitializer, align 8
# | @ss2 = global <8 x i16> zeroinitializer, align 8
# | @ss = global <8 x i16> zeroinitializer, align 8
# | @us2 = global <8 x i16> zeroinitializer, align 8
# | @us = global <8 x i16> zeroinitializer, align 8
# | @si2 = global <4 x i32> zeroinitializer, align 8
# | @si = global <4 x i32> zeroinitializer, align 8
# | @ui2 = global <4 x i32> zeroinitializer, align 8
# | @ui = global <4 x i32> zeroinitializer, align 8
# | @sl2 = global <2 x i64> zeroinitializer, align 8
# | @sl = global <2 x i64> zeroinitializer, align 8
# | @ul2 = global <2 x i64> zeroinitializer, align 8
# | @ul = global <2 x i64> zeroinitializer, align 8
# | @slll2 = global <1 x i128> zeroinitializer, align 8
# | @slll = global <1 x i128> zeroinitializer, align 8
# | @ulll2 = global <1 x i128> zeroinitializer, align 8
# | @ulll = global <1 x i128> zeroinitializer, align 8
# | @fd2 = global <2 x double> zeroinitializer, align 8
# | @fd = global <2 x double> zeroinitializer, align 8
# | @bc2 = global <16 x i8> zeroinitializer, align 8
# | @bc = global <16 x i8> zeroinitializer, align 8
# | @bs2 = global <8 x i16> zeroinitializer, align 8
# | @bs = global <8 x i16> zeroinitializer, align 8
# | @bi2 = global <4 x i32> zeroinitializer, align 8
# | @bi = global <4 x i32> zeroinitializer, align 8
# | @bl2 = global <2 x i64> zeroinitializer, align 8
# | @bl = global <2 x i64> zeroinitializer, align 8
# | @blll2 = global <1 x i128> zeroinitializer, align 8
# | @blll = global <1 x i128> zeroinitializer, align 8
# | @cnt = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_assign() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_pos() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_neg() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %sub = sub <16 x i8> zeroinitializer, %0
# |   store volatile <16 x i8> %sub, ptr @sc, align 8
# |   %1 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %sub1 = sub <8 x i16> zeroinitializer, %1
# |   store volatile <8 x i16> %sub1, ptr @ss, align 8
# |   %2 = load volatile <4 x i32>, ptr @si2, align 8
# |   %sub2 = sub <4 x i32> zeroinitializer, %2
# |   store volatile <4 x i32> %sub2, ptr @si, align 8
# |   %3 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %sub3 = sub <2 x i64> zeroinitializer, %3
# |   store volatile <2 x i64> %sub3, ptr @sl, align 8
# |   %4 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %sub4 = sub <1 x i128> zeroinitializer, %4
# |   store volatile <1 x i128> %sub4, ptr @slll, align 8
# |   %5 = load volatile <2 x double>, ptr @fd2, align 8
# |   %fneg = fneg <2 x double> %5
# |   store volatile <2 x double> %fneg, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_preinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_postinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_predec() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %dec = add <16 x i8> %0, splat (i8 -1)
# |   store volatile <16 x i8> %dec, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %dec1 = add <16 x i8> %1, splat (i8 -1)
# |   store volatile <16 x i8> %dec1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %dec2 = add <8 x i16> %2, splat (i16 -1)
# |   store volatile <8 x i16> %dec2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %dec3 = add <8 x i16> %3, splat (i16 -1)
# |   store volatile <8 x i16> %dec3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %dec4 = add <4 x i32> %4, splat (i32 -1)
# |   store volatile <4 x i32> %dec4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %dec5 = add <4 x i32> %5, splat (i32 -1)
# |   store volatile <4 x i32> %dec5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %dec6 = add <2 x i64> %6, splat (i64 -1)
# |   store volatile <2 x i64> %dec6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %dec7 = add <2 x i64> %7, splat (i64 -1)
# |   store volatile <2 x i64> %dec7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %dec8 = add <1 x i128> %8, splat (i128 -1)
# |   store volatile <1 x i128> %dec8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %dec
# | ...
# `---data was truncated (10240/152876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de5e77eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de5e77be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de5e77f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6059b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6059b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6059b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6059b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de5e714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de5e714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de5e6f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de5e3a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de5e3a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6059b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6059b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6059b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de5e3a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (8267 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsli
# | ...
# `---data was truncated (10240/14908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616988e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616988dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616988e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0143c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0143ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0143c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0143c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561698878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561698878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056169885d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056169850ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056169850cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0143c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0143c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0143c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056169850ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (8268 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/12177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd51142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd5113fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd5114362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f097e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f097e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f097e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f097e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd510d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd510d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd510bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd50d6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd50d6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f097e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f097e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f097e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd50d6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (8270 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cedd58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cedd55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cedd5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6631933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6631933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cedceebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cedceea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cedcd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ced982e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ced982b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f663191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ced982a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (8273 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055695e62deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055695e62ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055695e62e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9941b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9941b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9941b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9941b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055695e5c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055695e5c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055695e5a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055695e257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055695e257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9941b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9941b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9941b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055695e257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (8274 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c73b6e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c73b6dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c73b6e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c5621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c562725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c5621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c56203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c73b676bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c73b676a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c73b65b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c73b30ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c73b30ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c56204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c562050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c562050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c73b30aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (8277 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e5e123eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e5e120e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e5e12462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a5fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a5fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e5e0b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e5e0b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e5e09e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e5dd4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e5dd4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a5fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e5dd4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (8279 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e16aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e16aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e16af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f906041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90604725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f906041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9060403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e16a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e16a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e16a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e16719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e16719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9060404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90604050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90604050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e16719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (8280 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db7cac5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db7cac2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db7cac662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db7ca5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db7ca5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db7ca408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db7c6efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db7c6efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5c8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db7c6efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (8281 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634db6faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634db6f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634db6fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc006505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc00655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc006505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0064ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634db690bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634db690a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634db6758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634db324e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634db324b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0064eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0064ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0064ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634db324a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (8282 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056129e64beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056129e648e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056129e64c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83d4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83d458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83d4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83d451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056129e5e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056129e5e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056129e5c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056129e275e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056129e275b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83d451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83d451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83d451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056129e275a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (8284 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056297c8baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056297c8b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056297c8bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb83105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb8315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb83105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb830ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056297c850bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056297c850a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056297c8358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056297c4e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056297c4e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb830eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb830ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb830ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056297c4e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (8285 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a24e373eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a24e370e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a24e37462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe14a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe14a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe14a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe14a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a24e309bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a24e309a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a24e2ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a24df9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a24df9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe14a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe14a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe14a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a24df9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (8291 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558adbcc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558adbcc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558adbcc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9521449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9521449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9521431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558adbc5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558adbc5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558adbc428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558adb8f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558adb8f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9521432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95214330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558adb8f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (8294 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea5591aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea55917e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea5591b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc699049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc699049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc699031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea558b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea558b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea558958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea55544e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea55544b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc699032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6990330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea55544a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (8296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615a90c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615a90c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615a90c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5909b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5909b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5909b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5909b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615a905ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615a905ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615a90438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615a8cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615a8cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5909b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5909b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5909b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615a8cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (8297 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556607060eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055660705de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055660706162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ff1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ff178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ff1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ff171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556606ff6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556606ff6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556606fdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556606c8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556606c8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ff171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ff171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ff171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556606c8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (8298 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571320e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571320e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571320e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d66a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d66aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d66a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d66a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055713207bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055713207ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571320608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557131d0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557131d0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d66a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d66a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d66a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557131d0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (8299 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f496cd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f496cd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f496cd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f486ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f486ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f496c6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f496c6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f496c518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f496900e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f496900b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f486ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f496900a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (8302 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale
# | ...
# `---data was truncated (10240/12129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fe371ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fe3719e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fe371d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fe36b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fe36b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fe36978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fe3346e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fe3346b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fe3346a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (8303 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7ffa20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7ffa1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7ffa2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34fe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34fe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34fe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34fe51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7ff9b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7ff9b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7ff99b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7ff64ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7ff64ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34fe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34fe51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34fe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7ff64aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (8304 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee553d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee553d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee553d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbb2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbb298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbb2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbb291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee5536bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee5536ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee553508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee54fffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee54fffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbb291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbb291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbb291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee54fffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (8305 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba3c94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ba3c91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ba3c9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f880ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f880caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f880ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f880ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba3c2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ba3c2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ba3c0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ba38bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ba38beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f880ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f880ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f880ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba38bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (8307 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627dfda2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627dfd9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627dfda362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56b5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56b575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56b5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56b56ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627dfd38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627dfd38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627dfd1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627df9cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627df9ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56b56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56b56ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56b56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627df9cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (8308 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bb5af1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bb5aeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bb5af262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4362c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4362ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4362c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4362c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bb5a87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bb5a87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bb5a6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bb571be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bb571bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4362c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4362c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4362c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bb571ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (8310 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/12688) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561df299aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561df2997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561df299b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf38c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf38ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf38c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf38c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df2930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561df2930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df29158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561df25c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561df25c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf38c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf38c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf38c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df25c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (8311 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558905251eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055890524ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055890525262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b4bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b4bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589051e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589051e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589051cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558904e7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558904e7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b4bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558904e7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (8312 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c221e9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c221e97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c221e9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50d2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50d2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50d2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50d2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c221e30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c221e30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c221e158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c221ac4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c221ac4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50d2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50d2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50d2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c221ac4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (8313 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638774c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638774c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638774c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9fb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563877459bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563877459a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056387743e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638770ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638770edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638770eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (8314 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b76cc99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b76cc96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b76cc9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f206d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f206d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f206d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f206d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b76cc2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b76cc2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b76cc148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b76c8c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b76c8c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f206d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f206d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f206d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b76c8c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (8315 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c0cce6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c0cce3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c0cce762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a49333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a4938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a49333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a4931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c0cc7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c0cc7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c0cc618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c0c910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c0c910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a4931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a4931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a4931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c0c910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (8317 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<vscale x
# | ...
# `---data was truncated (10240/11396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fed24aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fed247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fed24b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8de9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8de9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8de9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8de9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fed1e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fed1e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fed1c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fece74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fece74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8de9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8de9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8de9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fece74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (8318 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e98b894eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e98b891e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e98b89562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bcb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bcb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bcb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bcb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e98b82abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e98b82aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e98b80f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e98b4bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e98b4beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bcb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bcb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bcb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e98b4bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (8319 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564301872eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056430186fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056430187362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3072905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f307295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3072905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30728ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564301808bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564301808a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643017ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056430149ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056430149cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30728eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30728ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30728ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056430149ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (8321 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055977e138eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055977e135e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055977e13962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9af2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9af2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9af2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9af2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055977e0cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055977e0cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055977e0b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055977dd62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055977dd62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9af2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9af2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9af2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055977dd62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (8322 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630a23dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630a23d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630a23dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27f491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630a2371bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630a2371a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630a23568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630a2005e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630a2005b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27f491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630a2005a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (8325 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f600d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f600d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f600da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7356333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f735638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7356333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f735631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f6006fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f6006fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f600548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f5fd03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f5fd03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f735631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f735631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f735631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f5fd03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (8326 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd06a3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd06a3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd06a4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd069d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd069d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd069ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd06669e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd06669b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd06669a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (8327 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb6290feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb6290ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb6291062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb628a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb628a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb6288a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb62539e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb62539b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb62539a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (8328 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2926f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2926f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2926f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faeed41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faeed4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faeed41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faeed403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d29268abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d29268aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d29266f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d29231ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d29231eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faeed404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faeed4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faeed4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d29231ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (8329 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3fd46feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3fd46ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3fd47062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31e801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31e80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31e801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31e8003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3fd405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3fd405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3fd3ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3fd099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3fd099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31e8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31e80050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31e80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3fd099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (8330 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056113fe64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056113fe61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056113fe6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a23905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a2395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a23905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a238ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056113fdfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056113fdfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056113fddf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056113fa8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056113fa8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a238eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a238ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a238ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056113fa8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (8331 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a676ce8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a676ce5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a676ce962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ac7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ac718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ac7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ac711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a676c7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a676c7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a676c638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a676912e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a676912b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ac711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ac711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ac711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a676912a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (8333 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c91cdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c91cd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c91cdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c8bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c8bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c8bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c8bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c91c70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c91c70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c91c558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c91904e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c91904b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c8bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c8bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c8bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c91904a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (8334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559559b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559559b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559559b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe129933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe12998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe129933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe12991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559559ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559559ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559559ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559559766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559559766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe12991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe12991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe12991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559559766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (8335 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae67d6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae67d6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae67d7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ebd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ebd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ebd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ebd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae67d05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae67d05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae67cea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae67999e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae67999b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ebd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ebd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ebd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae67999a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (8337 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"SmallDataLi
# | ...
# `---data was truncated (10240/10285) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a686787eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a686784e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a68678862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4722505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f472255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4722505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47224ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a68671dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a68671da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6867028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6863b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6863b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f47224eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47224ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47224ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6863b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (8341 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560915237eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560915234e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056091523862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83f8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609151cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609151cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609151b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560914e61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560914e61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83f8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560914e61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (8342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddde663eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddde660e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddde66462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbea9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbea998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbea9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbea991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddde5f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddde5f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddde5de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddde28de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddde28db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbea991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbea991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbea991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddde28da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (8343 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562413acbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562413ac8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562413acc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa95333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa95333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562413a61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562413a61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562413a468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624136f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624136f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa9531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624136f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (8344 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd99961eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd9995ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd9996262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3b5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3b538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3b5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3b531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd998f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd998f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd998dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd9958be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd9958bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3b531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3b531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3b531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd9958ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (8345 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056028aeaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056028aea7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056028aeab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76ff849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76ff8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76ff849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76ff831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056028ae40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056028ae40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056028ae258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056028aad4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056028aad4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76ff832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76ff8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76ff8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056028aad4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (8349 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4b0ee0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4b0edde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4b0ee162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f062d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f062d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f062d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f062d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b0e76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4b0e76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4b0e5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4b0b0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4b0b0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f062d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f062d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f062d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b0b0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (8351 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f4f91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622f4f8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622f4f9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b70c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b70ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b70c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b70c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f4f27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622f4f27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622f4f0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622f4bbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622f4bbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b70c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b70c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b70c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f4bbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (8353 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602b649aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602b6497e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602b649b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d58733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d5878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d58733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d5871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602b6430bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602b6430a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602b64158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602b60c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602b60c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d5871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d5871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d5871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602b60c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (8354 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vs
# | ...
# `---data was truncated (10240/18591) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aeb2ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aeb2cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aeb2cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf1c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf1c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf1c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf1c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aeb264bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aeb264a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aeb2498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aeaef8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aeaef8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf1c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf1c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf1c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aeaef8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (8356 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651cff25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651cff22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651cff2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff39d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff39d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff39d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff39d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651cfebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651cfebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651cfea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651cfb4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651cfb4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff39d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff39d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff39d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651cfb4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (8358 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a38f107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a38f104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a38f10862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc322b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc322b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc322b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc322b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a38f09dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a38f09da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a38f0828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a38ed31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a38ed31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc322b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc322b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc322b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a38ed31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (8360 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c59173eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c59170e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c5917462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36b2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36b28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36b2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36b2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c59109bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c59109a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c590ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c58d9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c58d9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36b2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36b28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36b28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c58d9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (8363 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562758282eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056275827fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056275828362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff966733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff96678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff966733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff96671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562758218bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562758218a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627581fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562757eace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562757eacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff96671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff96671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff96671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562757eaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (8366 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a00c6c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a00c6c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a00c6c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d7c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d7c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d7c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d7c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a00c65ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a00c65ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a00c6438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a00c2f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a00c2f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d7c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d7c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d7c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a00c2f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (8369 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f7da53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f7da50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f7da5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cbfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cbfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cbfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cbfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f7d9e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f7d9e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f7d9ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f7d67de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f7d67db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cbfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cbfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cbfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f7d67da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (8371 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056136a614eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056136a611e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056136a61562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd968733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd96878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd968733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd96871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056136a5aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056136a5aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056136a58f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056136a23ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056136a23eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd96871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd96871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd96871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056136a23ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (8373 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556aec6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556aec69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556aec6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f737d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f737d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f737d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f737d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556aec02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556aec02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556aebe78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556ae896e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556ae896b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f737d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f737d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f737d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556ae896a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (8374 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr
# | ...
# `---data was truncated (10240/14461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561533ea3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561533ea0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561533ea462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce58533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce5858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce58533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce5851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561533e39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561533e39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561533e1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561533acde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561533acdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce5851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce5851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce5851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561533acda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (8377 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a776406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a776403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a77640762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a77639cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a77639ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7763818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a776030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a776030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a776030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (8380 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llv
# | ...
# `---data was truncated (10240/18669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e33097eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e33097be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e33097f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a06e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a06ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a06e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a06e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e330914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e330914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3308f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3305a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3305a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a06e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a06e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a06e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3305a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (8382 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac60b83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac60b80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac60b8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a97133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a9718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a97133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a9711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac60b19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac60b19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac60afe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac607ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac607adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a9711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a9711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a9711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac607ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (8384 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558aaa348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aaa345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aaa34962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a00ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aaa2debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aaa2dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aaa2c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558aa9f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558aa9f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97a00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a00ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558aa9f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (8385 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0f2fb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0f2faee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0f2fb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bae031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0f2f47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0f2f47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0f2f2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0f2bdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0f2bdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bae0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0f2bdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (8388 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055957f540eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055957f53de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055957f54162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d88649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d88649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d88631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055957f4d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055957f4d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055957f4bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055957f16ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055957f16ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d88632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d886330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055957f16aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (8391 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a3ff6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a3ff6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a3ff6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcdf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcdf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcdf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcdf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a3ff03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a3ff03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a3fee88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a3fb97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a3fb97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcdf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcdf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcdf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a3fb97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (8392 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, i64 %2, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_
# | ...
# `---data was truncated (10240/15323) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c5b237eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c5b234e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c5b23862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19c3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19c3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19c3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19c3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c5b1cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c5b1cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c5b1b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c5ae61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c5ae61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19c3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19c3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19c3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c5ae61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (8395 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edd764feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edd764ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edd765062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab30a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab30aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab30a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab30a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edd75e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edd75e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edd75ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edd7279e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edd7279b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab30a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab30a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab30a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edd7279a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (8398 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca10763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca10760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca1076462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd433133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd43318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd433133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd43311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca106f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca106f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca106de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca1038de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca1038db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd43311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd43311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd43311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca1038da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (8399 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c882cc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c882cbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c882cc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10e7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10e778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10e7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10e771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c882c58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c882c58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c882c3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8828ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8828ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10e771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10e771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10e771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8828eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (8400 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579c411eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579c411be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579c411f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc682933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc68298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc682933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc68291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579c40b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579c40b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579c40998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579c3d48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579c3d48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc68291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc68291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc68291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579c3d48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (8401 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611f2a8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611f2a87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611f2a8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab8f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab8f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab8f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab8f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611f2a20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611f2a20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611f2a058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611f26b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611f26b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab8f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab8f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab8f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611f26b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (8402 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edb2f8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edb2f88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edb2f8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6131333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f613138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6131333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f613131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edb2f21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edb2f21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edb2f068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edb2bb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edb2bb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f613131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f613131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f613131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edb2bb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (8403 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c15723eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c15720e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c1572462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8b4a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8b4a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8b4a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8b4a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c156b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c156b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c1569e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c1534de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c1534db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8b4a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8b4a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8b4a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c1534da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (8405 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560a2971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560a296ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560a297262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560a2907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560a2907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560a28ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560a259be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560a259bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560a259ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (8408 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a0f36aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a0f367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a0f36b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc63d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc63d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc63d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc63d8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a0f300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a0f300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a0f2e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a0ef94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a0ef94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc63d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc63d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc63d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a0ef94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (8410 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d1fdaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d1fda7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d1fdab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ecbc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ecbc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ecbc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ecbc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d1fd40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d1fd40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d1fd258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d1f9d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d1f9d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ecbc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ecbc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ecbc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d1f9d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (8412 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555766c98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555766c95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555766c9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6997533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6997533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555766c2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555766c2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555766c138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557668c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557668c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557668c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (8413 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2bc7ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2bc7dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2bc7de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b15533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b1558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b15533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b1551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2bc773bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2bc773a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2bc7588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2bc407e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2bc407b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b1551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b1551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b1551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2bc407a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (8414 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056240f84deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056240f84ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056240f84e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facdea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facdeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facdea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facdea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056240f7e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056240f7e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056240f7c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056240f477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056240f477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facdea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facdea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facdea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056240f477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (8415 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b09f040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b09f03de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b09f04162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efec0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efec08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efec0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efec0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b09efd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b09efd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b09efbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b09ec6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b09ec6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efec0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efec08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efec08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b09ec6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (8416 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1791e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1791dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1791e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4b1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4b1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4b1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4b1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c179177bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c179177a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c17915c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c178e0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c178e0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4b1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4b1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4b1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c178e0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (8417 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e00318ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e003189e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e00318d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0705649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0705649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0705631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e003122bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e003122a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0031078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e002db6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e002db6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0705632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07056330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e002db6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (8419 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afd8efbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afd8ef8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afd8efc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ba7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ba7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ba7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ba7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afd8e91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afd8e91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afd8e768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afd8b25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afd8b25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ba7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ba7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ba7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afd8b25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (8420 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efca609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efca606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efca60a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc372533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc37258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc372533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc37251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efca59fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efca59fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efca5848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efca233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efca233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc37251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc37251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc37251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efca233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (8421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16
# | ...
# `---data was truncated (10240/12536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056265921feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056265921ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056265922062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626591b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626591b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056265919a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562658e49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562658e49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562658e49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (8422 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609fe0a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609fe0a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609fe0aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f930ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f930cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f930ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f930ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609fe03fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609fe03fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609fe0248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609fdcd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609fdcd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f930ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f930ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f930ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609fdcd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (8425 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607b9b16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607b9b13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607b9b1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80c5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80c5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80c5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80c5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607b9aacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607b9aaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607b9a918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607b9740e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607b9740b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80c5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80c5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80c5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607b9740a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (8429 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e53639eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e53636e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e5363a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ba8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ba8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ba8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ba8c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e535cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e535cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e535b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e53263e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e53263b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ba8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ba8c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ba8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e53263a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (8430 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i
# | ...
# `---data was truncated (10240/14788) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f910f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f910f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f910f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f03533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f0358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f03533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f0351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f910f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f910f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f910f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f910bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f910bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f0351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f0351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f0351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f910bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (8432 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3c652beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3c6528e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3c652c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5108c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5108ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5108c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5108c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3c64c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3c64c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3c64a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3c6155e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3c6155b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5108c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5108c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5108c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3c6155a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (8434 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620460cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620460cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620460ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60ef41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60ef4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60ef41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60ef403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562046063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562046063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620460488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562045cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562045cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60ef404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60ef4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60ef4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562045cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (8436 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055995551aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559955517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055995551b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f590b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f590b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f590b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f590b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599554b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599554b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599554958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559955144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559955144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f590b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f590b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f590b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559955144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (8437 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d2bfeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d2bfe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d2bfeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e43133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e4318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e43133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e4311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d2bf80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d2bf80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d2bf658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d2bc14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d2bc14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e4311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e4311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e4311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d2bc14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (8439 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056156eec5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056156eec2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056156eec662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe375d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe375d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe375d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe375d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056156ee5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056156ee5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056156ee408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056156eaefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056156eaefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe375d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe375d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe375d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056156eaefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (8441 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056527fd57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056527fd54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056527fd5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1613c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1613ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1613c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1613c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056527fcedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056527fceda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056527fcd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056527f981e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056527f981b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1613c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1613c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1613c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056527f981a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (8442 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d73c840eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d73c83de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d73c84162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8c1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8c16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8c1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8c1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d73c7d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d73c7d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d73c7bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d73c46ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d73c46ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8c1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8c16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8c16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d73c46aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (8444 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615c5017eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c5014e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c501862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f335f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f335f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f335f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f335f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c4fadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c4fada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c4f928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c4c41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c4c41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f335f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f335f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f335f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c4c41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (8445 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594d2662eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594d265fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594d266362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8019133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8019133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594d25f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594d25f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594d25dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594d228ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594d228cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594d228ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (8446 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9e8ba7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9e8ba4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9e8ba862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16b1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16b1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16b1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16b1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9e8b3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9e8b3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9e8b228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9e87d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9e87d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16b1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16b1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16b1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9e87d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (8447 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b71919eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b71916e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b7191a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f438aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f438aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f438aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b718afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b718afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b718948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b71543e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b71543b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f438aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f438aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f438aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b71543a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (8448 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb4a727eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb4a724e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb4a72862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48f4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48f48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48f4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48f4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb4a6bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb4a6bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb4a6a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb4a351e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb4a351b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48f4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48f48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48f48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb4a351a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (8451 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056518dedfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056518dedce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056518dee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37eea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37eeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37eea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37eea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056518de75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056518de75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056518de5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056518db09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056518db09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37eea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37eea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37eea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056518db09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (8452 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("risc
# | ...
# `---data was truncated (10240/14659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c94832eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c94832be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c94832f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9421c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9421c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9421c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9421c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9482c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9482c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9482a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c947f58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c947f58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9421c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9421c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9421c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c947f58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (8453 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eafb281eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eafb27ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eafb28262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7f6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7f638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7f6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7f631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eafb217bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eafb217a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eafb1fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eafaeabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eafaeabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7f631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7f631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7f631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eafaeaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (8454 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d9b50beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d9b508e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d9b50c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f102b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f102b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f102b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f102b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d9b4a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d9b4a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d9b4868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d9b135e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d9b135b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f102b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f102b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f102b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d9b135a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (8458 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e3704aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e37047e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e3704b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c6ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c6ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c6ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c6ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e36fe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e36fe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e36fc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e36c74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e36c74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c6ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c6ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c6ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e36c74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (8459 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entr
# | ...
# `---data was truncated (10240/18361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056321ef79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056321ef76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056321ef7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc704333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc70438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc704333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc70431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056321ef0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056321ef0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056321eef48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056321eba3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056321eba3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc70431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc70431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc70431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056321eba3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (8460 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd841c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd841bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd841c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2258733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f225878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2258733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f225871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd84156bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd84156a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd8413b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd83deae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd83deab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f225871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f225871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f225871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd83deaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (8461 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d158feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2d158ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2d159062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ae0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ae098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ae0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ae091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d1525bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2d1525a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2d150a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2d11b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2d11b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ae091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ae091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ae091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d11b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (8468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055956227beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559562278e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055956227c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19c8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19c8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19c8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19c8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559562211bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559562211a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595621f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559561ea5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559561ea5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19c8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19c8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19c8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559561ea5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (8469 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<
# | ...
# `---data was truncated (10240/11404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056043a48aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056043a487e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056043a48b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feef3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feef338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feef3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feef331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056043a420bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056043a420a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056043a4058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056043a0b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056043a0b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feef331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feef331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feef331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043a0b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (8470 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056381ed1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056381ed19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056381ed1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c57049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c570a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c57049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c57031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056381ecb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056381ecb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056381ec978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056381e946e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056381e946b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c57032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c570330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c570330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056381e946a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (8471 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d    -target-feature +v -target-feature +zfh -target-feature +zvfh    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 8)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t(<vscale x 16 x i8> %dest, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 8)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556085715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556085712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055608571662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa660249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6602a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa660249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa660231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560856abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560856aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560856908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055608533fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055608533fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa660232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6602330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6602330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055608533fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (8472 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9d599beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9d5998e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9d599c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad8ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad8cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad8ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad8ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9d5931bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9d5931a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9d59168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9d55c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9d55c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad8ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad8ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad8ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9d55c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (8478 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d20a392eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d20a38fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d20a39362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff699249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff699249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff699231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d20a328bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d20a328a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d20a30d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d209fbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d209fbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff699232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6992330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d209fbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (8479 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2aa09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e2aa06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2aa0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2a99fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e2a99fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e2a9848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e2a633e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e2a633b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e2a633a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (8480 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ddb962eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ddb95fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ddb96362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69cdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69cdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69cdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69cdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ddb8f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ddb8f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ddb8dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ddb58ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ddb58cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69cdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69cdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69cdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ddb58ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (8482 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acffaedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055acffaeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055acffaee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d2501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d250725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d2501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d25003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acffa83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055acffa83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055acffa688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055acff717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055acff717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d25004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d250050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d250050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acff717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (8484 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f0900deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f0900ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f0900e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e61f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e61f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e61f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e61eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f08fa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f08fa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f08f888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f08c37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f08c37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e61eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e61eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e61eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f08c37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (8485 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a19a2caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a19a2c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a19a2cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9587f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9587f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9587f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9587f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a19a260bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a19a260a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a19a2458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a199ef4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a199ef4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9587f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9587f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9587f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a199ef4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (8489 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd765aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd765abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd765af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ad6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ad62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ad6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ad6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd76544bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd76544a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd765298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd761d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd761d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ad6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ad62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ad62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd761d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (8491 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580f7ec3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580f7ec0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580f7ec462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef98049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef98049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef98031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580f7e59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580f7e59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580f7e3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580f7aede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580f7aedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef98032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef980330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580f7aeda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (8496 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0bb191eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0bb18ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0bb19262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae06f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae06f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae06f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae06f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0bb127bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0bb127a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0bb10c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0badbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0badbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae06f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae06f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae06f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0badbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (8497 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cede711eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cede70ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cede71262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b27f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b27f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b27f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b27eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cede6a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cede6a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cede68c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cede33be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cede33bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b27eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b27eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b27eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cede33ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (8498 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb9e06ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb9e069e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb9e06d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2ac61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2ac6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2ac61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2ac603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb9e002bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb9e002a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb9dfe78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb9dc96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb9dc96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2ac604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2ac6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2ac6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb9dc96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (8500 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c9e2b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c9e2b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c9e2b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8725b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8725b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8725b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8725b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c9e24bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c9e24ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c9e2308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c9dedfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c9dedfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8725b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8725b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8725b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c9dedfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (8503 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563391a75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563391a72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563391a7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe31a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe31a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe31a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe31a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563391a0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563391a0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633919f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056339169fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056339169fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe31a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe31a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe31a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056339169fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (8505 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/24990) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056313b193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056313b190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056313b19462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1529f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1529f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1529f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1529f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056313b129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056313b129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056313b10e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056313adbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056313adbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1529f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1529f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1529f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056313adbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (8507 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c5cb1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c5cb1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c5cb1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5efe105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5efe15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5efe105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5efe0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c5cab4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c5cab4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c5ca998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c5c748e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c5c748b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5efe0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5efe0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5efe0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c5c748a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (8508 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb1b8edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb1b8eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb1b8ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf7a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb1b883bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb1b883a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb1b8688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb1b517e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb1b517b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb1b517a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (8509 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d3aba9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d3aba6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d3abaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6af7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6af7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6af7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6af7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d3ab3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d3ab3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d3ab248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d3a7d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d3a7d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6af7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6af7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6af7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d3a7d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (8511 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30273deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c30273ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c30273e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f723a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f723a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f723a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f723a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3026d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3026d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3026b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c302367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c302367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f723a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f723a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f723a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c302367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (8512 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aaaca6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aaaca3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aaaca762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8b8505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8b855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8b8505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8b84ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aaac3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aaac3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aaac218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aaa8d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aaa8d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8b84eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8b84ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8b84ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aaa8d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (8515 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edfe550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edfe54de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edfe55162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2127e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2127ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2127e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2127e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edfe4e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edfe4e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edfe4cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edfe17ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edfe17ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2127e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2127e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2127e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edfe17aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (8516 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c6aa93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c6aa90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c6aa9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3029733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3029733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f302971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c6aa29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c6aa29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c6aa0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c6a6bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c6a6bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f302971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f302971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f302971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c6a6bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (8517 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @
# | ...
# `---data was truncated (10240/18570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d3e15ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d3e159e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d3e15d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbece905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbece95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbece905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbece8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d3e0f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d3e0f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d3e0d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d3dd86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d3dd86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbece8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbece8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbece8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d3dd86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (8519 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d7a0dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d7a0d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d7a0dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc769333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc76938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc769333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc76931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d7a071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d7a071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d7a0568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d79d05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d79d05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc76931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc76931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc76931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d79d05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (8525 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c1982ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c19829e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c1982d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f697be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f697bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f697be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f697be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c197c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c197c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c197a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c19456e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c19456b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f697be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f697be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f697be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c19456a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (8528 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b8c89feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b8c89ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b8c8a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37afc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37afca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37afc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37afc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b8c835bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b8c835a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b8c81a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b8c4c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b8c4c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37afc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37afc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37afc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b8c4c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (8529 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642661eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642661e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642661eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff130849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1308a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff130849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff130831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564266180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564266180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642661658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564265e14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564265e14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff130832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1308330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1308330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564265e14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (8530 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568b0674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568b0671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568b067562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac98649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac986a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac98649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac98631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568b060abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568b060aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568b05ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568b029ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568b029eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac98632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac986330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac986330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568b029ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (8533 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635f16deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635f16dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635f16df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8fa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635f1674bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635f1674a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635f16598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635f1308e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635f1308b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8fa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635f1308a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (8534 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593cd20ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593cd209e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593cd20d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bfd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bfd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bfd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bfd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593cd1a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593cd1a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593cd1878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593cce36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593cce36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bfd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bfd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bfd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593cce36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (8536 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac6e64beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac6e648e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac6e64c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba6d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac6e5e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac6e5e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac6e5c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac6e275e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac6e275b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6e275a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (8539 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055607f329eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055607f326e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055607f32a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b36333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b3638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b36333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b3631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055607f2bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055607f2bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055607f2a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055607ef53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055607ef53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b3631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b3631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b3631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055607ef53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (8540 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cf8f54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cf8f51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cf8f5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0263e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0263ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0263e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0263e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cf8eeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cf8eeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cf8ecf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cf8b7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cf8b7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0263e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0263e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0263e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cf8b7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (8541 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598945c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598945bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598945c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f056b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f056b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f056b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f056b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559894558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559894558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055989453d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598941ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598941ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f056b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f056b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f056b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598941eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (8543 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621035b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621035b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621035ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0358d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0358d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0358d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0358d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210354fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210354fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621035348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621031e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621031e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0358d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0358d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0358d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621031e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (8544 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055873ce32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055873ce2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055873ce3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64ed733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64ed78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64ed733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64ed71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055873cdc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055873cdc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055873cdad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055873ca5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055873ca5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64ed71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64ed71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64ed71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055873ca5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (8551 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a81866deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a81866ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a81866e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f54449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f544a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f54449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f54431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a818603bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a818603a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8185e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a818297e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a818297b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f54432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f544330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f544330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a818297a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (8554 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e086c1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e086c1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e086c1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faab0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faab0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faab0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faab0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e086bb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e086bb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e086b998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e086848e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e086848b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faab0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faab0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faab0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e086848a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (8555 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561848267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561848264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056184826862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88d0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88d098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88d0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88d091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618481fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618481fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618481e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561847e91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561847e91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88d091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88d091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88d091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561847e91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (8564 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635cf983eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635cf980e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635cf98462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4214705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f421475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4214705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42146ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635cf919bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635cf919a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635cf8fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635cf5ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635cf5adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42146eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42146ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42146ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635cf5ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (8568 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f6d548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f6d545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f6d54962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff850249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8502a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff850249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff850231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f6d4debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f6d4dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f6d4c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f6d172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f6d172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff850232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8502330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8502330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f6d172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (8569 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630379bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630379bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630379c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7975e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7975ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7975e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7975e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563037955bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563037955a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056303793a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630375e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630375e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7975e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7975e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7975e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630375e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (8572 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056353b187eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056353b184e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056353b18862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aa8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aa84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aa8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aa8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056353b11dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056353b11da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056353b1028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056353adb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056353adb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aa8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aa84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aa84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056353adb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (8574 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c8b43beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c8b438e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c8b43c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b65a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b65aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b65a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b65a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c8b3d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c8b3d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c8b3b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c8b065e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c8b065b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b65a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b65a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b65a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c8b065a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (8578 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560683888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560683885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056068388962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce62733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce6278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce62733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce6271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056068381ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056068381ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606838038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606834b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606834b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce6271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce6271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce6271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606834b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (8581 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b8fb38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b8fb35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b8fb3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb34249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb34249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb34231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b8facebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b8facea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b8fab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b8f762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b8f762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb34232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb342330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b8f762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (8582 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2c1d90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2c1d8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2c1d9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05b831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2c1d26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2c1d26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2c1d0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2c19bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2c19bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05b831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2c19baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (8584 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6e7b30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6e7b2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6e7b3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa477b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa477b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa477b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa477b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6e7ac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6e7ac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6e7aab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6e775ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6e775ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa477b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa477b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa477b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6e775aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (8588 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055890f7edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055890f7eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055890f7ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35de333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35de38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35de333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35de31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055890f783bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055890f783a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055890f7688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055890f417e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055890f417b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35de31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35de31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35de31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055890f417a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (8589 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565308228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565308225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056530822962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2dc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2dc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2dc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2dc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653081bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653081bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653081a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565307e52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565307e52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2dc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2dc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2dc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565307e52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (8590 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e725a74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e725a71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e725a7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6185449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6185449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6185431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e725a0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e725a0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7259ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e72569ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e72569eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6185432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61854330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e72569ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (8591 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bd9d8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bd9d89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bd9d8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f8d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f8d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f8d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f8d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bd9d22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bd9d22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bd9d078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bd99b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bd99b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f8d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f8d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f8d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bd99b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (8592 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e77316eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e77313e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e7731762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21b4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21b4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21b4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21b4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e772acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e772aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e772918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e76f40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e76f40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21b4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21b4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21b4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e76f40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (8593 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd1161eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559dd115ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559dd116262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8e1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd10f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559dd10f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559dd10dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559dd0d8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559dd0d8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8e1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd0d8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (8597 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624af02feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624af02ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624af03062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde05d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde05d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde05d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde05d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624aefc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624aefc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624aefaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624aec59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624aec59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde05d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde05d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde05d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624aec59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (8600 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504b776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056504b773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056504b77762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9f4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9f495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9f4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9f48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504b70cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056504b70ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056504b6f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056504b3a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056504b3a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9f48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9f48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9f48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504b3a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (8603 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/18867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f72c8b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f72c8b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f72c8b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4476c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4476ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4476c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4476c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f72c84cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f72c84ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f72c8318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f72c4e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f72c4e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4476c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4476c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4476c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f72c4e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (8604 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed17ed9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed17ed6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed17eda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2468533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f246858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2468533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f246851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed17e6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed17e6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed17e548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed17b03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed17b03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f246851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f246851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f246851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed17b03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (8605 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625dc8fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625dc8f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625dc8fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625dc891bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625dc891a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625dc8768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625dc525e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625dc525b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625dc525a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (8606 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056128e724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056128e721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056128e72562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff03fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff03fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff03fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff03fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056128e6babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056128e6baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056128e69f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056128e34ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056128e34eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff03fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff03fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff03fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056128e34ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (8608 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9ad055eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9ad052e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9ad05662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08af333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08af38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08af333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08af31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9acfebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9acfeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9acfd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9acc7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9acc7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08af31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08af31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08af31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9acc7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (8609 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb2acafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb2acace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb2acb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c35f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c35f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c35f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c35f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb2ac45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb2ac45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb2ac2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb2a8d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb2a8d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c35f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c35f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c35f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb2a8d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (8610 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f54a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f54a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f54a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6576133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f657618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6576133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f657611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f5499ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f5499ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f549838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f54632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f54632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f657611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f657611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f657611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f54632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (8611 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3e8a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3e8a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3e8a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5cdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5cdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5cdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5cdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3e89a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3e89a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3e898b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3e863ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3e863ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5cdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5cdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5cdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3e863aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (8612 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625817adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625817aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625817ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd987a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd987a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd987a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd987a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562581743bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562581743a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625817288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625813d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625813d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd987a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd987a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd987a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625813d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (8615 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056350bba1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056350bb9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056350bba262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2539b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2539b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2539b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2539aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056350bb37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056350bb37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056350bb1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056350b7cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056350b7cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2539aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2539aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2539aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056350b7cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (8618 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align
# | ...
# `---data was truncated (10240/19041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c65a677eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c65a674e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c65a67862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cc3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cc338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cc3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cc331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c65a60dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c65a60da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c65a5f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c65a2a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c65a2a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cc331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cc331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cc331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c65a2a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (8619 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> 
# | ...
# `---data was truncated (10240/12298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4a599deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4a599ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4a599e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3caad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3caad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3caad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3caad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4a5933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4a5933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4a59188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4a55c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4a55c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3caad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3caad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3caad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4a55c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (8622 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/14338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efb2594eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efb2591e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efb259562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb56d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb56d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb56d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb56d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efb252abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efb252aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efb250f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efb21bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efb21beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb56d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb56d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb56d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efb21bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (8624 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4b77aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4b77a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4b77ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b8eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b8eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b8eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b8eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4b7740bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4b7740a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4b77258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4b73d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4b73d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b8eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b8eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b8eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4b73d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (8625 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f57a88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f57a85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f57a8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d4a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d4a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d4a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d4a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f57a1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f57a1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f57a038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f576b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f576b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d4a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d4a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d4a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f576b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (8626 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2ecb68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2ecb65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2ecb6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe51cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe51cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe51cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe51cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2ecafebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2ecafea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2ecae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2ec792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2ec792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe51cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe51cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe51cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2ec792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (8630 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a653201eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6531fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a65320262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bdef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bdef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bdef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bdef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a653197bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a653197a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a65317c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a652e2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a652e2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bdef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bdef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bdef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a652e2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (8636 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589d44f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589d44eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589d44f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7dccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7dccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7dccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7dccb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589d4487bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589d4487a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589d446c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589d411be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589d411bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7dccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7dccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7dccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589d411ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (8639 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564083684eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564083681e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056408368562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa788449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7884a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa788449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa788431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056408361abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056408361aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640835ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640832aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640832aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa788432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7884330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7884330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640832aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (8641 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b49a0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b49a09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b49a0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b8a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b8a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b8a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b8a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b499a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b499a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b499878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b49636e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b49636b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b8a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b8a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b8a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b49636a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (8645 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a320ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a320cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a320cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b76849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b76849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b76831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a32064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a32064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a320498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a31cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a31cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b76832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b768330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a31cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (8649 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %v
# | ...
# `---data was truncated (10240/11349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f81f117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f81f114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f81f11862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64bdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64bdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64bdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64bdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f81f0adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f81f0ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f81f0928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f81ed41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f81ed41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64bdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64bdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64bdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f81ed41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (8650 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055894ec9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055894ec99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055894ec9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40fd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055894ec32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055894ec32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055894ec178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055894e8c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055894e8c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055894e8c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (8656 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/12644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558750ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558750cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558750cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbbf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbbf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbbf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbbf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555875064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555875064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558750498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555874cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555874cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbbf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbbf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbbf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555874cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (8657 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d471157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d471154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d47115862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe55ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe55ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe55ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe55feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4710edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4710eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4710d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d470d81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d470d81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe55feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe55feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe55feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d470d81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (8667 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652a5967eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652a5964e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652a596862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5825249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5825249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5825231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652a58fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652a58fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652a58e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652a5591e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652a5591b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5825232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652a5591a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (8669 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627b6985eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627b6982e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627b698662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2a6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2a6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2a6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2a6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627b691bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627b691ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627b69008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627b65afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627b65afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2a6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2a6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2a6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627b65afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (8670 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9124b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9124b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9124b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e91244abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e91244aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e91242f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9120dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9120deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94f8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9120dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (8671 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dfdbb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dfdbb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dfdbba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb21533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb2158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb21533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb2151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dfdb4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dfdb4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dfdb348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dfd7e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dfd7e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb2151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb2151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb2151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dfd7e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (8673 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vtdiscard() #0 {
# | entry:
# |   call void @llvm.riscv.sf.vtdiscard()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtdiscard() #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc1dd7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc1dd77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc1dd7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff59f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff59f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff59f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff59f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc1dd10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc1dd10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc1dcf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc1d9a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc1d9a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff59f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff59f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff59f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc1d9a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (8676 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626fdb8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626fdb87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626fdb8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb99f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb99f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb99f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb99f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626fdb20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626fdb20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626fdb058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626fd7b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626fd7b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb99f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb99f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb99f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626fd7b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (8677 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f5a3b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f5a3afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f5a3b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5c6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5c66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5c6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5c6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f5a348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f5a348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f5a32d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f59fdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f59fdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5c6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5c66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5c66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f59fdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (8679 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624f0ff9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624f0ff6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624f0ffa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2240849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2240849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2240831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624f0f8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624f0f8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624f0f748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624f0c23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624f0c23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2240832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624f0c23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (8681 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564358371eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056435836ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056435837262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbe1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbe16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbe1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbe1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564358307bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564358307a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643582ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564357f9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564357f9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbe1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbe16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbe16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564357f9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (8686 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b8841feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b8841ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b8842062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f49a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f49aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f49a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f49a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b883b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b883b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b8839a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b88049e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b88049b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f49a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f49a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f49a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b88049a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (8699 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/14699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a3324aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a33247e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a3324b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f961fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f961fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f961fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f961fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a331e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a331e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a331c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a32e74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a32e74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f961fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f961fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f961fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a32e74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (8703 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad7c0a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad7c0a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad7c0a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d5c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d5c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d5c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d5c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad7c039bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad7c039a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad7c01e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad7bccde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad7bccdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d5c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d5c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d5c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad7bccda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (8705 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa2e7f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa2e7f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa2e7f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecc5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecc538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecc5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecc531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa2e78cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa2e78ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa2e7718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa2e420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa2e420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecc531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecc531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecc531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa2e420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (8710 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c484276eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c484273e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c48427762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f57d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f57d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f57d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f57d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c48420cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c48420ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4841f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c483ea0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c483ea0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f57d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f57d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f57d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c483ea0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (8713 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dca1edaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dca1ed7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dca1edb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc922933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc92298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc922933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc92291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dca1e70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dca1e70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dca1e558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca1b04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca1b04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc92291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc92291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc92291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca1b04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (8714 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575f9241eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575f923ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575f924262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95a2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95a26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95a2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95a2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575f91d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575f91d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575f91bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575f8e6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575f8e6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95a2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95a26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95a26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575f8e6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (8735 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560efe8d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560efe8cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560efe8d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1157d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1157d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1157d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1157ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560efe868bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560efe868a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560efe84d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560efe4fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560efe4fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1157ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1157cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1157cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560efe4fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (8743 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e871c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e871c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e871c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0080b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0080b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0080b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0080b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e8715bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e8715ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e871408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e86defe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e86defb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0080b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0080b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0080b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e86defa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (8745 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9f6250eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9f624de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9f625162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f417f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f417f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f417f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f417f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9f61e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9f61e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9f61cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9f5e7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9f5e7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f417f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f417f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f417f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9f5e7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (8746 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad4e280eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad4e27de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad4e28162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea28b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea28b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea28b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea28b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad4e216bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad4e216a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad4e1fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad4deaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad4deaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea28b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea28b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea28b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad4deaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (8748 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ed889eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ed889be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ed889f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49bdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ed8834bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ed8834a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ed88198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ed84c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ed84c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ed84c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (8768 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638cf4f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638cf4f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638cf4f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c49133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c4918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c49133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c4911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638cf48dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638cf48da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638cf4728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638cf121e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638cf121b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c4911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c4911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c4911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638cf121a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (8771 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c34a7cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c34a7cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c34a7ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58c9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58c94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58c9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58c9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c34a763bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c34a763a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c34a7488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c34a3f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c34a3f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58c9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58c94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58c94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c34a3f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (8782 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4
# | ...
# `---data was truncated (10240/17583) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4196f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4196eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4196f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a419687bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a419687a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a41966c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a41931be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a41931bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4fdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a41931ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (8805 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580c03f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580c03f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580c03f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12b4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580c038abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580c038aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580c036f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580c001ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580c001eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12b4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580c001ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (8840 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556374cc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556374cbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556374cc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0f3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0f3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0f3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0f3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556374c56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556374c56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556374c3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563748eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563748eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0f3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0f3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0f3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563748eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/builtin-align.c (8880 of 27910)
******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR    -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR    -enable-var-scope '-D$PTRTYPE=i8'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | @aligned_true = global i8 1, align 1
# | @aligned_false = global i8 0, align 1
# | @down_1 = global i32 992, align 4
# | @down_2 = global i32 256, align 4
# | @up_1 = global i32 1024, align 4
# | @up_2 = global i32 256, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @get_type() #0 {
# | entry:
# |   ret ptr null
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %src_addr = ptrtoint ptr %0 to i64
# |   %set_bits = and i64 %src_addr, %mask
# |   %is_aligned = icmp eq i64 %set_bits, 0
# |   ret i1 %is_aligned
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000562de74b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562de74b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562de74b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb21af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb21af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb21af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb21af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562de744dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562de744da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562de74328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562de70e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562de70e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb21af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb21af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb21af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562de70e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (8897 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x float> @add_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x float>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %b.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store <8 x float> %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load <8 x float>, ptr %b.addr, align 8
# |   %add = fadd <8 x float> %0, %1
# |   store <8 x float> %add, ptr %retval, align 8
# |   %2 = load <8 x float>, ptr %retval,
# | ...
# `---data was truncated (10240/145303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000561aa916feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aa916ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aa917062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aa9105bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aa9105a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aa90ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561aa8d99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561aa8d99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aa8d99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (8995 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4dfde1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4dfddee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4dfde262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed6d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed6d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4dfd77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4dfd77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4dfd5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4dfa0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4dfa0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed6d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4dfa0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (8996 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ab17b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ab17b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ab17b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3475f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3475f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3475f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3475f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ab174cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ab174ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ab17318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ab13e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ab13e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3475f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3475f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3475f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ab13e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (9001 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626fe942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626fe93fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626fe94362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626fe8d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626fe8d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626fe8bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626fe56ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626fe56cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626fe56ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (9153 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# |  #0 0x0000556a2b349eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a2b346e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a2b34a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f953c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f953c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f953c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f953c803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a2b2dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a2b2dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a2b2c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a2af73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a2af73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f953c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f953c8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f953c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a2af73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (9217 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, al
# | ...
# `---data was truncated (10240/28866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c1672ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c16729e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c1672d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd4881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd488725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd4881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd48803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c166c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c166c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c166a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c16356e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c16356b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd48804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd488050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd488050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c16356a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (9334 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602ed89beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602ed898e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602ed89c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c1f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c1f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c1f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c1f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602ed831bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602ed831a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602ed8168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602ed4c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602ed4c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c1f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c1f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c1f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602ed4c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (9342 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef5c211eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef5c20ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef5c21262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9584133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f958418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9584133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f958411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef5c1a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef5c1a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef5c18c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef5be3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef5be3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f958411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f958411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f958411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef5be3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (9346 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1d0441eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1d043ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1d044262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4334849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4334849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4334831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1d03d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1d03d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1d03bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1d006be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1d006bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4334832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1d006ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80..
FAIL: Clang :: CodeGen/thinlto-multi-module.ll (9347 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# |  #0 0x00005605a54afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605a54ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605a54b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc82133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc8218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc82133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc8211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605a5445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605a5445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605a542a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605a50d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605a50d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc8211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc8211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc8211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605a50d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (9393 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563bc9a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563bc9a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563bc9aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60fde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60fdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60fde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60fde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563bc93fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563bc93fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563bc9248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563bc5d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563bc5d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60fde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60fde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60fde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563bc5d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (9405 of 27910)
******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# |  #0 0x0000560259215eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560259212e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056025921662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5d1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5d1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5d1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5d1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602591abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602591aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602591908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560258e3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560258e3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5d1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5d1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5d1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560258e3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (9666 of 27910)
******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# |  #0 0x000056301fa5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056301fa57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056301fa5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe39f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe39f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe39f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe39f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301f9f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056301f9f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056301f9d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056301f684e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056301f684b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe39f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe39f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe39f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301f684a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (9735 of 27910)
******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }>
# | %struct.A.base = type <{ ptr, i32 }>
# | 
# | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8
# | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x0000555c3901aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c39017e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c3901b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c38fb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c38fb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c38f958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c38c44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c38c44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c38c44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (10056 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# |  #0 0x0000563dc6b84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dc6b81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dc6b8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bd1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bd14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bd1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bd1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dc6b1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dc6b1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dc6aff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dc67aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dc67aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bd1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bd14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bd14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dc67aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (10059 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056366d468eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056366d465e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056366d46962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f546b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f546b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f546b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f546b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056366d3febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056366d3fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056366d3e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056366d092e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056366d092b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f546b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f546b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f546b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056366d092a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (10060 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f9bf1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f9bf17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f9bf1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f305b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f305b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f305b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f305b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f9beb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f9beb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f9be958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f9bb44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f9bb44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f305b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f305b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f305b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f9bb44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/arm64-crc32.c (10137 of 27910)
******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32x(i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fa3c60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561fa3c5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561fa3c6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7c9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7c938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7c9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7c931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fa3bf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561fa3bf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561fa3bdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561fa388ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561fa388ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7c931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7c931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7c931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fa388aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (10454 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# |  #0 0x00005559e9f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559e9f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559e9f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf7721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf772725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf7721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf77203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559e9f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559e9f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559e9efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559e9bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559e9bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf77204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf772050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf772050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559e9baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 
FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (10472 of 27910)
******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.annotated_flex = type { i64, i8, [0 x i8] }
# | 
# | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8
# | @sink = external global i64, align 8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_fam(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %2 = ptrtoint ptr %arraydecay to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %3 = icmp sgt i64 %flexible_array_member_size, -1
# |   %4 = select i1 %3, i64 %flexible_array_member_size, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_subscript(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2
# |   %2 = ptrtoint ptr %arrayidx to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 2
# |   %3 = icmp sgt i64 %result, -1
# |   %4 = and i1 true, %3
# |   %5 = select i1 %4, i64 %result, i64 0
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_addrof(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %2 = ptrtoint ptr %fam to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_fam() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %0 = icmp sgt i64 %flexible_array_member_size, -1
# |   %1 = select i1 %0, i64 %flexible_array_member_size, i64 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_subscript() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %0 = icmp sgt i64 %result, -1
# |   %1 = and i1 true, %0
# |   %2 = select i1 %1, i64 %result, i64 0
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_addrof() #0 {
# | entry:
# |   %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_fam(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %2 = icmp sgt i64 %flexible_array_member_size, -1
# |   %3 = select i1 %2, i64 %flexible_array_member_size, i64 0
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %2 = icmp sgt i64 %result, -1
# |   %3 = and i1 true, %2
# |   %4 = select i1 %3, i64 %result, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ff76148eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff76145e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff7614962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb26af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb26af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb26af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb26af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff760debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff760dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff760c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff75d72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff75d72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb26af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb26af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb26af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff75d72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/linker-diagnostic.ll (10758 of 27910)
******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# |  #0 0x000055dad5df8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dad5df5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dad5df962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bf3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bf38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bf3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bf3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dad5d8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dad5d8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dad5d738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dad5a22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dad5a22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bf3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bf38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bf38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dad5a22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (10833 of 27910)
******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default<O0>,default<O2>' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.wrapper = type { %struct.task }
# | %struct.task = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" }
# | %"struct.std::coroutine_handle.0" = type { ptr }
# | %"struct.task::promise_type" = type { i8 }
# | %"struct.std::suspend_always" = type { i8 }
# | 
# | $_ZN4task12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN4task12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN4task12promise_type11return_voidEv = comdat any
# | 
# | $_ZN4task12promise_type13final_suspendEv = comdat any
# | 
# | $_ZN7wrapperC1EO4task = comdat any
# | 
# | $_ZN4taskD1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZN7wrapperC2EO4task = comdat any
# | 
# | $_ZN4taskC1EOS_ = comdat any
# | 
# | $_ZN4taskC2EOS_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEaSEDn = comdat any
# | 
# | $_ZN4taskD2Ev = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any
# | 
# | ; Function Attrs: mustprogress nounwind presplitcoroutine
# | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %gro.active = alloca i1, align 1
# |   %__promise = alloca %"struct.task::promise_type", align 1
# |   %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6
# |   %ref.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %ref.tmp2 = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null)
# |   %1 = call i1 @llvm.coro.alloc(token %0)
# |   br i1 %1, label %coro.alloc, label %coro.init
# | 
# | coro.alloc:                                       ; preds = %entry
# |   %2 = call i64 @llvm.coro.size.i64()
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14
# |   br label %coro.init
# | 
# | coro.init:                                        ; preds = %coro.alloc, %entry
# |   %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ]
# |   %4 = call ptr @llvm.coro.begin(token %0, ptr %3)
# |   store i1 false, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %__promise) #9
# |   call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9
# |   call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   store i1 true, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9
# |   call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br i1 %call1, label %init.ready, label %init.suspend
# | 
# | init.suspend:                                     ; preds = %coro.init
# |   %5 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9
# |   %6 = call i8 @llvm.coro.suspend(token %5, i1 false)
# |   switch i8 %6, label %pre.gvo.conv [
# |     i8 0, label %init.ready
# |     i8 1, label %init.cleanup
# |   ]
# | 
# | init.cleanup:                                     ; preds = %init.suspend
# |   br label %cleanup
# | 
# | init.ready:                                       ; preds = %init.suspend, %coro.init
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %init.ready, %init.cleanup
# |   %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9
# |   switch i32 %cleanup.dest.slot.0, label %unreachable [
# |     i32 0, label %cleanup.cont
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | cleanup.cont:                                     ; preds = %cleanup
# |   call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   br label %coro.final
# | 
# | coro.final:                                       ; preds = %cleanup.cont
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9
# |   call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br i1 %call4, label %final.ready, label %final.suspend
# | 
# | final.suspend:                                    ; preds = %coro.final
# |   %7 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9
# |   %8 = call i8 @llvm.coro.suspend(token %7, i1 true)
# |   switch i8 %8, label %pre.gvo.conv [
# |     i8 0, label %final.ready
# |     i8 1, label %final.cleanup
# |   ]
# | 
# | final.cleanup:                                    ; preds = %final.suspend
# |   br label %cleanup5
# | 
# | final.ready:                                      ; preds = %final.suspend, %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br label %cleanup5
# | 
# | cleanup5:                                         ; preds = %final.ready, %final.cleanup
# |   %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9
# |   switch i32 %cleanup.dest.slot.1, label %unreachable [
# |     i32 0, label %pre.gvo.conv
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | pre.gvo.conv:                                     ; preds = %cleanup5, %final.suspend, %init.suspend
# |   %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ]
# |   %InRamp = call i1 @llvm.coro.is_in_ramp()
# |   br i1 %InRamp, label %gro.conv, label %after.gro.conv
# | 
# | gro.conv:                                         ; preds = %pre.gvo.conv
# |   call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9
# |   %cleanup.is_active = load i1, ptr %gro.active, align 1
# |   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done
# | 
# | cleanup.action:                                   ; preds = %gro.conv
# |   call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9
# |   br label %cleanup.done
# | 
# | cleanup.done:                                     ; preds = %cleanup.action, %gro.conv
# |   br label %after.gro.conv
# | 
# | after.gro.conv:                                   ; preds = %cleanup.done, %pre.gvo.conv
# |   br i1 %9, label %cleanup.cont7, label %coro.ret
# | 
# | cleanup.cont7:                                    ; preds = %after.gro.conv
# |   br label %coro.cleanup
# | 
# | coro.cleanup:                                     ; preds = %cleanup.cont7, %cleanup5, %cleanup
# |   call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9
# |   call void @llvm.lifetime.end.p0(ptr %__promise) #9
# |   %10 = call ptr @llvm.coro.free(token %0, ptr %4)
# |   %11 = icmp ne ptr %10, null
# |   br i1 %11, label %coro.free, label %after.coro.free
# | 
# | coro.free:                                        ; preds = %coro.cleanup
# |   %12 = call i64 @llvm.coro.size.i64()
# |   call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9
# |   br label %after.coro.free
# | 
# | after.coro.free:                                  ; preds = %coro.cleanup, %coro.free
# |   call void @llvm.coro.dead(ptr %4)
# |   br label %coro.ret
# | 
# | coro.ret:                                         ; preds = %after.coro.free, %after.gro.conv
# |   call void @llvm.coro.end(ptr null, i1 false, token none)
# |   ret void
# | 
# | unreachable:                                      ; preds = %cleanup5, %cleanup
# |   unreachable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i1 @llvm.coro.alloc(token) #2
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #3
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i64 @llvm.coro.size.i64() #2
# | 
# | ; Function Attrs: nounwind memory(argmem: readwrite)
# | declare ptr @llvm.coro.begin(token, ptr writeonly) #4
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5
# | 
# | ; Function Attrs: mustprogress nounwind
# | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %this.addr = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8, !tbaa !7
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"s
# | ...
# `---data was truncated (10240/31146) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default<O0>,default<O2>' -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default<O0>,default<O2> -S
# |  #0 0x000056107bf43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056107bf40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056107bf4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a7dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a7dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a7dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a7dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056107bed9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056107bed9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056107bebe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056107bb6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056107bb6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a7dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a7dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a7dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056107bb6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (11229 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# |  #0 0x000055b71d948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b71d945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b71d94962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4502c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4502ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4502c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4502c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b71d8debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b71d8dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b71d8c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b71d572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b71d572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4502c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4502c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4502c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b71d572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/X86/sse.c (11636 of 27910)
******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f609c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f609c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f609ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f264401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26440725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f264401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2644003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f6095fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f6095fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f609448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f605f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f605f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2644004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26440050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26440050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f605f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (11667 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabi"
# | 
# | %struct.Simple = type { i8, i8 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldrex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldaex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_strex(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %res = alloca i32, align 4
# |   %var = alloca %struct.Simple, align 1
# |   %tmp = alloca i64, align 8
# |   %tmp8 = alloca double, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i32 0, ptr %res, align 4
# |   call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false)
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0)
# |   %1 = load i32, ptr %res, align 4
# |   %or = or i32 %1, %strex
# |   store i32 %or, ptr %res, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2)
# |   %3 = load i32, ptr %res, align 4
# |   %or2 = or i32 %3, %strex1
# |   store i32 %or2, ptr %res, align 4
# |   %4 = load ptr, ptr %addr.addr, align 4
# |   %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4)
# |   %5 = load i32, ptr %res, align 4
# |   %or4 = or i32 %5, %strex3
# |   store i32 %or4, ptr %res, align 4
# |   store i64 42, ptr %tmp, align 8
# |   %6 = load { i32, i32 }, ptr %tmp, align 8
# |   %7 = extractvalue { i32, i32 } %6, 0
# |   %8 = extractvalue { i32, i32 } %6, 1
# |   %9 = load ptr, ptr %addr.addr, align 4
# |   %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9)
# |   %10 = load i32, ptr %res, align 4
# |   %or5 = or i32 %10, %strexd
# |   store i32 %or5, ptr %res, align 4
# |   %11 = load ptr, ptr %addr.addr, align 4
# |   %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11)
# |   %12 = load i32, ptr %res, align 4
# |   %or7 = or i32 %12, %strex6
# |   store i32 %or7, ptr %res, align 4
# |   store double 3.141590e+00, ptr %tmp8, align 8
# |   %13 = load { i32, i32 }, ptr %tmp8, align 8
# |   %14 = extractvalue { i32, i32 } %13, 0
# |   %15 = extractvalue { i32, i32 } %13, 1
# |   %16 = load ptr, ptr %addr.addr, align 4
# |   %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16)
# |   %17 = load i32, ptr %res, align 4
# |   %or10 = or i32 %17, %strexd9
# |   store i32 %or10, ptr %res, align 4
# |   %18 = load ptr, ptr %addr.addr, ali
# | ...
# `---data was truncated (10240/16971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ac9158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ac9155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ac915962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36f1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36f158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36f1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36f151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ac90eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ac90eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ac90d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ac8d82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ac8d82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36f151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36f151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36f151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ac8d82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (11730 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c  -check-prefix=RV32ZKSED
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksed1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d9cc88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9cc85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9cc8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe566733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe56678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe566733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe56671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d9cc1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d9cc1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d9cc038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d9c8b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d9c8b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe56671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe56671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe56671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d9c8b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (11807 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c  -check-prefix=RV32ZBKC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642486edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642486eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642486ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a46505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a4655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a46505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a464ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564248683bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564248683a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642486688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564248317e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564248317b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a464eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a464ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a464ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564248317a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (11862 of 27910)
******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# |  #0 0x000056434cef3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056434cef0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056434cef462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc623049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6230a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc623049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc623031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056434ce89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056434ce89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056434ce6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056434cb1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056434cb1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc623032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6230330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6230330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056434cb1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (11874 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local signext i32 @test() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
# |   %conv = trunc i64 %0 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056299d81aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056299d817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056299d81b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff06249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff06249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff06231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056299d7b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056299d7b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056299d7958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056299d444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056299d444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff06232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff062330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056299d444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (12122 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c  -check-prefix=RV32ZBKX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkx1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056533ca92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056533ca8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056533ca9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd16f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd16f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd16f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd16f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056533ca28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056533ca28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056533ca0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056533c6bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056533c6bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd16f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd16f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd16f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056533c6bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (12346 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# |  #0 0x000055df22f46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df22f43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df22f4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61aa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61aa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61aa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61aa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df22edcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df22edca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df22ec18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df22b70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df22b70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61aa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61aa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61aa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df22b70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (12421 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr.i = alloca bfloat, align 2
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   store bfloat %0, ptr %bf.addr.i, align 2
# |   %1 = load bfloat, ptr %bf.addr.i, align 2
# |   %2 = fpext bfloat %1 to float
# |   ret float %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr.i = alloca float, align 4
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   store float %0, ptr %sf.addr.i, align 4
# |   %1 = load float, ptr %sf.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   ret bfloat %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605dcc25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605dcc22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605dcc2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54ec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54ec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54ec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54ec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605dcbbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605dcbbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605dcba08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605dc84fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605dc84fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54ec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54ec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54ec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605dc84fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (12468 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c  -check-prefix=RV32ZBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @orc_b_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @ctz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cpop_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctpop.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.orc.b.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctpop.i32(i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b5a3beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b5a3bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b5a3bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b5a354bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b5a354a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b5a3398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b59fe8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b59fe8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23d4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b59fe8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (12505 of 27910)
******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %class.Foo = type { i8 }
# | %class.HasTrivialDestructor = type { i8 }
# | %struct.Data = type { ptr }
# | %struct.HasNonTrivialCopyConstructor = type { i8 }
# | %struct.HasNonTrivialCopyConstructor2 = type { i8 }
# | %struct.LargeWithCopyConstructor = type { [32 x i8] }
# | %class.anon = type { i8 }
# | 
# | $_Z12TemplateFuncIiET_S0_ = comdat any
# | 
# | $_Z6Func10IiEii = comdat any
# | 
# | $_Z6Func12IiET_S0_ = comdat any
# | 
# | @pmf = global { i64, i64 } zeroinitializer, align 8
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %entry
# |   %1 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1)
# |   ret i32 %call
# | 
# | 2:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | if.else:                                          ; preds = %entry
# |   %3 = load i32, ptr %x.addr, align 4
# |   %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3)
# |   ret i32 %call1
# | 
# | 4:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %4, %2
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | declare noundef i32 @_Z3Bari(i32 noundef) #1
# | 
# | declare noundef i32 @_Z3Bazi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z3Bari(i32 noundef %0)
# |   %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call)
# |   ret i32 %call1
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.Foo, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local void @_Z5Func5v() #0 {
# | entry:
# |   musttail call void @_Z11ReturnsVoidv()
# |   ret void
# | 
# | 0:                                                ; No predecessors!
# |   ret void
# | }
# | 
# | declare void @_Z11ReturnsVoidv() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.HasTrivialDestructor, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 {
# | entry:
# |   %data.addr = alloca ptr, align 8
# |   store ptr %data, ptr %data.addr, align 8
# |   %0 = load ptr, ptr %data.addr, align 8
# |   %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %fptr, align 8
# |   %2 = load ptr, ptr %data.addr, align 8
# |   %call = musttail call noundef i32 %1(ptr noundef %2)
# |   ret i32 %call
# | 
# | 3:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat {
# | entry:
# |   %.addr = alloca i32, align 4
# |   store i32 %0, ptr %.addr, align 4
# |   ret i32 5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %t = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 {
# | entry:
# |   %x.ad
# | ...
# `---data was truncated (10240/18685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# |  #0 0x0000555590f60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555590f5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555590f6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aa2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aa2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aa2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aa2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555590ef6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555590ef6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555590edb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555590b8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555590b8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aa2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aa2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aa2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555590b8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (12867 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   %1 = fpext bfloat %0 to float
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   %1 = fptrunc float %0 to bfloat
# |   ret bfloat %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abff733eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abff730e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abff73462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08ade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08adea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08ade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08ade31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abff6c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abff6c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abff6ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abff35de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abff35db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08ade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08ade330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08ade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abff35da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (12911 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c  -check-prefix=RV32ZKSH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599ef6f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599ef6f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599ef6fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b73849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b73849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b73831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599ef68fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599ef68fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599ef6748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599ef323e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599ef323b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b73832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b738330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599ef323a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (12926 of 27910)
******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# |  #0 0x000055c235ea5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c235ea2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c235ea662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b8fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b8fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b8fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b8fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c235e3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c235e3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c235e208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c235acfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c235acfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b8fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b8fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b8fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c235acfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (12931 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056387fc1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056387fc1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056387fc1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a66049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a66049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a66031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056387fbb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056387fbb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056387fb988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056387f847e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056387f847b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a66032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a660330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056387f847a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: Modules/pr93497.cppm (12977 of 27910)
******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 3
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm      -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp      -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm      -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.Thing = type { i32 }
# | %struct.C = type { i32 }
# | %struct.NonConstexprDtor = type { i32 }
# | 
# | $needed = comdat any
# | 
# | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4
# | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4
# | @_ZW3mod11ConstantPtr = external global ptr, align 8
# | @_ZW3mod16NonConstantValue = external global %struct.C, align 4
# | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4
# | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }]
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z3usev() #0 {
# | entry:
# |   %t1 = alloca %struct.Thing, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | declare noundef i32 @_Z7consumei(i32 noundef) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use2v() #0 {
# | entry:
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %0 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0)
# |   ret i32 %call
# | }
# | 
# | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use3v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ptr = alloca ptr, align 8
# |   %agg.tmp = alloca %struct.C, align 4
# |   %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8
# |   store ptr %0, ptr %Ptr, align 8
# |   %1 = load ptr, ptr %Ptr, align 8
# |   %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0
# |   %2 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %2, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %3 = load ptr, ptr %Ptr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %4 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr i32 @needed() #0 comdat {
# | entry:
# |   %call = call noundef i32 @_Z7consumei(i32 noundef 43)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use4v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ref = alloca %struct.C, align 4
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false)
# |   %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0
# |   %0 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %1 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use5v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %V = alloca %struct.NonConstexprDtor, align 4
# |   %cleanup.dest.slot = alloca i32, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %1 = load i32, ptr %raw1, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %1)
# |   store i32 %call, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | if.end:                                           ; preds = %entry
# |   %call2 = call i32 @needed()
# |   store i32 %call2, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %if.end, %if.then
# |   call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3
# | 
# | declare void @_ZGIW3mod()
# | 
# | ; Function Attrs: noinline nounwind
# | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" {
# | entry:
# |   call void @_ZGIW3mod()
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #5 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# |  #0 0x000055952036deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055952036ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055952036e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43e6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43e638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43e6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43e631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559520303bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559520303a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595202e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055951ff97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055951ff97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43e631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43e631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43e631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055951ff97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (12997 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> 
# | ...
# `---data was truncated (10240/63117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000559408f8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559408f8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559408f9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb77d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb77d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb77d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb77d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559408f25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559408f25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559408f0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559408bb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559408bb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb77d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb77d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb77d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559408bb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (13011 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c  -check-prefix=RV64ZKND-ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fa03b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fa03b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fa03b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd27333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd2738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd27333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd2731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fa034ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fa034ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fa03338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f9ffe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f9ffe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd2731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd2731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd2731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f9ffe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (13296 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = ashr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = lshr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = ashr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = lshr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @lshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %shl = shl <8 x i32> %0, %1
# |   store <8 x i32> %shl, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @rshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %r
# | ...
# `---data was truncated (10240/50943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056303bc0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056303bc0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056303bc0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc7a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc7a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc7a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc7a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056303bba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056303bba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056303bb898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056303b838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056303b838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc7a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc7a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc7a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056303b838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (13306 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c  -check-prefix=RV32ZBC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564419739eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564419736e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056441973a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc560733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc56078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc560733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc56071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644196cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644196cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644196b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564419363e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564419363b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc56071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc56071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc56071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564419363a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (13665 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @or_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %or = or <32 x i8> %0, %1
# |   store <32 x i8> %or, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 
# | ...
# `---data was truncated (10240/30877) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056352656deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056352656ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056352656e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb67a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb67a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb67a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb67a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563526503bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563526503a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635264e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563526197e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563526197b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb67a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb67a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb67a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563526197a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (13744 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c  -check-prefix=RV32ZBKB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.brev8.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @zip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.zip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @unzip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.unzip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.brev8.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.zip.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.unzip.i32(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564886011eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056488600ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056488601262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe442733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe44278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe442733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe44271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564885fa7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564885fa7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564885f8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564885c3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564885c3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe44271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe44271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe44271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564885c3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/builtins-riscv.c (13770 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 10, ptr %res, align 4
# |   store volatile i32 11, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557538643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557538640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055753864462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8b6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575385d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575385d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575385be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055753826de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055753826db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055753826da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/builtins-loongarch.c (13916 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "loongarch32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 4, ptr %res, align 4
# |   store volatile i32 5, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7b546aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7b5467e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7b546b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92e5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92e538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92e5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92e531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7b5400bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7b5400a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7b53e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7b5094e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7b5094b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92e531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92e531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92e531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7b5094a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (13949 of 27910)
******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc |     not grep _foo2
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @bar() #0 {
# | entry:
# |   call void @foo2()
# |   ret void
# | }
# | 
# | declare void @foo2() #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# |  #0 0x000055e0d364eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0d364be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0d364f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f5b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f5b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f5b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f5b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0d35e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0d35e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0d35c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0d3278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0d3278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f5b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f5b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f5b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0d3278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: llc
# executed command: not grep _foo2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (13961 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# |  #0 0x000055c8867aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8867abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8867af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07aec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07aec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07aec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07aec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c886744bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c886744a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8867298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8863d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8863d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07aec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07aec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07aec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8863d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (13993 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1)
# |   store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.fptosi.sat.i64.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   st
# | ...
# `---data was truncated (10240/53064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4bd0faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4bd0f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4bd0fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c9cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c9cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c9cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c9cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4bd090bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4bd090a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4bd0758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4bcd24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4bcd24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c9cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c9cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c9cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4bcd24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/arm-crc32.c (14017 of 27910)
******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563ab020eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563ab01de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563ab02162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc00f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc00f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc00f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc00f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563aafb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563aafb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563aaf9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563aac4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563aac4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc00f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc00f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc00f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563aac4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (14482 of 27910)
******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32-unknown-unknown"
# | 
# | %struct.asc = type { i8, i16, i32, i32, float, double }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %0 = load i32, ptr %argp.next, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16
# |   store ptr %argp.next2, ptr %va, align 4
# |   %2 = load double, ptr %1, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %2
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11
# |   %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load i32, ptr %argp.next, align 8, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0)
# |   store <2 x i64> %call, ptr %r, align 16, !tbaa !9
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr n
# | ...
# `---data was truncated (10240/20646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default<O1>) --expand-variadics-override=optimize -o -
# |  #0 0x000055a2d6c11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2d6c0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2d6c1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06f0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06f0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06f0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06f0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2d6ba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2d6ba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2d6b8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2d683be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2d683bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06f0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06f0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06f0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2d683ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (14506 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %class.anon = type { i8 }
# | 
# | $_Z15template_functyIiET_S0_ = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_caller() #0 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | declare i32 @normal_callee() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_callee() #0 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_decl() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_caller() #3 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_callee() #3 {
# | entry:
# |   %call = call i32 @streaming_compatible_decl() #16
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_compatible_decl() #4
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_caller() #5 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_callee() #5 {
# | entry:
# |   %call = call i32 @locally_streaming_caller() #17
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_caller() #6 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_callee() #6 {
# | entry:
# |   %call = call i32 @shared_za_decl() #18
# |   ret i32 %call
# | }
# | 
# | declare i32 @shared_za_decl() #7
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_caller() #8 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_callee() #8 {
# | entry:
# |   %call = call i32 @preserves_za_decl() #19
# |   ret i32 %call
# | }
# | 
# | declare i32 @preserves_za_decl() #9
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_caller() #10 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_callee() #10 {
# | entry:
# |   %call = call i32 @private_za_decl()
# |   ret i32 %call
# | }
# | 
# | declare i32 @private_za_decl() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_caller() #11 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee() #12 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | declare i32 @agnostic_za_decl() #13
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee_live_za() #6 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #16
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #18
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #19
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %fptr.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %fptr, ptr %fptr.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %fptr.addr, align 8
# |   %1 = load ptr, ptr %0, align 8
# |   %2 = load ptr, ptr %1, align 8
# |   %3 = load i32, ptr %x.addr, align 4
# |   %4 = load i32, ptr %y.addr, align 4
# |   call void %2(i32 noundef %3, i32 noundef %4) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @_Z24test_same_type_streamingv() #12 {
# | entry:
# |   call void @_Z10streaming1v() #15
# |   call void @_Z10streaming2v() #15
# |   call void @_Z20same_type_streaming1v() #15
# |   call void @_Z20same_type_streaming2v() #15
# |   ret void
# | }
# | 
# | declare void @_Z10streaming1v() #2
# | 
# | declare void @_Z10streaming2v() #2
# | 
# | declare void @_Z20same_type_streaming1v() #2
# | 
# | declare void @_Z20same_type_streaming2v() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   ret float %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   %call = call noundef float @_Z12overloadedfnf(float noundef %0)
# |   ret float %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %F = alloca %class.anon, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 {
# | entry:
# |   %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z25locally_streaming_inheritv() #5 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret void
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define dso_local noundef i32 @_Z4callv() #14 {
# | entry:
# |   ret i32 0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 {
# | entry:
# |   %f.addr.i16 = alloca ptr, align 8
# |   %f.addr.i12 = alloca ptr, align 8
# |   %other.addr.i13 = alloca ptr, align 8
# |   %f.addr.i7 = alloca ptr, align 8
# |   %other.addr.i8 = alloca ptr, align 8
# |   %other.addr2.i9 = alloca ptr, align 8
# |   %f.addr.i1 = alloca ptr, align 8
# |   %other.addr.i2 = alloca ptr, align 8
# |   %other.addr2.i3 = alloca ptr, align 8
# |   %other.addr4.i4 = alloca ptr, align 8
# |   %f.addr.i = alloca ptr, align 8
# |   %other.addr.i = alloca ptr, align 8
# |   %other.addr2.i = alloca ptr, align 8
# |   %other.addr4.i = alloca ptr, align 8
# |   %other.addr6.i = alloca ptr, align 8
# |   store ptr @normal_callee, ptr %f.addr.i, align 8
# |   store ptr @streaming_decl, ptr %other.addr.i, align 8
# |   store ptr @streaming_compatible_decl
# | ...
# `---data was truncated (10240/15241) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575dc13eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575dc13be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575dc13f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3848733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f384878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3848733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f384871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575dc0d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575dc0d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575dc0b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575dbd68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575dbd68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f384871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f384871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f384871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575dbd68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x000055f63f4bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f63f4b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f63f4bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f950d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f950d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f950d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f950d2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f63f452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f63f452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f63f4378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f63f0e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f63f0e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f950d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f950d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f950d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f63f0e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (15355 of 27910)
******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | declare noundef zeroext i1 @_Z1av() #1
# | 
# | declare noundef zeroext i1 @_Z1bv() #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.expect.i64(i64, i64) #2
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true)
# |   br i1 %call.expval, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true)
# |   br i1 %call1.expval, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i1 @llvm.expect.i1(i1, i1) #2
# | 
# | declare noundef zeroext i1 @_Z1cv() #1
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1cv()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:                                          ; preds = %lor.lhs.false
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %lor.end
# | 
# | lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
# |   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.end
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %if.then, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %if.then, label %lor.lhs.false2
# | 
# | lor.lhs.false2:                                   ; preds = %lor.lhs.false
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.lhs.false2
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %dec = add nsw i32 %2, -1
# |   store i32 %dec, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:     
# | ...
# `---data was truncated (10240/28468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# |  #0 0x00005564396f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564396f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564396f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb185733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb18578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb185733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb18571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556439689bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556439689a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055643966e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055643931de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055643931db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb18571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb18571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb18571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055643931da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (15520 of 27910)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# |  #0 0x00005597a945eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597a945be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597a945f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff36d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff36d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff36d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff36d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597a93f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597a93f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597a93d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597a9088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597a9088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff36d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff36d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff36d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597a9088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (15849 of 27910)
******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20       -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone       | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.MyTask = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { ptr }
# | %"struct.std::suspend_always" = type { i8 }
# | %struct.Awaiter = type { ptr }
# | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" }
# | 
# | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15await_transformERKi = comdat any
# | 
# | $_ZN7Awaiter11await_readyEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any
# | 
# | $_ZN7Awaiter12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type13final_suspendEv = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | @g_array = global [32 x i32] zeroinitializer, align 16
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local ptr @_Z6FooBarv() #0 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6
# |   store ptr @_Z6FooBarv.resume, ptr %call, align 8
# |   %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup
# |   %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8
# |   store ptr %0, ptr %destroy.addr, align 8
# |   %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18
# |   %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24
# |   %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32
# |   %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40
# |   %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48
# |   %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56
# |   %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19
# |   %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16
# |   %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call1, ptr %coerce.dive2, align 8
# |   call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   br i1 %call3, label %init.ready, label %CoroSave
# | 
# | CoroSave:                                         ; preds = %entry
# |   %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 0, ptr %index.addr39, align 1
# |   call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | init.ready:                                       ; preds = %entry
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   store ptr @g_array, ptr %__range1.reload.addr, align 8
# |   store ptr @g_array, ptr %__begin1.reload.addr, align 8
# |   store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %init.ready
# |   %1 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %2 = load ptr, ptr %__end1.reload.addr, align 8
# |   %cmp = icmp ne ptr %1, %2
# |   br i1 %cmp, label %for.body, label %coro.final
# | 
# | for.body:                                         ; preds = %for.cond
# |   %3 = load ptr, ptr %__begin1.reload.addr, align 8
# |   store ptr %3, ptr %x.reload.addr, align 8
# |   %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2
# |   %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4)
# |   %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0
# |   store ptr %call5, ptr %coerce.dive6, align 8
# |   %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   br i1 %call7, label %await.ready, label %CoroSave27
# | 
# | CoroSave27:                                       ; preds = %for.body
# |   %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 1, ptr %index.addr40, align 1
# |   %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call)
# |   %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0
# |   %7 = load ptr, ptr %6, align 8
# |   call void %7(ptr %5)
# |   br label %AfterCoroEnd
# | 
# | await.ready:                                      ; preds = %for.body
# |   call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   %cond = icmp eq i32 0, 0
# |   %cond26 = icmp eq i32 0, 0
# |   br i1 %cond26, label %for.inc, label %coro.final
# | 
# | for.inc:                                          ; preds = %await.ready
# |   %8 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1
# |   store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8
# |   br label %for.cond
# | 
# | coro.final:                                       ; preds = %await.ready, %for.cond
# |   call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7
# |   %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   br i1 %call20, label %final.ready, label %CoroSave31
# | 
# | CoroSave31:                                       ; preds = %coro.final
# |   store ptr null, ptr %call, align 8
# |   call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | final.ready:                                      ; preds = %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   %9 = icmp ne ptr %call, null
# |   br i1 %9, label %coro.free, label %AfterCoroEnd
# | 
# | coro.free:                                        ; preds = %final.ready
# |   call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7
# |   br label %AfterCoroEnd
# | 
# | AfterCoroEnd:                                     ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave
# |   %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0
# |   %10 = load ptr, ptr %coerce.dive25, align 8
# |   ret ptr %10
# | }
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %this.addr = alloca ptr, align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call, ptr %coerce.dive2, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false)
# |   %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0
# |   %0 = load ptr, ptr %coerce.dive4, align 8
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret i1 false
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 {
# | entry:
# |   %.addr = alloca ptr, align 8
# |   %.addr1 = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %0, ptr %.addr, align 8
# |   store ptr %1, ptr %.addr1, align 8
# |   %2 = load ptr, ptr %.addr, align 8
# |   %3 = load ptr, ptr %.addr1, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7
# |   
# | ...
# `---data was truncated (10240/37953) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# |  #0 0x000055b841987eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b841984e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b84198862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f390ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f390eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f390ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f390ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b84191dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b84191da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8419028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8415b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8415b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f390ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f390ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f390ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8415b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (15897 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_zt0() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_zt0() #1 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_zt0() #2 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_zt0() #3 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_zt0() #4 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_za_zt0() #5 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_za_zt0() #6 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_za_zt0() #7 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_za_zt0() #8 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_za_zt0() #9 {
# | entry:
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efef681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efef67ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efef68262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2277649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22776a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2277649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2277631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efef617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efef617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efef5fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efef2abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efef2abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2277632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22776330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22776330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efef2aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x0000557a6b8a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a6b89de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a6b8a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35b9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35b9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35b9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35b9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a6b836bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a6b836a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a6b81b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a6b4cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a6b4cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35b9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35b9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35b9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a6b4caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (15914 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %x.addr, align 8
# |   %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
# |   ret <8 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   %p.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   store <8 x i8> %p, ptr %p.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %p.addr, align 8
# |   %mask = and <8 x i8> %1, splat (i8 7)
# |   %shuf_idx = extractelement <8 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <8 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <8 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <8 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <8 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <8 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <8 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <8 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   ret <8 x i8> %shuf_ins21
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %x.addr, align 16
# |   %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
# |   ret <16 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %p.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store <16 x i8> %p, ptr %p.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %p.addr, align 16
# |   %mask = and <16 x i8> %1, splat (i8 15)
# |   %shuf_idx = extractelement <16 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <16 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <16 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <16 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <16 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <16 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <16 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <16 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   %shuf_idx22 = extractelement <16 x i8> %mask, i64 8
# |   %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22
# |   %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8
# |   %shuf_idx25 = extractelement <16 x i8> %mask, i64 9
# |   %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25
# |   %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9
# |   %shuf_idx28 = extractelement <16 x i8> %mask, i64 10
# |   %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28
# |   %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10
# |   %shuf_idx31 = extractelement <16 x i8> %mask, i64 11
# |   %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31
# |   %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11
# |   %shuf_idx34 = extractelement <16 x i8> %mask, i64 12
# |   %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34
# |   %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12
# |   %shuf_idx37 = extractelement <16 x i8> %mask, i64 13
# |   %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37
# |   %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13
# |   %shuf_idx40 = extractelement <16 x i8> %mask, i64 14
# |   %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40
# |   %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14
# |   %shuf_idx43 = extractelement <16 x i8> %mask, i64 15
# |   %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43
# |   %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15
# |   ret <16 x i8> %shuf_ins45
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561264821eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056126481ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056126482262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba63049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba630a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba63049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba63031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612647b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612647b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056126479c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056126444be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056126444bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba63032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba630330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba630330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056126444ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/builtins-arm.c (15993 of 27910)
******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-unknown-unknown-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @f0() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   %b.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load ptr, ptr %b.addr, align 4
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf0(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtr.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf1(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtru.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd0(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtr.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd1(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtru.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 0, ptr %res, align 4
# |   store volatile i32 1, ptr %res, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_barrier() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   call void @llvm.arm.dsb(i32 2)
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch(i32 noundef %i) #0 {
# | entry:
# |   %i.addr = alloca i32, align 4
# |   store i32 %i, ptr %i.addr, align 4
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp() #0 {
# | entry:
# |   call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp2() #0 {
# | entry:
# |   call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc2() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr2(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_lo
# | ...
# `---data was truncated (10240/15632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c236d34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c236d31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c236d3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe867e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe867ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe867e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe867e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c236ccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c236ccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c236caf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c23695ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c23695eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe867e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe867e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe867e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c23695ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/packed-structure.c (16126 of 27910)
******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | %struct.s0 = type { i32, i32 }
# | %struct.s1 = type { i32, i32 }
# | %struct.s2 = type { i32, i32 }
# | %struct.s3 = type <{ i16, i32, [10 x i8] }>
# | 
# | @s0_align_x = global i32 4, align 4
# | @s0_align_y = global i32 1, align 4
# | @s0_align = global i32 4, align 4
# | @s1_align_x = global i32 1, align 4
# | @s1_align_y = global i32 1, align 4
# | @s1_align = global i32 1, align 4
# | @s2_align_x = global i32 2, align 4
# | @s2_align_y = global i32 2, align 4
# | @s2_align = global i32 2, align 4
# | @s3_1 = global i32 1, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @test3(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %anInt, align 2
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# |  #0 0x000055dd870aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd870a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd870ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa425049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa425049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa425031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd87042bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd87042a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd870278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd86cd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd86cd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa425032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4250330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd86cd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (16455 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vsqrth_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %vsqrt, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %__s2 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load half, ptr %__s0, align 2
# |   %4 = load half, ptr %__s1, align 2
# |   %5 = load half, ptr %__s2, align 2
# |   %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %6, ptr %ref.tmp, align 2
# |   %7 = load half, ptr %ref.tmp, align 2
# |   store half %7, ptr %__ret, align 2
# |   %8 = load half, ptr %__ret, align 2
# |   store half %8, ptr %tmp, align 2
# |   %9 = load half, ptr %tmp, align 2
# |   ret half %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# |  #0 0x00005564af7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564af7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564af7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfab31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564af791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564af791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564af7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564af425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564af425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfab31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564af425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/arm-cde-gpr.c (16563 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 {
# | entry:
# |   %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
# |   %1 = extractvalue { i32, i32 } %0, 1
# |   %2 = zext i32 %1 to i64
# |   %3 = shl i64 %2, 32
# |   %4 = extractvalue { i32, i32 } %0, 0
# |   %5 = zext i32 %4 to i64
# |   %6 = or i64 %3, %5
# |   ret i64 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33)
# |   %2 = extractvalue { i32, i32 } %1, 1
# |   %3 = zext i32 %2 to i64
# |   %4 = shl i64 %3, 32
# |   %5 = extractvalue { i32, i32 } %1, 0
# |   %6 = zext i32 %5 to i64
# |   %7 = or i64 %4, %6
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3)
# |   %3 = extractvalue { i32, i32 } %2, 1
# |   %4 = zext i32 %3 to i64
# |   %5 = shl i64 %4, 32
# |   %6 = extractvalue { i32, i32 } %2, 0
# |   %7 = zext i32 %6 to i64
# |   %8 = or i64 %5, %7
# |   ret i64 %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = load i32, ptr %m.addr, align 4
# |   %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c702ac1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c702abee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c702ac262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7128849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7128849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7128831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c702a57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c702a57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c702a3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7026ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7026ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7128832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71288330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7026eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (16769 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp sle i32 %2, %3
# |   %sle.i = zext i1 %4 to i32
# |   ret i32 %sle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp ule i32 %2, %3
# |   %sleu.i = zext i1 %4 to i32
# |   ret i32 %sleu.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = sext i16 %1 to i32
# |   %exths.i = sext i16 %1 to i32
# |   ret i32 %exths.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = zext i16 %1 to i32
# |   %exthz.i = zext i16 %1 to i32
# |   ret i32 %exthz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = sext i8 %1 to i32
# |   %extbs.i = sext i8 %1 to i32
# |   ret i32 %extbs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = zext i8 %1 to i32
# |   %extbz.i = zext i8 %1 to i32
# |   ret i32 %extbz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   st
# | ...
# `---data was truncated (10240/15696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559357896eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559357893e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055935789762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44b2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055935782cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055935782ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593578118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593574c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593574c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44b24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593574c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (16790 of 27910)
******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - |     /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | @X = global i32 0, align 4
# | @Y = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @foo() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %i = alloca i32, align 4
# |   store i32 0, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %entry
# |   %0 = load i32, ptr %i, align 4
# |   %cmp = icmp slt i32 %0, 100
# |   br i1 %cmp, label %for.body, label %for.end
# | 
# | for.body:                                         ; preds = %for.cond
# |   br label %for.end
# | 
# | for.inc:                                          ; No predecessors!
# |   %1 = load i32, ptr %i, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.end:                                          ; preds = %for.body, %for.cond
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type]
# |    13 | }
# |       | ^
# | 1 warning generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# |  #0 0x000055a4f6f92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4f6f8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4f6f9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63edf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63edf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63edf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63edf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4f6f28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4f6f28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4f6f0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4f6bbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4f6bbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63edf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63edf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63edf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4f6bbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (16845 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg             | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vaddh = fadd half %2, %3
# |   store half %vaddh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vsubh = fsub half %2, %3
# |   store half %vsubh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmulh = fmul half %2, %3
# |   store half %vmulh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vdivh = fdiv half %2, %3
# |   store half %vdivh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3)
# |   store half %vmax, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3)
# |   store half %vmaxnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3)
# |   store half %vmin, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3)
# |   store half %vminnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabsh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vabs = call half @llvm.fabs.f16(half %1)
# |   store half %vabs, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.fabs.f16(half) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = all
# | ...
# `---data was truncated (10240/27802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561616ba4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561616ba1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561616ba562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67b4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67b418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67b4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67b411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561616b3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561616b3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561616b1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616167cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616167ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67b411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67b411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67b411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616167cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (16859 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1)
# |   ret float %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1)
# |   ret double %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1)
# |   ret float %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1)
# |   ret double %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1)
# |   ret float %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1)
# |   ret double %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1)
# |   ret float %frint64x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1)
# |   ret double %frint64x.i
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32x.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64x.f64(double) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056132851deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056132851ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056132851e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7708733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f770878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7708733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f770871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613284b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613284b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613284988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561328147e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561328147b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f770871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f770871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f770871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561328147a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (17068 of 27910)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1
# | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fde73feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fde73ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fde74062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56a3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56a3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56a3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56a3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fde6d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fde6d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fde6ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fde369e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fde369b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56a3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56a3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56a3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fde369a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (17078 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i8 @subscript_int8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i8 @subscript_uint8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i16 @subscript_int16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i16 @subscript_uint16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_int32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_uint32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 2 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 1 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> %a.coerce, i64 0)
# |   store <4 x double> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x double>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b8ffe97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8ffe94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8ffe9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fdc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fdc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fdc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fdc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8ffe2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8ffe2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8ffe128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8ffac1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8ffac1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fdc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fdc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fdc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8ffac1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (17263 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.abs.i32(i32 %0, i1 true)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.abs.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp sle i32 %0, %1
# |   %sle = zext i1 %2 to i32
# |   ret i32 %sle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp ule i32 %0, %1
# |   %sleu = zext i1 %2 to i32
# |   ret i32 %sleu
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = sext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exths = sext i16 %1 to i32
# |   ret i32 %exths
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = zext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exthz = zext i16 %1 to i32
# |   ret i32 %exthz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = sext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbs = sext i8 %1 to i32
# |   ret i32 %extbs
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = zext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbz = zext i8 %1 to i32
# |   ret i32 %extbz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xcvalu1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564868d13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564868d10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564868d1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e02d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e02d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e02d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e02d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564868ca9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564868ca9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564868c8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056486893de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056486893db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e02d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e02d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e02d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056486893da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/arm-cde-vfp.c (17419 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 {
# | entry:
# |   %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
# |   %1 = bitcast float %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = load i32, ptr %m.addr, align 4
# |   %5 = bitcast i32 %4 to float
# |   %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5)
# |   %7 = bitcast float %6 to i32
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 {
# | entry:
# |   %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
# |   %1 = bitcast double %0 to i64
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %m.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = load i64, ptr %m.addr, align 8
# |   %5 = bitcast i64 %4 to double
# |   %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5)
# |   %7 = bitcast double %6 to i64
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4c2347eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4c2344e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4c234862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dc5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dc5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dc5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dc5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4c22ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4c22dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4c22c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4c1f71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4c1f71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1dc5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dc5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dc5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4c1f71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (17432 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c  -check-prefix=RV32ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559d57c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559d57c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559d57c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f76049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f76049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f76031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559d575cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559d575ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559d57418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559d53f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559d53f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f76032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f760330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559d53f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (17477 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f8a95aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f8a957e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f8a95b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc343533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc34358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc343533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc34351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f8a8f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f8a8f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f8a8d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f8a584e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f8a584b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc34351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc34351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc34351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f8a584a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (17506 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c  -check-prefix=RV32XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clo_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056093e19beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056093e198e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056093e19c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0879e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0879ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0879e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0879e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056093e131bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056093e131a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056093e1168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056093ddc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056093ddc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0879e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0879e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0879e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056093ddc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (17594 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c  -check-prefix=RV64ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64es(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64esm(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056492fcddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056492fcdae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056492fcde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67fb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67fb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67fb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67fb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056492fc73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056492fc73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056492fc588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056492f907e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056492f907b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67fb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67fb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67fb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056492f907a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (17741 of 27910)
******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c"
# | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128"
# | target triple = "i386-apple-darwin10"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke_copy_to_stack() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 {
# | entry:
# |   %that.addr = alloca ptr, align 4
# |   %methodIndex.addr = alloca i32, align 4
# |   %paramCount.addr = alloca i32, align 4
# |   %params.addr = alloca ptr, align 4
# |   store ptr %that, ptr %that.addr, align 4
# |   store i32 %methodIndex, ptr %methodIndex.addr, align 4
# |   store i32 %paramCount, ptr %paramCount.addr, align 4
# |   store ptr %params, ptr %params.addr, align 4
# |   call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
# | attributes #1 = { nounwind }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"NumRegisterParameters", i32 0}
# | !1 = !{!"clang version 24.0.0"}
# | !2 = !{i64 1623}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# |  #0 0x0000564f25d83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f25d80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f25d8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd17449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd17449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd17431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f25d19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f25d19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f25cfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f259ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f259adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd17432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f259ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (17772 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c5909aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c59097e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c5909b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9936333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9936333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f993631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c59030bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c59030a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c590158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c58cc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c58cc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f993631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f993631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f993631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c58cc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (17810 of 27910)
******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-none-elf"
# | 
# | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any
# | 
# | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any
# | 
# | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any
# | 
# | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{i32 1, !5}
# | !5 = !{!"aarch64.mem_hint", i32 0}
# | !6 = !{i32 1, !7}
# | !7 = !{!"aarch64.mem_hint", i32 1}
# | !8 = !{i32 0, !9}
# | !9 = !{!"aarch64.mem_hint", i32 3}
# | !10 = !{i32 0, !11}
# | !11 = !{!"aarch64.mem_hint", i32 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b50ca26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b50ca23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b50ca2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0c9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0c998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0c9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0c991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b50c9bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b50c9bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b50c9a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b50c650e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b50c650b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0c991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0c991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0c991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b50c650a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/arm-cde-vec.c (17834 of 27910)
******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 {
# | entry:
# |   %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %acc, ptr %acc.addr, align 8
# |   %0 = load <4 x i32>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113)
# |   %3 = bitcast <16 x i8> %2 to <4 x i32>
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <8 x half>, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   %0 = load <8 x half>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <4 x float>, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %n.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112)
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <2 x i64>, align 8
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = load <2 x i64>, ptr %n.addr, align 8
# |   %3 = bitcast <2 x i64> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113)
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x i32> %m, ptr %m.addr, align 8
# |   %0 = load <8 x i16>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <16 x i8>
# |   %2 = load <4 x i32>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x i32> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <2 x i64>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <2 x i64>, ptr %n.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %2 = load <4 x float>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12)
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load <8 x i16>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x i16> %1 to <16 x i8>
# |   %3 = load <4 x float>, ptr %m.addr, align 8
# |   %4 = bitcast <4 x float> %3 to <16 x i8>
# |   %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %n.addr, align 8
# |   %2 = bitcast <4 x float> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = load <8 x half>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x half> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %m.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# | ...
# `---data was truncated (10240/13030) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645e3f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645e3f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645e3f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645e3ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645e3ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645e3ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645e3b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645e3b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84c291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645e3b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (18396 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c  -check-prefix=RV64XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %not = xor i64 %0, -1
# |   %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa0a729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa0a726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa0a72a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62da105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62da15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62da105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62da0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa0a6bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa0a6bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa0a6a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa0a353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa0a353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62da0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62da0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62da0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa0a353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (18500 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-unknown-linux-gnu"
# | 
# | @__riscv_cpu_model = external dso_local global { i32, i64, i64 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1808
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372035378380799
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 1152921505839391232
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775800
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 102892581
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775543
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 337970694
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560706a24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560706a21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560706a2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2a9e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2a9e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2a9e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2a9e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607069babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607069baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056070699f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056070664ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056070664eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2a9e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2a9e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2a9e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056070664ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (18714 of 27910)
******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | @con_unify_unimap_p1 = global ptr null, align 8
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @con_unify_unimap_q1() #0 {
# | entry:
# |   %p.addr.i = alloca ptr, align 8
# |   %q.addr.i = alloca ptr, align 8
# |   %size.addr.i = alloca i64, align 8
# |   %0 = load ptr, ptr @con_unify_unimap_p1, align 8
# |   store ptr %0, ptr %p.addr.i, align 8
# |   store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8
# |   store i64 4, ptr %size.addr.i, align 8
# |   %1 = load ptr, ptr %p.addr.i, align 8
# |   %2 = load ptr, ptr %q.addr.i, align 8
# |   %3 = load i64, ptr %size.addr.i, align 8
# |   %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2
# |   ret i32 %call.i
# | }
# | 
# | ; Function Attrs: alwaysinline nobuiltin nounwind
# | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #2 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# |  #0 0x0000555ab3128eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ab3125e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ab312962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe256f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe256f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe256f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe256f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ab30bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ab30bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ab30a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ab2d52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ab2d52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe256f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe256f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe256f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ab2d52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (18844 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563056fdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563056fd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563056fdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b0d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b0d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563056f72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563056f72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563056f578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563056c06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563056c06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b0d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563056c06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (18860 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c  -check-prefix=RV32ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ba99b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ba99b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ba99b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc94b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc94b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc94b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc94b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ba994bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ba994ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ba99308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ba95dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ba95dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc94b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc94b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc94b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ba95dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (18895 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c  -check-prefix=RV64ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055629f336eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055629f333e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055629f33762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3e671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055629f2ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055629f2cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055629f2b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055629ef60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055629ef60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3e671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055629ef60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (18904 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c  -check-prefix=RV32ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad30e1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad30e19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad30e1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d9b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d9b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d9b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad30db2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad30db2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad30d978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad30a46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad30a46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d9b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d9b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d9b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad30a46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (18926 of 27910)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.funcref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615bdeb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615bdeaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615bdeb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615bde47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615bde47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615bde2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615bdadbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615bdadbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2f7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615bdadba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (18983 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055615e89beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055615e898e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055615e89c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbb9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbb9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbb9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbb9aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055615e831bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055615e831a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055615e8168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055615e4c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055615e4c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbb9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbb9aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbb9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055615e4c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (19806 of 27910)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c  -check-prefix=RV64ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64im(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.aes64im(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ds(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64im(i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055594ed70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055594ed6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055594ed7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8593849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85938a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8593849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8593831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055594ed06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055594ed06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055594eceb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055594e99ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055594e99ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8593832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85938330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85938330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055594e99aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (19823 of 27910)
******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type { ptr, ptr, %struct.A }
# | %struct.A = type { i32 }
# | 
# | $_ZTV1B = comdat any
# | 
# | $_ZTI1B = comdat any
# | 
# | $_ZTS1B = comdat any
# | 
# | $_ZTI1A = comdat any
# | 
# | $_ZTS1A = comdat any
# | 
# | @y = local_unnamed_addr global i8 2, align 1
# | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8
# | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
# | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8
# | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr]
# | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1
# | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8
# | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr]
# | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000055931093eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055931093be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055931093f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11e3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11e378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11e3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11e371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593108d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593108d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593108b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559310568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559310568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11e371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11e371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11e371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559310568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (20989 of 27910)
******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm    /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   %fpext = fpext bfloat %0 to float
# |   %fptrunc = fptrunc float %fpext to half
# |   ret half %fptrunc
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %fpext = fpext half %0 to float
# |   %fptrunc = fptrunc float %fpext to bfloat
# |   ret bfloat %fptrunc
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2fcd5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2fcd5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2fcd6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a28449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a284a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a28449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a28431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2fccf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2fccf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2fccda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2fc989e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2fc989b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a28432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a284330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a284330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2fc989a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. 
********************
Failed Tests (3297):
  Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c
  Clang :: CodeGen/2005-09-24-AsmUserPrefix.c
  Clang :: CodeGen/2008-07-17-no-emit-on-error.c
  Clang :: CodeGen/AArch64/atomic-hint-template.cpp
  Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c
  Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c
  Clang :: CodeGen/AArch64/fp8-cast.c
  Clang :: CodeGen/AArch64/fp8-extract.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/neon-2velem.c
  Clang :: CodeGen/AArch64/neon-3v.c
  Clang :: CodeGen/AArch64/neon-dot-product.c
  Clang :: CodeGen/AArch64/neon-extract.c
  Clang :: CodeGen/AArch64/neon-fma.c
  Clang :: CodeGen/AArch64/neon-fp16fml.c
  Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon-intrinsics.c
  Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c
  Clang :: CodeGen/AArch64/neon-misc-constrained.c
  Clang :: CodeGen/AArch64/neon-misc.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c
  Clang :: CodeGen/AArch64/neon-shifts.c
  Clang :: CodeGen/AArch64/neon-tbl.c
  Clang :: CodeGen/AArch64/neon-vcmla.c
  Clang :: CodeGen/AArch64/neon-vcombine.c
  Clang :: CodeGen/AArch64/neon-vget-hilo.c
  Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c
  Clang :: CodeGen/AArch64/neon/add.c
  Clang :: CodeGen/AArch64/neon/bf16-getset.c
  Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c
  Clang :: CodeGen/AArch64/neon/f16-getset.c
  Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiply.c
  Clang :: CodeGen/AArch64/neon/getset.c
  Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon/intrinsics.c
  Clang :: CodeGen/AArch64/neon/load.c
  Clang :: CodeGen/AArch64/neon/perm.c
  Clang :: CodeGen/AArch64/neon/rounding-v8.5.c
  Clang :: CodeGen/AArch64/neon/rounding.c
  Clang :: CodeGen/AArch64/neon/store.c
  Clang :: CodeGen/AArch64/neon/subtraction.c
  Clang :: CodeGen/AArch64/neon/vpaddl.c
  Clang :: CodeGen/AArch64/neon/widen.c
  Clang :: CodeGen/AArch64/poly128.c
  Clang :: CodeGen/AArch64/poly64.c
  Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
  Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
  Clang :: CodeGen/AArch64/sve-vector-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vector-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vector-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c
  Clang :: CodeGen/AArch64/sve-vls-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vls-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vls-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c
  Clang :: CodeGen/AArch64/sve/addv.c
  Clang :: CodeGen/AArch64/sve/andv.c
  Clang :: CodeGen/AArch64/sve/dup.c
  Clang :: CodeGen/AArch64/sve/eorv.c
  Clang :: CodeGen/AArch64/sve/len.c
  Clang :: CodeGen/AArch64/sve/maxnmv.c
  Clang :: CodeGen/AArch64/sve/maxv.c
  Clang :: CodeGen/AArch64/sve/minnmv.c
  Clang :: CodeGen/AArch64/sve/minv.c
  Clang :: CodeGen/AArch64/sve/nand.c
  Clang :: CodeGen/AArch64/sve/nor.c
  Clang :: CodeGen/AArch64/sve/orn.c
  Clang :: CodeGen/AArch64/sve/orv.c
  Clang :: CodeGen/AArch64/sve/pfalse.c
  Clang :: CodeGen/AArch64/sve/recpe.c
  Clang :: CodeGen/AArch64/sve/recps.c
  Clang :: CodeGen/AArch64/sve/rsqrte.c
  Clang :: CodeGen/AArch64/sve/rsqrts.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
  Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
  Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
  Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/builtin-cpu-is.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c
  Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c
  Clang :: CodeGen/RISCV/riscv-xcvalu.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c
  Clang :: CodeGen/RISCV/rvp-intrinsics.c
  Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/SystemZ/zvector.c
  Clang :: CodeGen/WebAssembly/builtins-table-externref.c
  Clang :: CodeGen/WebAssembly/builtins-table-funcref.c
  Clang :: CodeGen/X86/avx-cmp-builtins.c
  Clang :: CodeGen/X86/avx-shuffle-builtins.c
  Clang :: CodeGen/X86/bfloat16-convert-half.c
  Clang :: CodeGen/X86/sse.c
  Clang :: CodeGen/aapcs-bitfield.c
  Clang :: CodeGen/arm-bf16-convert-intrinsics.c
  Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c
  Clang :: CodeGen/arm-bf16-params-returns.c
  Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/arm-cde-gpr.c
  Clang :: CodeGen/arm-cde-reinterpret.c
  Clang :: CodeGen/arm-cde-vec.c
  Clang :: CodeGen/arm-cde-vfp.c
  Clang :: CodeGen/arm-crc32.c
  Clang :: CodeGen/arm-mfp8.c
  Clang :: CodeGen/arm-mve-intrinsics/absneg.c
  Clang :: CodeGen/arm-mve-intrinsics/admin.c
  Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/compare.c
  Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp
  Clang :: CodeGen/arm-mve-intrinsics/dup.c
  Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c
  Clang :: CodeGen/arm-mve-intrinsics/idup.c
  Clang :: CodeGen/arm-mve-intrinsics/load-store.c
  Clang :: CodeGen/arm-mve-intrinsics/predicates.c
  Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c
  Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c
  Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c
  Clang :: CodeGen/arm-mve-intrinsics/ternary.c
  Clang :: CodeGen/arm-mve-intrinsics/vabavq.c
  Clang :: CodeGen/arm-mve-intrinsics/vabdq.c
  Clang :: CodeGen/arm-mve-intrinsics/vadc.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddv.c
  Clang :: CodeGen/arm-mve-intrinsics/vandq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbicq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vclz.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c
  Clang :: CodeGen/arm-mve-intrinsics/veorq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vld24.c
  Clang :: CodeGen/arm-mve-intrinsics/vldr.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminvq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovl.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vornq.c
  Clang :: CodeGen/arm-mve-intrinsics/vorrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrev.c
  Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrnd.c
  Clang :: CodeGen/arm-mve-intrinsics/vshlc.c
  Clang :: CodeGen/arm-mve-intrinsics/vsubq.c
  Clang :: CodeGen/arm-neon-directed-rounding-constrained.c
  Clang :: CodeGen/arm-neon-directed-rounding.c
  Clang :: CodeGen/arm-neon-dot-product.c
  Clang :: CodeGen/arm-neon-endianness.c
  Clang :: CodeGen/arm-neon-fma.c
  Clang :: CodeGen/arm-neon-numeric-maxmin.c
  Clang :: CodeGen/arm-neon-shifts.c
  Clang :: CodeGen/arm-neon-vcadd.c
  Clang :: CodeGen/arm-neon-vcvtX.c
  Clang :: CodeGen/arm-neon-vget.c
  Clang :: CodeGen/arm-neon-vld.c
  Clang :: CodeGen/arm-neon-vst.c
  Clang :: CodeGen/arm-poly-add.c
  Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c
  Clang :: CodeGen/arm-vector_type-params-returns.c
  Clang :: CodeGen/arm64-crc32.c
  Clang :: CodeGen/arm64-lanes.c
  Clang :: CodeGen/arm64_vcopy.c
  Clang :: CodeGen/arm64_vcreate.c
  Clang :: CodeGen/arm64_vdupq_n_f64.c
  Clang :: CodeGen/arm_acle.c
  Clang :: CodeGen/arm_acle_swp.c
  Clang :: CodeGen/arm_neon_intrinsics.c
  Clang :: CodeGen/attr-counted-by-issue200014.c
  Clang :: CodeGen/builtin-align.c
  Clang :: CodeGen/builtins-arm-exclusive.c
  Clang :: CodeGen/builtins-arm.c
  Clang :: CodeGen/builtins-arm64.c
  Clang :: CodeGen/builtins-loongarch.c
  Clang :: CodeGen/builtins-riscv.c
  Clang :: CodeGen/cx-complex-range-real.c
  Clang :: CodeGen/cx-complex-range.c
  Clang :: CodeGen/distributed-thin-lto/backend-skip.ll
  Clang :: CodeGen/distributed-thin-lto/basic.ll
  Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll
  Clang :: CodeGen/distributed-thin-lto/cfi.ll
  Clang :: CodeGen/distributed-thin-lto/newpm.ll
  Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll
  Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
  Clang :: CodeGen/linker-diagnostic.ll
  Clang :: CodeGen/memcmp-inline-builtin-to-asm.c
  Clang :: CodeGen/mozilla-ms-inline-asm.c
  Clang :: CodeGen/packed-structure.c
  Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
  Clang :: CodeGen/thinlto-funcattr-prop.ll
  Clang :: CodeGen/thinlto-multi-module.ll
  Clang :: CodeGen/thinlto-opaque-typed-mix.ll
  Clang :: CodeGen/thinlto_backend.ll
  Clang :: CodeGen/thinlto_backend_local_name_conflict.ll
  Clang :: CodeGen/thinlto_embed_bitcode.ll
  Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
  Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
  Clang :: CodeGenCXX/attr-musttail.cpp
  Clang :: CodeGenCXX/ctor-globalopt.cpp
  Clang :: CodeGenCXX/inline-then-fold-variadics.cpp
  Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll
  Clang :: CodeGenCXX/virtual-base-ctor.cpp
  Clang :: CodeGenCoroutines/coro-gro4.cpp
  Clang :: CodeGenCoroutines/pr65054.cpp
  Clang :: CodeGenHIP/offload-pgo-sections.hip
  Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
  Clang :: Modules/pr93497.cppm


Testing Time: 178.38s

Total Discovered Tests: 55926
  Skipped          :    37 (0.07%)
  Unsupported      :  1675 (3.00%)
  Passed           : 50888 (90.99%)
  Expectedly Failed:    29 (0.05%)
  Failed           :  3297 (5.90%)
FAILED: gen/clang/test/run-lit 
python3 bin/llvm-lit -sv ../../clang/test
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.